An image sensor and a method of forming an image sensor

Abstract

The embodiment of the present disclosure relates to the field of image sensors, and provides an image sensor, comprising: a substrate; a first transistor and a second transistor, the first transistor and the second transistor sharing one source or drain, and at least the first transistor being a junction transistor; the first transistor comprising: a first doped region and a second doped region; a first channel region located between the first doped region and the second doped region; a third doped region surrounding the first channel region; the first channel region extending along a first direction or a second direction, the first direction being parallel to the surface of the substrate, and the second direction being perpendicular to the surface of the substrate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to an image sensor and a forming method of the image sensor. BACKGROUND

[0002] The source follower in current CMOS image sensors is usually a metal-oxide semiconductor field effect transistor (MOSFET), in which structure, the change of the gate voltage will affect the change of the source voltage or current, and by detecting the change, the amount of photo-generated charge of the photodiode can be known. This process is often accompanied by noise, in which the transient noise plays a major role at low frequencies, and the transient noise is generated due to the capture and release of electrons and holes in the channel by the Si and SiO2 interface, which will weaken the gate control ability and reduce the conversion gain. SUMMARY

[0003] Embodiments of the present disclosure provide an image sensor and a forming method of the image sensor, which at least reduce the transient noise and solve the problems of weakening the gate control ability and reducing the conversion gain caused by the transient noise.

[0004] According to some embodiments of the present disclosure, the present disclosure provides an image sensor, comprising: a substrate;

[0005] A first transistor and a second transistor, the first transistor and the second transistor share one source or drain, and at least the first transistor is a junction transistor;

[0006] The first transistor comprises: a first doped region and a second doped region; a first channel region between the first doped region and the second doped region; and a third doped region surrounding the first channel region.

[0007] The first channel region extends along a first direction or a second direction, the first direction is parallel to the surface of the substrate, and the second direction is perpendicular to the surface of the substrate.

[0008] In some embodiments, the first channel region extends along the second direction, the second doped region comprises a first sub-doped region and a second sub-doped region, the first sub-doped region is located below the first doped region and parallel to the surface of the substrate, and the second sub-doped region extends along the second direction and is electrically connected to the first sub-doped region.

[0009] In some embodiments, the first isolation structure and the second isolation structure are between the second sub-doped region and the third doped region, the first isolation structure and the second isolation structure have a first pad therebetween, the first isolation structure extends from the top of the substrate to below the first doped region, and the second isolation structure extends from the top of the substrate to the first sub-doped region; a depth of the first isolation structure along the second direction is greater than a depth of the first doped region along the second direction and less than a depth of the second isolation structure along the second direction.

[0010] In some embodiments, the first doped region and the second doped region have a same doping type, the first channel region has a same doping type as the first doped region and the second doped region, and the third doped region has an opposite doping type as the first channel region; a doping concentration of the first channel region is less than a doping concentration of the first doped region and the second doped region.

[0011] In some embodiments, the second transistor is a metal-oxide-semiconductor field effect transistor, and the second transistor further includes a gate and a fourth doped region, the gate is located on the substrate and is adjacent to the first doped region, and the fourth doped region is located on a side of the gate away from the first doped region; a doping depth of the fourth doped region is less than a doping depth of the first doped region.

[0012] In some embodiments, the second transistor is a junction transistor, and the second transistor further includes a fourth doped region and a second channel region, the second channel region is located between the first doped region and the fourth doped region, and a fifth doped region is arranged around the second channel region; the second channel region extends along the first direction or the second direction.

[0013] In some embodiments, the second channel region extends along the second direction, the fourth doped region includes a third sub-doped region and a fourth sub-doped region, the third sub-doped region is located below the first doped region and parallel to the surface of the substrate, and the fourth sub-doped region extends along the second direction and is electrically connected to the third sub-doped region.

[0014] In some embodiments, the fourth sub-doped region and the fifth doped region have a second isolation structure therebetween, the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure; the third sub-isolation structure and the fourth sub-isolation structure have a second pad therebetween, the third sub-isolation structure extends from the top of the substrate to below the first doped region, and the fourth sub-isolation structure extends from the top of the substrate to the third sub-doped region; a depth of the third sub-isolation structure along the second direction is greater than a depth of the first doped region along the second direction and less than a depth of the fourth sub-isolation structure along the second direction.

[0015] In some embodiments, the fifth doped region and the third doped region further have a third isolation structure therebetween, and a depth of the third isolation structure is not less than a depth of the first channel region or the second channel region.

[0016] Another aspect of the embodiments of the present disclosure provides a forming method of an image sensor, comprising:

[0017] providing a substrate;

[0018] forming a first transistor and a second transistor, the first transistor and the second transistor sharing one source or drain, at least the first transistor being a junction transistor;

[0019] the first transistor comprises: a first doped region and a second doped region; a first channel region between the first doped region and the second doped region; a third doped region surrounding the first channel region;

[0020] the first channel region extends along a first direction or a second direction, the first direction being parallel to a surface of the substrate, the second direction being perpendicular to the surface of the substrate.

[0021] In some embodiments, the first channel region extends along the first direction, and the forming method of the first transistor at least comprises: performing a first doping and a second doping on the substrate to form the first doped region and the second doped region, the first channel region being formed between the first doped region and the second doped region; and performing a third doping on the first channel region to form the third doped region.

[0022] In some embodiments, the first channel region extends along the first direction, and the forming method of the first transistor at least comprises: forming a first initial doped region, a top surface of the first initial doped region being spaced apart from a top surface of the substrate by a first distance; forming a second initial doped region on the first initial doped region; forming a third initial doped region on a top portion of the second initial doped region; forming a fourth initial doped region on a side portion of the second initial doped region; the first initial doped region, the third initial doped region, and the fourth initial doped region collectively forming the third doped region, the third doped region surrounding the second initial doped region, a doping type of the third doped region being opposite to a doping type of the second initial doped region, the second initial doped region serving as the first channel region; and forming the first doped region and the second doped region at two ends of the third doped region.

[0023] In some embodiments, the first channel region extends along the first direction, and the forming method of the first transistor at least comprises: forming a fifth initial doped region, the fifth initial doped region extending from a surface of the substrate to the substrate, a bottom portion of the fifth initial doped region being spaced apart from the surface of the substrate by a second distance; forming a sixth initial doped region in the fifth initial doped region, a doping type of the fifth initial doped region being opposite to a doping type of the sixth initial doped region, the sixth initial doped region serving as the first channel region, a remaining portion of the fifth initial doped region surrounding the first channel region, the remaining portion of the fifth initial doped region serving as the third doped region; and forming the first doped region and the second doped region at two ends of the third doped region.

[0024] In some embodiments, the first channel region extends along the second direction, and the method for forming the first transistor at least includes: forming a second doping region, the second doping region including a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region; forming a seventh initial doping region on the first sub-doping region, the seventh initial doping region serves as the first channel region, and is doped around the first channel region to form a third doping region; forming a first doping region on the third doping region and the first channel region; a first isolation structure is formed between the second sub-doping region and the third doping region, the first isolation structure including a first sub-isolation structure and a second sub-isolation structure; a first pad is formed between the first sub-isolation structure and the second sub-isolation structure, the first sub-isolation structure extends from the top of the substrate to below the first doping region, and the second sub-isolation structure extends from the top of the substrate to the first sub-doping region; the depth of the first sub-isolation structure along the second direction is greater than the depth of the first doping region along the second direction and less than the depth of the second sub-isolation structure along the second direction.

[0025] In some embodiments, the first channel region extends along the second direction, and the method for forming the first transistor at least includes: forming a second doping region, the second doping region including a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region; forming an eighth initial doping region on the first sub-doping region, the eighth initial doping region extends from the top surface of the substrate to the first sub-doping region, and a ninth initial doping region is formed in the eighth initial doping region, the eighth initial doping is opposite to the doping type of the ninth initial doping region, the ninth initial doping region serves as the first channel region, the remaining eighth initial doping region surrounds the first channel region, the remaining eighth initial doping region serves as the third doping region, and the first doping region is formed on the top of the third doping region.

[0026] In some embodiments, the second transistor is a metal oxide semiconductor field effect transistor, and the method for forming the second transistor also includes forming a gate, the gate is located on the substrate, and the gate is adjacent to the first doped region; a fourth doped region is formed on the side of the gate away from the first doped region, and the doping depth of the fourth doped region is less than the doping depth of the first doped region.

[0027] In some embodiments, the second transistor is a junction transistor, and the second transistor also includes a fourth doping region and a second channel region, the second channel region is located between the first doping region and the fourth doping region, the fifth doping region is arranged around the second channel region, and the second channel region extends along the first direction or the second direction.

[0028] In some embodiments, the second channel region extends along the second direction, the fourth doped region includes a third sub-doped region and a fourth sub-doped region, the third sub-doped region is located below the first doped region and parallel to the substrate surface, and the fourth sub-doped region extends along the second direction and is electrically connected with the third sub-doped region.

[0029] In some embodiments, a second isolation structure is formed between the fourth sub-doped region and the fifth doped region, the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure, the third sub-isolation structure has a second pad between the third sub-isolation structure and the fourth sub-isolation structure, the third sub-isolation structure extends from the top of the substrate to below the first doped region, and the fourth sub-isolation structure extends from the top of the substrate to the third sub-doped region; the depth of the third sub-isolation structure along the second direction is greater than the depth of the first doped region along the second direction and less than the depth of the fourth sub-isolation structure along the second direction.

[0030] In some embodiments, a third isolation structure is further formed between the fifth doped region and the third doped region, and the depth of the third isolation structure is not less than the depth of the first channel region or the second channel region.

[0031] The technical scheme provided by the embodiments of the present disclosure has at least the following advantages: the source follower transistor is changed from a MOSFET transistor to a JFET transistor, the conduction of the JFET needs a PN field effect, and does not need an oxide field effect, so that the instantaneous noise caused by the capture and release of carriers at the Si and / SiO2 interface can be removed, and the gate control ability of the source follower transistor is enhanced, and the conversion gain is increased. BRIEF DESCRIPTION OF DRAWINGS

[0032] One or more embodiments are illustrated by way of example in the drawings that are not intended to be limiting of the embodiments so far as they are in conformity with the legal requirements, and the drawings are not necessarily drawn to scale, except as expressly indicated in the specification. In order to clearly illustrate the technical solutions of the embodiments or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0033] Figure 1 A schematic diagram of an image sensor is provided for an embodiment of the present disclosure;

[0034] Figure 1 a 、 Figure 1 b A schematic diagram of an image sensor is provided for an embodiment of the present disclosure; Figure 1 A schematic diagram of an image sensor is provided for an embodiment of the present disclosure;

[0035] Figure 2 A schematic diagram of an image sensor is provided for an embodiment of the present disclosure; Figure 1 A schematic diagram of an image sensor is provided for an embodiment of the present disclosure;

[0036] Figure 3 a circuit connection schematic diagram of an image sensor provided by an embodiment of the present disclosure;

[0037] Figure 4 a schematic diagram of an image sensor provided by another embodiment of the present disclosure;

[0038] Figure 5 a top view of Figure 4 ;

[0039] Figure 6 a circuit connection schematic diagram of an image sensor provided by another embodiment of the present disclosure;

[0040] Figure 7 a schematic diagram of an image sensor provided by still another embodiment of the present disclosure;

[0041] Figure 7a , Figure 7b a sectional view along the Y-Y' direction of Figure 7 ;

[0042] Figure 8 a top view of Figure 7 ;

[0043] Figure 9 a circuit connection schematic diagram of an image sensor provided by still another embodiment of the present disclosure;

[0044] Figure 10 a schematic diagram of an image sensor provided by yet another embodiment of the present disclosure;

[0045] Figure 11 a top view of Figure 10 ;

[0046] Figure 12 a circuit connection schematic diagram of an image sensor provided by yet another embodiment of the present disclosure;

[0047] Figure 13 a circuit diagram of an image sensor provided by the present disclosure;

[0048] Figure 14a to Figure 14c a process flow chart of a method for manufacturing an image sensor provided by an embodiment of the present disclosure, Figure 14d a sectional view along the Z-Z' direction of Figure 14c ;

[0049] Figure 15a to Figure 15d a process flow chart of a method for manufacturing an image sensor provided by another embodiment of the present disclosure, Figure 15e a sectional view along the Z-Z' direction of Figure 14d ;

[0050] Figure 16a to Figure 16d a process flow chart of a method for manufacturing an image sensor provided by still another embodiment of the present disclosure,Figure 16e As Figure 14d A cross-sectional view in the Z-Z' direction;

[0051] Figure 17a to Figure 17e A process flow diagram of a method of fabricating an image sensor according to yet another embodiment of the present disclosure;

[0052] Figure 18a to Figure 18d A process flow diagram of a method of fabricating an image sensor according to still another embodiment of the present disclosure; DETAILED DESCRIPTION

[0053] As known from the background art, the source follower in current CMOS image sensors is usually a MOSFET, in which structure, the change in the gate voltage affects the change in the source voltage or current, and by detecting the change, the amount of photo-generated charge of the photodiode can be known. This process is often accompanied by noise, in which the flicker noise plays a major role at low frequencies, and the flicker noise is generated due to the capture and release of electrons and holes in the channel by the Si and SiO2 interface, which weakens the gate control ability of the source follower and reduces the conversion gain.

[0054] The present disclosure implements a change from a MOSFET transistor to a JFET transistor for the source follower transistor, and the conduction of the JFET requires the field effect of PN, and does not require the field effect of the oxide, so that the flicker noise originally generated due to the capture and release of carriers at the Si and SiO2 interface can be removed, so that the gate control ability of the source follower transistor is enhanced, and the conversion gain is improved.

[0055] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to make the reader better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0056] The present disclosure is described in more detail below with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present disclosure will be clearer according to the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clarifying the purpose of assisting in the description of the embodiments of the present disclosure.

[0057] It can be understood that the meaning of "on", "above" and "over" of the present disclosure should be interpreted in the broadest way, so that the meaning of "on" not only means "on" something and there is no intervening characteristic or layer between them (i.e. directly on something), but also includes the meaning of "on" something and there is an intervening characteristic or layer between them.

[0058] In the embodiments of the present disclosure, the terms "first", "second", "third", and the like are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence.

[0059] In the embodiments of the present disclosure, the term "layer" refers to a material portion including a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Furthermore, the layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0060] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0061] Figure 1 A schematic diagram of an image sensor is provided for an embodiment of the present disclosure; Figure 1 a 、 Figure 1 b A schematic diagram of an image sensor is provided for an embodiment of the present disclosure; Figure 1 A cross-sectional view along the X-X' direction of the schematic diagram of the image sensor is provided for an embodiment of the present disclosure; Figure 2 A top view of the schematic diagram of the image sensor is provided for an embodiment of the present disclosure; Figure 1 A schematic diagram of the circuit connection of the image sensor is provided for an embodiment of the present disclosure; Figure 3 A schematic diagram of the circuit connection of the image sensor is provided for an embodiment of the present disclosure;

[0062] Figure 4 A schematic diagram of an image sensor is provided for another embodiment of the present disclosure; Figure 5 A top view of the schematic diagram of the image sensor is provided for another embodiment of the present disclosure; Figure 4 A schematic diagram of the circuit connection of the image sensor is provided for another embodiment of the present disclosure; Figure 6 A schematic diagram of the circuit connection of the image sensor is provided for another embodiment of the present disclosure; Figure 7 A schematic diagram of an image sensor is provided for another embodiment of the present disclosure; Figure 7a 、 Figure 7b A cross-sectional view along the Y-Y' direction of the schematic diagram of the image sensor is provided for another embodiment of the present disclosure; Figure 7 A top view of the schematic diagram of the image sensor is provided for another embodiment of the present disclosure; Figure 8 A schematic diagram of the circuit connection of the image sensor is provided for another embodiment of the present disclosure; Figure 7 A schematic diagram of an image sensor is provided for another embodiment of the present disclosure; Figure 9 A top view of the schematic diagram of the image sensor is provided for another embodiment of the present disclosure; Figure 10 A schematic diagram of the circuit connection of the image sensor is provided for another embodiment of the present disclosure; Figure 11 A schematic diagram of the circuit connection of the image sensor is provided for another embodiment of the present disclosure; Figure 10 A circuit diagram of the image sensor is provided for the present disclosure; Figure 12 A process flow diagram of a method for preparing an image sensor is provided for an embodiment of the present disclosure, Figure 13 A process flow diagram of a method for preparing an image sensor is provided for an embodiment of the present disclosure, Figure 14a to Figure 14c A process flow diagram of a method for preparing an image sensor is provided for an embodiment of the present disclosure, Figure 14d A process flow diagram of a method for preparing an image sensor is provided for an embodiment of the present disclosure, Figure 14ca cross-sectional view taken along the Z-Z' direction; Figure 15a to Figure 15d A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided, Figure 15e A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided, Figure 14d a cross-sectional view taken along the Z-Z' direction;

[0063] Figure 16a to Figure 16d A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided, Figure 16e A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided, Figure 14d a cross-sectional view taken along the Z-Z' direction; Figure 17a to Figure 17e A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided, Figure 18a to Figure 18d A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided,

[0064] Figure 1 to Figure 3 A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided, Figure 1 , the image sensor comprises: a substrate 10, the substrate 10 having a well region 20; a first transistor 1 and a second transistor 2, the first transistor 1 and the second transistor 2 sharing one source or drain, at least the first transistor 1 being a junction transistor (JFET); the first transistor 1 comprising: a first doped region 101 and a second doped region 102; a first channel region 201 located between the first doped region 101 and the second doped region 102; a third doped region 103 surrounding the first channel region 201; the first channel region 201 extending along a first direction or a second direction, the first direction being parallel to a surface of the substrate 10, the second direction being perpendicular to the surface of the substrate 10. Wherein the first doped region 101 and the second doped region 102 serve as the source and the drain of the first transistor 1, the first doped region 101 and a fourth doped region 104 serve as the source and the drain of the second transistor 2, and the first doped region 101 serves as the shared source or drain of the first transistor 1 and the second transistor 2. The first transistor 1 can be a source follower transistor (SF: Source Follower), and the second transistor 2 can be a selector transistor (SEL: Selector).

[0065] The second transistor 2 can be a junction transistor or a metal-oxide-semiconductor field-effect transistor (MOSFET), as shown in Figure 1 The first transistor 1 is a junction transistor, and the second transistor 2 is a metal-oxide-semiconductor field-effect transistor, as shown in; the second transistor 2 further comprises a gate 301 and a fourth doped region 104, the gate 301 is located on the substrate 10 and is adjacent to the first doped region 101, the fourth doped region 104 is located on a side of the gate 301 away from the first doped region 101, and the doping depth of the fourth doped region 104 is less than the doping depth of the first doped region 101.

[0066] Figure 1 a 、 Figure 1 b A process flow diagram of a method for manufacturing an image sensor according to another embodiment of the present disclosure is provided, Figure 1The cross-sectional view in the direction of X-X'; the third doped region 103 is arranged around the first channel region 201, the cross-section of the first channel region 201 can be circular or square, and the third doped region 103 can also be circular or square accordingly, which is only an example and is not limited herein, for example, the third doped region 103 and the first channel region 201 can also be elliptical or rectangular.

[0067] Figure 2 The top view of Figure 1 Figure 2 The dashed line position schematically represents the position of the first channel region 201, which is located between the first doped region 101 and the second doped region 102; the first transistor 1 and the second transistor 2 share the first doped region 101, and the second transistor 2 has a gate 301.

[0068] In the embodiment, the first transistor 1 is a junction field effect transistor (JFET), and the second transistor 2 is a metal oxide semiconductor field effect transistor (MOSFET). The first transistor 1 in the embodiment can be a P-type junction transistor, wherein the well region 20 is N-type doped, i.e., an N-well, the first doped region 101 and the second doped region 102 are P-type doped, the first channel region 201 is also P-type doped, the doping concentration of the first doped region 101 and the second doped region 102 is greater than that of the first channel region 201, and the third doped region 103 is N-type doped. Since the doping type of the third doped region 103 is opposite to that of the first channel region 201, a PN junction is formed between the third doped region 103 and the first channel region 201. By applying a voltage to the third doped region 103, the width of the PN junction barrier is changed, and thus the thickness of the conductive channel, i.e., the first channel region 201, is changed, so that the JFET is in an open or off state, and the conductivity of the conductive channel is adjusted to realize the control of the output current. The thickness of the first channel region 201 refers to the width of the first channel region 201 from top to bottom. When the cross-section of the first channel region 201 is circular, the thickness refers to the diameter of the circle. When the cross-section of the first channel region 201 is square, the thickness refers to the side length of the square.

[0069] ​First transistor 1 can be a source follower transistor (SF). In a CMOS image sensor (CIS), the SF is used to amplify and read out the signal output from the floating diffusion region (FD). In prior art, the SF transistor is typically a MOSFET. The Si and SiO2 interfaces of a MOSFET have interface defects. When the SF transistor in a CMOS image sensor is operating, carriers in the channel continuously bind and dissociate with bound states at the Si and SiO2 interfaces. This causes the source output voltage to fluctuate randomly over time, generating transient noise and affecting the output voltage stability. In this embodiment, the first transistor 1 is a junction transistor. By applying a voltage to the third doped region 103 to change the width of the PN junction barrier and thereby changing the thickness of the first channel region 201, the JFET is turned on or off. Since the third doped region 103 and the first channel region 201 in the JFET are both made of silicon, there is no interface between Si and SiO2, that is, no Si and SiO2 interface defects. In other words, in this embodiment, when the SF transistor in the CMOS image sensor is operating, there is no binding and dissociation process between carriers in the channel and bound states at the Si and SiO2 interface, thereby preventing the generation of transient noise and thus making the output voltage more stable.

[0070] Figure 3 A schematic diagram of circuit connections of an image sensor provided in one embodiment of the present disclosure; and Figure 2 What is different from the top view is that in this embodiment, a first pad M1, a second pad M2, a third pad M3 and a fourth pad M4 are also included. The first pad M1 is electrically connected to the third doping region 103 and is used to apply a voltage to the third doping region 103; the second pad M2 is electrically connected to the gate 301 and is used to apply a voltage to the gate 301; the third pad M3 is used to lead out the signal, and the fourth pad M4 is used to apply a power supply voltage VDD to the first transistor 1. In addition, the image sensor also includes a photodiode (PD: Photo diode) 401, which is used to collect and store charges induced by photons; a transfer transistor 402 (TG: Transfer gate), which is used to control the on and off of FD, and a fifth pad M5 is also included in the transfer transistor 402, which is used to input a voltage to the transfer transistor 402; a floating diffusion region (FD: Floating diffusion) is also included between the multiple photodiodes 401, and FD is used to store electrons transferred from PD, Figure 3FD is not shown in the figure, and there is also a sixth pad M6 on the FD, which is used to lead out the signal of the FD; the first pad M1 and the sixth pad M6 are connected by a wire 403; the source follower transistor SF can amplify the potential change of the floating diffusion area FD, and can output the amplified signal.

[0071] Figure 4 to Figure 6 This is the second embodiment; the difference from the previous embodiment is that the second transistor 2 and the first transistor 1 are both junction transistors (JFETs). Figure 4 and Figure 5 , Figure 4 A schematic diagram of an image sensor provided in another embodiment of the present disclosure is shown. Figure 5 for Figure 4 The image sensor comprises: a substrate 10 having a well region 20; a first transistor 1 and a second transistor 2, the first transistor 1 and the second transistor 2 sharing a source or a drain, the first transistor 1 and the second transistor 2 being JFETs; the first transistor 1 comprising: a first doping region 101 and a second doping region 102; a first channel region 201 located between the first doping region 101 and the second doping region 102, and a third doping region 103 surrounding the first channel region 201; the first channel region 201 extending along a first direction parallel to the surface of the substrate 10, wherein the first doping region 201 extends in a first direction parallel to the surface of the substrate 10, wherein the first doping region 101 extends in a first direction parallel to the surface of the substrate 10, wherein the first doping region 101 extends in a first direction parallel to the surface of the substrate 10, wherein the first doping region 101 extends in a first direction parallel to the surface of the substrate 10, wherein the first doping region 103 extends in a first direction parallel to the surface of the substrate 10, wherein the first doping region 1 ... The doped region 101 and the second doped region 102 serve as the source and drain of the first transistor 1. The second transistor 2 includes the first doped region 101 and the fourth doped region 104, a second channel region 202 located between the first doped region 101 and the fourth doped region 104, and a fifth doped region 105 surrounding the second channel region 202. The second channel region 202 extends along a first direction parallel to the surface of the substrate 10. The first doped region 101 and the fourth doped region 104 serve as the source and drain of the second transistor 2, and the first doped region 101 serves as a common source or drain for the first transistor 1 and the second transistor 2. The first transistor 1 can be a source follower transistor (SF), and the second transistor 2 can be a select transistor (SEL). Figure 5 The dotted lines in FIG. 2 respectively indicate the positions of the first channel region 201 and the second channel region 202 .

[0072] Figure 6A circuit connection diagram of an image sensor provided in another embodiment of the present disclosure is provided. The parts that are the same as the circuit connection diagram in the previous embodiment are not repeated here. The difference from the circuit connection diagram in the previous embodiment is that in this embodiment, the second pad M2 is connected to the fifth doping region 105 instead of the gate 301. A voltage is applied to the fifth doping region 105 through the second pad M2 to change the width of the PN junction barrier in the second transistor 2, thereby changing the thickness of the second channel region 202, so that the JFET is turned on or off.

[0073] Figure 7 to Figure 9 This is the third embodiment; Figure 7 A schematic diagram of an image sensor provided in yet another embodiment of the present disclosure; Figure 7a 、 Figure 7b For the Figure 7 Cross-sectional view in the Y-Y' direction; Figure 8 for Figure 7 A top view of Figure 9 This is a circuit connection diagram of an image sensor provided by another embodiment of the present disclosure. Figure 7The image sensor includes: a substrate 10, the substrate 10 has a well region 20; a first transistor 1 and a second transistor 2, the first transistor 1 and the second transistor 2 share a source or drain; the first transistor 1 includes: a first doping region 101 and a second doping region 102, the second doping region 102 includes a first sub-doping region 1021 and a second sub-doping region 1022, the first sub-doping region 1021 is located below the first doping region 101 and parallel to the surface of the substrate 10, the second sub-doping region 1022 extends along a second direction and is electrically connected to the first sub-doping region 1021, the second direction is perpendicular to the surface of the substrate 10, it should be noted that the first sub-doping region 1021 is inside the substrate 10 and has a certain distance from the top surface of the substrate 10, and the lateral length of the first doping region 101 is smaller than the lateral length of the first sub-doping region. A first channel region 201 is further provided between the first doping region 101 and the first sub-doping region 1021. The first channel region 201 extends along a second direction perpendicular to the direction of the substrate 10. The third doping region 103 is arranged around the first channel region 201. One end of the third doping region 103 is connected to the first doping region 101, and the other end of the third doping region 103 is connected to the first sub-doping region 1021. A first isolation structure 50 is provided between the second sub-doping region 1022 and the third doping region 103. The first isolation structure 50 The first and second sub-isolation structures 501 and 502 are provided with a first pad M1 between the first and second sub-isolation structures 501 and 502. The first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doped region 101, and the second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doped region 1021. The depth of the first sub-isolation structure 501 along the second direction is greater than the depth of the first doped region 101 along the second direction and less than the depth of the second sub-isolation structure 502 along the second direction. The second transistor 2 is a metal oxide semiconductor field effect transistor (MOSFET), with reference to Figure 7 The second transistor 2 shown further includes a gate 301 and a fourth doping region 104 . The gate 301 is located on the substrate 10 and is adjacent to the first doping region 101 . The fourth doping region 104 is located on a side of the gate 301 away from the first doping region 101 .

[0074] Figure 7a 、 Figure 7b For the Figure 7 Cross-sectional view in the Y-Y' direction; the third doped region 103 is arranged around the first channel region 201, and the cross-section of the first channel region 201 can be circular or square, and the corresponding third doped region 103 can also be circular or square. This is only an example and is not limited here. For example, the third doped region 103 and the first channel region 201 can also be elliptical or rectangular.

[0075] Figure 8 for Figure 7 A top view ofFigure 8 The middle dotted line schematically represents the position of the first channel region 201, which is located between the first doped region 101 and the gate 301; the first doped region 101 is shared by the first transistor 1 and the second transistor 2; the first sub-isolation structure 501 and the second sub-isolation structure 502 have the first pad M1 therebetween.

[0076] In the embodiment, the first transistor 1 is set as a JFET, and the first channel region 201 extends along the second direction, so that the channel length of the first channel region 201 is lengthened, the control ability of the first transistor 1 is improved, the voltage output is more stable, and the performance of the first transistor 1 is further improved. In the embodiment, the first transistor 1 is a JFET, the second transistor 2 is a MOSFET, the first transistor 1 is a P-type JFET, the well region 20 is N-type doped, i.e., an N-well, the first doped region 101 and the second doped region 102 are P-type doped, the first channel region 201 is also P-type doped, the doping concentration of the first doped region 101 and the second doped region 102 is greater than the doping concentration of the first channel region 201, and the third doped region 103 is N-type doped; the doping type of the third doped region 103 is the same as that of the well region 20, and the doping type of the third doped region 103 is opposite to that of the first channel region 201; since the doping type of the third doped region 103 is opposite to that of the first channel region 201, a PN junction is formed between the third doped region 103 and the first channel region 201, the first channel region 201 extends along the second direction, the extension depth of the first channel region 201 is deep, the channel length of the first channel region 201 is lengthened, and when a voltage is applied to the third doped region 103 through the first pad M1, the thickness of the conductive channel, i.e., the first channel region 201, is changed, so that the JFET is in an open or cut-off state, and the control ability of the first transistor is improved due to the first channel region 201 of the vertical substrate 10. In addition, it should be noted that the doping type of the third doped region 103 is the same as that of the well region 20, when a voltage is applied to the first pad M1, the voltage is transmitted to the third doped region 103 through the well region 20 between the third doped region 103 and the second sub-doped region 1022, the width of the PN junction barrier of the first transistor 1 is changed, so that the JFET is in an open or cut-off state, and then the control of the output current is realized by adjusting the conductivity of the conductive channel. In order to prevent the influence of the first pad M1 on the first doped region 101 and the second sub-doped region 1022 when the voltage is applied to the first pad M1, the first sub-isolation structure 501 and the second sub-isolation structure 502 are arranged on both sides of the first pad, the first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doped region 101, so that the influence of the first pad M1 on the first doped region 101 is prevented, and the second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doped region 1021, so that the influence of the first pad M1 on the second sub-doped region 1022 is further prevented. Since the first sub-doped region 1021 is far away from the first pad M1, the first sub-doped region 1021 is basically not affected by the voltage applied by the first pad M1, and therefore the first sub-doped region 1021 can not be provided with an isolation structure. Of course, in other embodiments, other isolation structures can also be arranged on the first sub-doped region 1021 in order to maintain better isolation effect.

[0077] Figure 9 A schematic diagram of the circuit connection of the image sensor is provided for another embodiment of the present disclosure. In this embodiment, the image sensor also includes a first pad M1, a second pad M2, a third pad M3, and a fourth pad M4. The first pad M1 is located between the first sub-isolation structure 501 and the second sub-isolation structure 502, and is used to apply a voltage to the third doped region 103; the second pad M2 is electrically connected to the gate 301, and is used to apply a voltage to the gate 301; the third pad M3 is located at the fourth doped region 104, and is used to lead out a signal; and the fourth pad M4 is located at the second sub-doped region 1022, and is used to apply a power voltage VDD to the first transistor 1. In addition, the image sensor also includes a photo diode (PD) 401, which is used to collect and store charges induced by photons; a transfer gate (TG) 402, which is used to control the on and off of the FD, and also includes a fifth pad M5 in the transfer gate 402, which is used to input a voltage to the transfer gate 402; and a floating diffusion (FD) between a plurality of photo diodes 401, which is used to store electrons transferred from the PD, Figure 3 The FD is not shown in the middle, and also has a sixth pad M6 on the FD, which is used to lead out a signal of the FD; the first pad M1 and the sixth pad M6 are connected by a wire 403; and a source follower transistor SF can amplify the potential change of the floating diffusion FD receiving charges from the photo diode PD, and can output the amplified change to an output line.

[0078] Figure 10 to Figure 12 For a fourth embodiment; Figure 10 A schematic diagram of the image sensor is provided for another embodiment of the present disclosure; Figure 11 A top view of Figure 10 ; Figure 12This is a circuit connection diagram of an image sensor provided in accordance with another embodiment of the present disclosure. Unlike the previous embodiment, in this embodiment, the second transistor 2 and the first transistor 1 are both junction transistors. The first channel region 201 and the second channel region 202 both extend along the second direction. The first transistor 1 and the second transistor 2 share a first doping region 101. The second transistor 2 further includes a fourth doping region 104 and a second channel region 202. The second channel region 202 is located between the first doping region 101 and the fourth doping region 104. The fifth doping region 105 is disposed around the second channel region 202. The second channel region 202 extends along the second direction. The fourth doping 104 includes a third sub-doping region 1041 and a fourth sub-doping region 1042, the third sub-doping region 1041 is located below the first doping region 101 and parallel to the surface of the substrate 10, the fourth sub-doping region 1042 extends along the second direction and is electrically connected to the third sub-doping region 1041; a second isolation structure 60 is provided between the fourth sub-doping region 1042 and the fifth doping region 105, the second isolation structure 60 includes a third sub-isolation structure 601 and a fourth sub-isolation structure 602; a second pad M2 is provided between the third sub-isolation structure 601 and the fourth sub-isolation structure 602, the third sub-isolation structure 601 extends from the top of the substrate 10 to below the first doping region 101, and the fourth sub-isolation structure 602 extends from the top of the substrate 10 to the third sub-doping region 1041; the depth of the third sub-isolation structure 601 along the second direction is greater than the depth of the first doping region 101 along the second direction and is less than the depth of the fourth sub-isolation structure 602 along the second direction. A third isolation structure 70 is further provided between the fifth doping region 105 and the third doping region. The depth of the third isolation structure 70 is not less than the depth of the first channel region 201 or the second channel 202 .

[0079] Figure 11 for Figure 10 A top view of Figure 11 The middle dotted line position schematically indicates the position of the first channel region 201 and the second channel region 202, and there is a third isolation structure 70 between the first channel region 201 and the second channel region 202; the first transistor 1 and the second transistor 2 share the first doped region 101; there is a first pad M1 between the first sub-isolation structure 501 and the second sub-isolation structure 502, and there is a second pad M2 between the third sub-isolation structure 601 and the fourth sub-isolation structure 602.

[0080] In the embodiment, the first transistor 1 and the second transistor 2 are set as JFETs, and the first channel region 201 and the second channel region 202 both extend along the second direction, so that the channel lengths of the first channel region 201 and the second channel region 202 are both lengthened, the control abilities of the first transistor 1 and the second transistor 2 are improved, the voltage output is more stable, and the performance of the first transistor 1 and the second transistor 2 is further improved. In the embodiment, the first transistor 1 and the second transistor 2 are both P-type junction transistors, the well region 20 is N-type doped, that is, an N well, the first doped region 101 and the second doped region 102 are P-type doped, the first channel region 201 and the second channel region 202 are also P-type doped, the doping concentrations of the first doped region 101 and the second doped region 102 are both greater than the doping concentration of the first channel region 201, the doping concentrations of the first doped region 101 and the fourth doped region 104 are both greater than the doping concentration of the second channel region 202, the third doped region 103 and the fifth doped region 105 are both N-type doped, the doping type of the third doped region 103 and the doping type of the fifth doped region 105 are both the same as the doping type of the well region 20, the doping type of the third doped region 103 is opposite to the doping type of the first channel region 201, and the doping type of the fifth doped region 105 is opposite to the doping type of the second channel region 202.

[0081] Since the doping type of the third doped region 103 is opposite to that of the first channel region 201, a PN junction is formed between the third doped region 103 and the first channel region 201. Since the first channel region 201 extends along the second direction, the extension depth is deepened so that the channel length of the first channel region 201 is lengthened. When a voltage is applied to the third doped region 103 through the first pad M1, the conductive channel, i.e., the thickness of the first channel region 201, is changed so that the JFET is turned on or off. The first channel region 201 provided in the vertical substrate 10 improves the control ability of the first transistor. It should be noted that the doping type of the third doped region 103 is the same as that of the well region 20. When a voltage is applied to the first pad M1, the voltage is transmitted to the third doped region 103 through the well region 20 between the third doped region 103 and the second sub-doped region 1022, which changes the width of the PN junction barrier of the first transistor 1, so that the JFET is turned on or off, thereby controlling the output current by adjusting the conductivity of the conductive channel. In order to prevent the first pad M1 from affecting the first doped region 101 and the second sub-doped region 1022 when a voltage is applied to the first pad, the first sub-isolation structure 501 and the second sub-isolation structure 502 are provided on both sides of the first pad. The first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doped region 101, which prevents the first pad M1 from affecting the first doped region 101. The second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doped region 1021, which further prevents the first pad M1 from affecting the second sub-doped region 1022. Since the first sub-doped region 1021 is far away from the first pad M1, the first sub-doped region 1021 is basically not affected by the voltage applied by the first pad M1. Therefore, the first sub-doped region 1021 does not need to be provided with an isolation structure. Of course, in other embodiments, other isolation structures can also be provided on the first sub-doped region 1021 to maintain better isolation effect. Since the doping type of the fifth doped region 105 is opposite to that of the second channel region 202, a PN junction is formed between the fifth doped region 105 and the second channel region 202. Since the second channel region 202 extends along the second direction, the extension depth is deepened so that the channel length of the second channel region 202 is lengthened. When a voltage is applied to the fifth doped region 105 through the second pad M2, the conductive channel, i.e., the thickness of the second channel region 202, is changed so that the JFET is turned on or off. The second channel region 202 provided in the vertical substrate 10 improves the control ability of the second transistor. It should be noted that the doping type of the fifth doped region 105 is the same as that of the well region 20. When a voltage is applied to the second pad M2, the voltage is transmitted to the fifth doped region 105 through the well region 20 between the fifth doped region 105 and the fourth sub-doped region 1042, which changes the width of the PN junction barrier of the second transistor 2, so that the JFET is turned on or off, thereby controlling the output current by adjusting the conductivity of the conductive channel.In order to prevent the influence of the second pad M2 on the first doped region 101 and the fourth sub-doped region 1042 when the second pad M2 applies voltage, the third sub-isolation structure 601 and the fourth sub-isolation structure 602 are arranged on both sides of the second pad M2, the third sub-isolation structure 601 extends from the top of the substrate 10 to below the first doped region 101, so as to prevent the influence of the second pad M2 on the first doped region 101, and the fourth sub-isolation structure 602 extends from the top of the substrate 10 to the third sub-doped region 1041, so as to further prevent the influence of the second pad M2 on the fourth sub-doped region 1042. Since the third sub-doped region 1041 is far away from the second pad M2, the third sub-doped region 1041 is basically not affected by the voltage applied by the second pad M2, so the third sub-doped region 1041 can not be provided with an isolation structure. Of course, in other embodiments, in order to maintain better isolation effect, other isolation structures can also be arranged on the third sub-doped region 1041.

[0082] Figure 12 A schematic diagram of the circuit connection of the image sensor is provided for another embodiment of the present disclosure. In the present embodiment, the image sensor further comprises a first pad M1, a second pad M2, a third pad M3 and a fourth pad M4. The first pad M1 is located between the first sub-isolation structure 501 and the second sub-isolation structure 502, and the first pad is used to apply voltage to the third doped region 103; the second pad M2 is located between the third sub-isolation structure 601 and the fourth sub-isolation structure 602, and the second pad M2 is used to apply voltage to the fifth doped region 105; the third pad M3 is located at the fourth sub-doped region 1042 for signal output, and the fourth pad M4 is located at the second sub-doped region 1022 for applying a power voltage VDD to the first transistor 1. In addition, the image sensor further comprises a photo diode (PD) 401 for collecting and storing charges induced by photons; a transfer gate (TG) 402 for controlling the conduction and cutoff of the FD, the fifth pad M5 is further included in the transfer gate 402, and the fifth pad M5 is used to input voltage to the transfer gate 402; a floating diffusion (FD) is further included between a plurality of photo diodes 401, the FD is used to store electrons transferred from the PD, Figure 3 The FD is not shown in the middle, and the sixth pad M6 is further provided on the FD, and the sixth pad M6 is used to output the signal of the FD; the first pad M1 and the sixth pad M6 are connected through a wire 403; the source follower transistor SF can amplify the potential change of the floating diffusion FD receiving charges from the photo diode PD, and can output the amplified change to the output line.

[0083] Figure 13A circuit diagram of an image sensor of the present disclosure; the image sensor comprises a photodiode PD, a transfer transistor TG, a floating diffusion region FD, a reset transistor RST, a source follower transistor SF and a selection transistor SEL. The photodiode PD can generate charges proportional to the amount of light incident from the outside, the photodiode PD can be coupled to the transfer transistor TG, the charges generated and accumulated by the photodiode PD are transferred to the floating diffusion region FD through the transfer transistor TG, and the floating diffusion region FD can accumulate and store the charges. One end of the transfer transistor TG is connected to the photodiode PD, the other end of the transfer transistor TG can be connected to the floating diffusion region FD, the transfer transistor TG can transfer the charges generated by the photodiode PD to the floating diffusion region FD according to a transfer signal TX, the source follower transistor SF can amplify the potential change of the floating diffusion region FD, and can output the amplified signal; when the source follower transistor SF is turned on, the power supply voltage VDD provided to the drain of the source follower transistor SF can be transferred to the drain region of the selection transistor SEL, the selection transistor SEL can select unit pixels to be read row by row, and the selection transistor SEL can be a transistor driven by a selection line of a row selection signal RS; the reset transistor RST can periodically reset the floating diffusion region FD, and the reset transistor RST can be driven by a reset line of a reset signal RX, when the reset signal RX turns on the reset transistor RST, the power supply voltage VDD is provided to the drain of the reset transistor RST, and the power supply voltage VDD can be transferred to the floating diffusion region FD. The working process of the circuit of the image sensor in the embodiment is as follows: first, open RST and TG at the same time to empty PD, then open RST transistor to reset FD voltage; the photodiode PD generates electron holes under light, the TG transistor is turned on, the electrons generated by the PD are transmitted to the FD (the voltage of the FD and the SF transistor is equal), the SF transistor gate obtains electrons, the SF transistor gate voltage is lowered (the potential is raised), and the output signal Vout fluctuates with the potential fluctuation of the FD.

[0084] A method for forming an image sensor will be described below. The method comprises: providing a substrate, doping the substrate to form a well region; forming a first transistor and a second transistor in the substrate, the first transistor and the second transistor sharing a source or a drain, and at least the first transistor being a junction transistor; the first transistor comprising: a first doped region and a second doped region; a first channel region between the first doped region and the second doped region; a third doped region surrounding the first channel region; the first channel region extending in a first direction or a second direction, the first direction being parallel to the surface of the substrate, and the second direction being perpendicular to the surface of the substrate. Figure 14a - Figure 18d Only the formation method of the first transistor 1 will be described, and the formation process of the second transistor 2 can refer to the formation process of the first transistor 1.

[0085] Figure 14a to Figure 14c This is a process flow chart of an image sensor manufacturing method provided in an embodiment of the present disclosure. The first channel region 201 extends along a first direction. The method for forming the first transistor at least includes: providing a substrate 10, doping the substrate 10 to form a well region 20; performing a first doping and a second doping on the well region 20 to form a first doping region 101 and a second doping region 102, forming a first channel region 201 between the first doping region 101 and the second doping region 102, and performing a third doping around the first channel region 201 to form a third doping region 103. Figure 14d for Figure 14c In the ZZ′ direction cross-sectional view, the first channel region 201 may be circular, the third doped region 103 surrounds the first channel region 201 , and the third doped region 103 and the first channel region 201 may be concentric circles.

[0086] Figure 15a to Figure 15d This is a process flow chart of a method for manufacturing an image sensor provided by another embodiment of the present disclosure. Figure 15e for Figure 14d Z-Z' direction cross-sectional view; In this embodiment, the first channel region extends along the first direction, and the method for forming the first transistor at least includes: forming a first initial doping region 1031, the top surface of the first initial doping region 1031 has a first distance D1 from the top surface of the substrate 10, forming a second initial doping region 1032 on the first initial doping region 1031, forming a third initial doping region 1033 on the top of the second initial doping region 1032, and forming a fourth initial doping region 1034 on the side of the second initial doping region 1032, as shown in FIG. Figure 15e The fourth initial doping region 1034 shown is located between the first initial doping region 1031 and the second initial doping region 1032 and on both sides of the second initial doping region 1032; the first initial doping region 1031, the third initial doping region 1033 and the fourth initial doping region 1034 together constitute the third doping region 103, the third doping region 103 surrounds the second initial doping region 1032, the doping type of the third doping region 103 is opposite to the doping type of the second initial doping region 1032, and the second initial doping region 1032 serves as the first channel region 201; the first doping region 101 and the second doping region 102 are formed at both ends of the third doping region.

[0087] Figure 16a to Figure 16d This is a process flow chart of a method for manufacturing an image sensor provided by yet another embodiment of the present disclosure. Figure 16e for Figure 14dA cross-sectional view along the Z-Z' direction; the first channel region extends along the first direction, and the forming method of the first transistor at least includes: forming a fifth initial doping region 1035 extending from the surface of the substrate 10 into the substrate 10, the bottom of the fifth initial doping region 1035 being away from the surface of the substrate 10 by a second interval D2; forming a sixth initial doping region 1036 in the fifth initial doping region 1035, the doping type of the fifth initial doping region 1035 being opposite to that of the sixth initial doping region 1036, the sixth initial doping region 1036 serving as the first channel region 201, the remaining fifth initial doping region 1035 surrounding the first channel region 201, the remaining fifth initial doping region serving as the third doping region 103, and the first and second doping regions 101 and 102 being formed at two ends of the third doping region 103. As shown in Figure 16e the sixth initial doping region 1036 can be circular, and the remaining fifth initial doping region 1035 surrounds the sixth initial doping region 1036. The remaining fifth initial doping region 1035 and the sixth initial doping region 1036 can be concentric circles.

[0088] Figure 17a to Figure 17e A process flow chart of the image sensor manufacturing method provided for another embodiment of the present disclosure; the first channel region 201 extends along the second direction, and the forming method of the first transistor 1 at least includes: forming a second doping region 102 including a first sub-doping region 1021 and a second sub-doping region 1022, the first sub-doping region 1021 being below the surface of the substrate 10, and the second sub-doping region 1022 extending along the second direction and being electrically connected to the first sub-doping region 1021; forming a seventh initial doping region 1037 on the first sub-doping region 1021, the seventh initial doping region 1037 serving as the first channel region 201, and the third doping region 103 being formed by doping around the first channel region 201; forming the first doping region 101 on the third doping region 103 and the seventh initial doping region 1037; the first isolation structure 50 is formed between the second sub-doping region 102 and the third doping region 103, and the first isolation structure 50 includes a first sub-isolation structure 501 and a second sub-isolation structure 502; the first pad M1 is formed between the first sub-isolation structure 501 and the second sub-isolation structure 502, the first sub-isolation structure 501 extending from the top of the substrate 10 to below the first doping region 101, and the second sub-isolation structure 502 extending from the top of the substrate 10 to the first sub-doping region 1021; the depth of the first sub-isolation structure 1021 along the second direction is greater than the depth of the first doping region 101 along the second direction and less than the depth of the second sub-isolation structure 1022 along the second direction.

[0089] Figure 18a to Figure 18d A process flow chart of the image sensor manufacturing method provided for another embodiment of the present disclosure; the structure of the first transistor 1 formed by the present embodiment is the same as that of the Figure 17e embodiment, and thus reference can be made to the description of the Figure 18a to Figure 18dand Figure 17e It is explained that the first channel region 201 extends along the second direction, and the forming method of the first transistor 1 at least includes: forming the second doped region 102, the second doped region 102 includes a first sub-doped region 1021 and a second sub-doped region 1022, the first sub-doped region 1021 is located below the surface of the substrate 10, and the second sub-doped region 1022 extends along the second direction and is electrically connected with the first sub-doped region 1021; forming an eighth initial doped region 1038 on the first sub-doped region 1021, the eighth initial doped region 1038 extends from the top surface of the substrate 10 to the first sub-doped region 1021, and a ninth initial doped region 1039 is formed in the eighth initial doped region 1038, the eighth initial doped region 1038 and the ninth initial doped region 1039 are opposite in doping type, the ninth initial doped region 1039 serves as the first channel region 201, and the remaining eighth initial doped region 1038 surrounds the first channel region 201, and the remaining eighth initial doped region 1038 serves as a third doped region 103; the first doped region 101 is formed on the top of the third doped region 103. The first isolation structure 50 is formed between the second doped region 102 and the third doped region 103, and the first isolation structure 50 includes a first sub-isolation structure 501 and a second sub-isolation structure 502; the first pad M1 is formed between the first sub-isolation structure 501 and the second sub-isolation structure 502, the first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doped region 101, and the second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doped region 1021; the depth of the first sub-isolation structure 1021 along the second direction is greater than the depth of the first doped region 101 along the second direction and less than the depth of the second sub-isolation structure 1022 along the second direction.

[0090] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. An image sensor, characterized by, Comprising: a substrate; a first transistor and a second transistor, the first transistor and the second transistor sharing one source or drain, at least the first transistor being a junction transistor; the first transistor comprising: a first doped region and a second doped region; a first channel region between the first doped region and the second doped region; a third doped region surrounding the first channel region; the first channel region extending along a first direction or a second direction, the first direction being parallel to a surface of the substrate, the second direction being perpendicular to the surface of the substrate.

2. The image sensor of claim 1, wherein, the first channel region extending along a second direction, the second doped region comprising a first sub-doped region and a second sub-doped region, the first sub-doped region being below the first doped region and parallel to the surface of the substrate, the second sub-doped region extending along the second direction and electrically connected to the first sub-doped region.

3. The image sensor of claim 2, wherein, the second sub-doped region and the third doped region having a first isolation structure therebetween, the first isolation structure comprising a first sub-isolation structure and a second sub-isolation structure; the first sub-isolation structure and the second sub-isolation structure having a first pad therebetween, the first sub-isolation structure extending from a top of the substrate to below the first doped region, the second sub-isolation structure extending from the top of the substrate to the first sub-doped region; a depth of the first sub-isolation structure along the second direction being greater than a depth of the first doped region along the second direction and less than a depth of the second sub-isolation structure along the second direction.

4. The image sensor of claim 1, wherein, the first doped region and the second doped region being of the same doping type, the first channel region being of the same doping type as the first doped region and the second doped region, the third doped region being of an opposite doping type to the first channel region; a doping concentration of the first channel region being less than a doping concentration of the first doped region and the second doped region.

5. The image sensor according to any one of claims 1 to 4, wherein the second transistor being a metal-oxide-semiconductor field-effect transistor, the second transistor further comprising a gate and a fourth doped region, the gate being on the substrate and adjacent to the first doped region, the fourth doped region being on a side of the gate away from the first doped region, a doping depth of the fourth doped region being less than a doping depth of the first doped region.

6. The image sensor according to any one of claims 1 to 4, wherein the second transistor being a junction transistor, the second transistor further comprising a fourth doped region and a second channel region, the second channel region being between the first doped region and the fourth doped region, a fifth doped region surrounding the second channel region, the second channel region extending along the first direction or the second direction.

7. The image sensor of claim 6, wherein, the second channel region extending along the second direction, the fourth doped region comprising a third sub-doped region and a fourth sub-doped region, the third sub-doped region being below the first doped region and parallel to the surface of the substrate, the fourth sub-doped region extending along the second direction and electrically connected to the third sub-doped region.

8. The image sensor of claim 6, wherein, The fourth doped region and the fifth doped region have a second isolation structure therebetween, the second isolation structure comprising a third sub-isolation structure and a fourth sub-isolation structure; the third sub-isolation structure and the fourth sub-isolation structure have a second pad therebetween, the third sub-isolation structure extending from the top of the substrate to below the first doped region, the fourth sub-isolation structure extending from the top of the substrate to the third doped region; the depth of the third sub-isolation structure along the second direction is greater than the depth of the first doped region along the second direction and less than the depth of the fourth sub-isolation structure along the second direction.

9. The image sensor of claim 6, wherein, The fifth doped region and the third doped region also have a third isolation structure therebetween, the depth of the third isolation structure being not less than the depth of the first channel region or the second channel region.

10. A method of forming an image sensor, comprising: Comprising: providing a substrate; forming a first transistor and a second transistor, the first transistor and the second transistor sharing one source or drain, at least the first transistor being a junction transistor; the first transistor comprising: a first doped region and a second doped region; a first channel region between the first doped region and the second doped region; a third doped region surrounding the first channel region; the first channel region extending along a first direction or a second direction, the first direction being parallel to the surface of the substrate, the second direction being perpendicular to the surface of the substrate.

11. The method for forming an image sensor according to claim 10, wherein The first channel region extends along the first direction, and the forming method of the first transistor at least comprises: performing first doping and second doping on the substrate to form a first doped region and a second doped region, a first channel region being formed between the first doped region and the second doped region, and performing third doping on the first channel region to form a third doped region.

12. The method for forming an image sensor according to claim 10, wherein The first channel region extends along the first direction, and the forming method of the first transistor at least comprises: forming a first initial doped region, the top surface of the first initial doped region being at a first distance from the top surface of the substrate, forming a second initial doped region on the first initial doped region, forming a third initial doped region on the top of the second initial doped region, and forming a fourth initial doped region on the side of the second initial doped region, the first initial doped region, the third initial doped region, and the fourth initial doped region collectively constituting the third doped region, the third doped region surrounding the second initial doped region, the doping type of the third doped region being opposite to the doping type of the second initial doped region, the second initial doped region serving as the first channel region; forming the first doped region and the second doped region at both ends of the third doped region.

13. The method for forming an image sensor according to claim 10, wherein The first channel region extends along the first direction, and a forming method of the first transistor at least includes: forming a fifth initial doping region, the fifth initial doping region extends from the substrate surface to the substrate, and a bottom of the fifth initial doping region is away from the substrate surface by a second interval; forming a sixth initial doping region in the fifth initial doping region, a doping type of the fifth initial doping region is opposite to that of the sixth initial doping region, the sixth initial doping region serves as the first channel region, and a remaining part of the fifth initial doping region surrounds the first channel region, and the remaining part of the fifth initial doping region serves as the third doping region, and the first doping region and the second doping region are formed at two ends of the third doping region.

14. The method for forming an image sensor according to claim 10, wherein The first channel region extends along the second direction, and a forming method of the first transistor at least includes: forming the second doping region, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, and the second sub-doping region extends along the second direction and is electrically connected with the first sub-doping region; forming a seventh initial doping region on the first sub-doping region, the seventh initial doping region serves as the first channel region, and the first channel region is surrounded by doping to form the third doping region; the first doping region is formed on the third doping region and the first channel region; a first isolation structure is formed between the second sub-doping region and the third doping region, the first isolation structure includes a first sub-isolation structure and a second sub-isolation structure; a first pad is formed between the first sub-isolation structure and the second sub-isolation structure, the first sub-isolation structure extends from the top of the substrate to below the first doping region, and the second sub-isolation structure extends from the top of the substrate to the first sub-doping region; a depth of the first sub-isolation structure along the second direction is greater than a depth of the first doping region along the second direction and less than a depth of the second sub-isolation structure along the second direction.

15. The method for forming an image sensor according to claim 10, wherein The first channel region extends along the second direction, and a forming method of the first transistor at least includes: forming the second doping region, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, and the second sub-doping region extends along the second direction and is electrically connected with the first sub-doping region; forming a seventh initial doping region on the first sub-doping region, the seventh initial doping region extends from the top surface of the substrate to the first sub-doping region, and a ninth initial doping region is formed in the eighth initial doping region, a doping type of the eighth initial doping region is opposite to that of the ninth initial doping region, the ninth initial doping region serves as the first channel region, and a remaining part of the eighth initial doping region surrounds the first channel region, and the remaining part of the eighth initial doping region serves as the third doping region, and the first doping region is formed at the top of the third doping region.

16. The method for forming an image sensor according to any one of claims 10 to 15, wherein The second transistor is a metal oxide semiconductor field effect transistor, and a forming method of the second transistor further comprises forming a gate on the substrate, the gate being adjacent to the first doped region; a fourth doped region is formed on a side of the gate away from the first doped region, and a doping depth of the fourth doped region is less than a doping depth of the first doped region.

17. The method for forming an image sensor according to any one of claims 10 to 15, wherein The second transistor is a junction transistor, and the second transistor further comprises a fourth doped region and a second channel region, the second channel region being located between the first doped region and the fourth doped region, and a fifth doped region is arranged around the second channel region, and the second channel region extends along the first direction or the second direction.

18. The method for forming an image sensor according to claim 17, wherein The second channel region extends along the second direction, the fourth doped region comprises a third sub-doped region and a fourth sub-doped region, the third sub-doped region is located below the first doped region and parallel to the surface of the substrate, and the fourth sub-doped region extends along the second direction and is electrically connected with the third sub-doped region.

19. The method of forming a photosensor according to claim 17, wherein, A second isolation structure is formed between the fourth doped region and the fifth doped region, the second isolation structure comprises a third sub-isolation structure and a fourth sub-isolation structure, and a second pad is provided between the third sub-isolation structure and the fourth sub-isolation structure, the third sub-isolation structure extends from the top of the substrate to below the first doped region, and the fourth sub-isolation structure extends from the top of the substrate to the third sub-doped region, a depth of the third sub-isolation structure along the second direction is greater than a depth of the first doped region along the second direction and less than a depth of the fourth sub-isolation structure along the second direction.

20. The method for forming an image sensor according to claim 17, wherein, A third isolation structure is further formed between the fifth doped region and the third doped region, and a depth of the third isolation structure is not less than a depth of the first channel region or the second channel region.

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