Termination structure of super junction device and manufacturing method thereof

Abstract

In a termination structure of a super-junction device, a guard ring oxide film covers the surface of the super-junction structure in the transition region and the termination region. Each P-type column has a first surface region, and part of the P-type impurities in the first surface region will be thermally segregated into the guard ring oxide film. Second P-type implanted impurities are located in a second surface region of the super-junction structure in the termination region, and the second surface region and the first surface region have an overlapping region. The second P-type implanted impurities compensate for the reduction of the P-type impurities in the first surface region, thereby improving the PN balance of the super-junction structure in the termination region. The second P-type implanted impurities also reduce the N-type net doping amount of the second surface region of the N-type column in the termination region. A manufacturing method of the termination structure of the super-junction device is also disclosed. The present application can improve the PN balance of the termination structure, improve the device withstand voltage, and also expand the process window of the P-type column of the device, improve the consistency of the breakdown voltage of the device, and improve the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a termination structure for a super junction device; this invention also relates to a method for manufacturing a termination structure for a super junction device. Background Technology

[0002] Existing superjunction devices include a current-flowing region (also known as a charge-flowing region) and a voltage-bearing termination region, with a transition region between them. In the current-flowing region, there are alternating P-type pillars and N-type pillars, i.e., PN pillars, forming a superjunction structure. Typically, P-type pillars consist of P-type epitaxial layers filling trenches (superjunction trenches), while N-type pillars consist of N-type epitaxial layers between the P-type pillars. Taking a strip-shaped PN pillar structure as an example, each N-pillar has a gate structure above it, including planar gate structures and trench gate structures. For planar gate structures, this gate structure may partially cover the surrounding P-type pillars or not. Each P-type pillar has a P-type well above it, containing a source region composed of N+ regions. A contact hole is formed at the top of the source region, connecting it to the source electrode (metal source) composed of the front-side metal layer. Simultaneously, the bottom of the contact hole is connected to the P-type well through a high-concentration P+ contact region.

[0003] The transition region contains a P-type ring region connected to the P-type well in the current flow region. This P-type region has a contact hole, and below the contact hole is a high-concentration P+ contact region. Therefore, the P-type ring contacts the top contact hole through the P+ contact region and is connected to the source composed of the front metal layer through the top contact hole. In this way, the P-type ring, the P-type well in the current flow region, and the source region are all connected to the source.

[0004] The termination region is used to withstand the voltage between the source and drain regions laterally. In typical superjunction MOSFET devices, this termination region mainly consists of alternating PN pillars, or an additional cutoff region composed of N+ regions outside the alternating PN pillars. When reverse bias is applied between the source and drain regions, the carriers in these alternating PN pillars deplete each other, forming a depletion region to withstand the lateral voltage. To improve the device's competitiveness, a minimum termination size is required, which increases the lateral electric field strength of the PN pillars. This makes the device termination design more critical, especially as it can improve the source-drain breakdown voltage (BVdss) VsPN balance relationship, affecting the consistency of process window and product BVdss. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a termination structure for a superjunction device that improves the PN balance of the termination structure, enhances the breakdown voltage capability of the termination structure and thus improves the overall breakdown voltage capability of the superjunction device, expands the process window of the P-type pillars, and improves the breakdown voltage consistency and reliability of the device. To this end, this invention also provides a method for manufacturing the termination structure of the superjunction device.

[0006] To solve the above-mentioned technical problems, the present invention provides a superjunction device with a terminal structure in which the middle region of the superjunction device is a current flow region, the terminal region surrounds the outer periphery of the current flow region, and the transition region is located between the current flow region and the terminal region.

[0007] A superjunction structure is formed in the current flow region, the transition region, and the termination region. The superjunction structure is formed in a semiconductor substrate and is composed of alternating N-type pillars and P-type pillars. Each P-type pillar has a first initial P-type impurity, and each N-type pillar has a first initial N-type impurity. The superjunction unit consists of one N-type pillar and an adjacent P-type pillar.

[0008] The terminal structure is formed in the transition region and the terminal region, and the terminal structure includes: the superjunction structure, the protective epoxide film, and the second P-type implanted impurity.

[0009] The protective epoxide film covers the surface of the superjunction structure in the transition region and the terminal region.

[0010] Each of the P-type columns has a first surface region, and some of the P-type impurities in the first surface region will thermally segregate into the protective epoxide film, thereby reducing the amount of P-type impurities in the first surface region of each of the P-type columns.

[0011] The second P-type implanted impurity is located in the second surface region of the superjunction structure in the terminal region, and there is no second P-type implanted impurity in the current flow region; in the P-type pillar in the terminal region, the second surface region and the first surface region have an overlapping region, and the second P-type implanted impurity is used to compensate for the reduction of P-type impurities in the first surface region, thereby improving the PN balance of the superjunction structure in the terminal region. The second P-type implanted impurity also reduces the net N-type doping amount in the second surface region of the N-type pillar in the terminal region, so as to improve the breakdown voltage of the superjunction structure in the terminal region and improve the process window of the P-type pillar.

[0012] A further improvement is that the constituent film of the protective epoxide film includes a thermal oxide film.

[0013] A further improvement is that the first initial P-type impurity includes boron or boron fluoride.

[0014] A further improvement is that, in the current flow region, a P-type well is also formed on the surface of each of the P-type pillars, and the P-type well extends to the surface of the adjacent N-type pillar.

[0015] A P-type ring is formed in the transition region, and the P-type ring covers the surface of each of the superjunction units in the transition region.

[0016] The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than that of the P-type pillar, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than that of the P-type pillar.

[0017] A further improvement is that the second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions for the second P-type implanted impurity include 2E11cm. -2 ~8E11cm -2 .

[0018] A further improvement is that, by adjusting the second P-type implanted impurity, the withstand voltage capability of the superjunction structure in the terminal region is adjusted to be greater than that of the superjunction structure in the current flow region, so that the withstand voltage capability of the superjunction device is determined by the withstand voltage capability of the superjunction structure in the current flow region.

[0019] A further improvement is that the process window of the P-type pillar is the window for the variation of the doping concentration of the first initial P-type impurity in the P-type pillar. The minimum doping concentration of the P-type pillar is taken as the optimal equilibrium doping concentration, and the maximum doping concentration of the P-type pillar ensures that the breakdown voltage of the superjunction device meets the minimum breakdown voltage requirement. The improved breakdown voltage of the superjunction structure in the termination region enhances the breakdown voltage of the superjunction device, increases the maximum doping concentration of the P-type pillar, and expands the process window of the P-type pillar.

[0020] A further improvement is that a first epitaxial layer is formed on the surface of the semiconductor substrate, and the superjunction structure is formed in the first epitaxial layer.

[0021] The first epitaxial layer is a single epitaxial layer with a single resistivity.

[0022] Alternatively, the first epitaxial layer is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, wherein the resistivity of the second epitaxial sublayer is lower than that of the first epitaxial sublayer.

[0023] A further improvement is that the first epitaxial layer is N-type doped, the P-type pillars are composed of a second P-type doped epitaxial layer filled in the trenches, and the N-type pillars are composed of the first epitaxial layer between the P-type pillars;

[0024] The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type pillar.

[0025] To solve the above-mentioned technical problems, the manufacturing method of the terminal structure of the superjunction device provided by the present invention includes the following steps:

[0026] Step 1: Divide the formation region of the superjunction device into a current flow region, a transition region, and a termination region. The middle region of the superjunction device is the current flow region, the termination region surrounds the outer periphery of the current flow region, and the transition region is located between the current flow region and the termination region.

[0027] A superjunction structure is formed in the current flow region, the transition region, and the termination region. The superjunction structure is formed in a semiconductor substrate and is composed of alternating N-type pillars and P-type pillars. Each P-type pillar has a first initial P-type impurity, and each N-type pillar has a first initial N-type impurity. The superjunction unit consists of one N-type pillar and an adjacent P-type pillar.

[0028] Step 2: Perform selective P-type ion implantation to form a second P-type implanted impurity in the second surface region of the superjunction structure in the terminal region; there is no second P-type implanted impurity in the current flow region.

[0029] Step 3: Form a protective epoxide film and perform patterned etching on the protective epoxide film, wherein the patterned etching causes the protective epoxide film to exist only on the surface of the superjunction structure in the transition region and the terminal region.

[0030] During the formation of the protective epoxide film, some P-type impurities in the first surface region of each P-type column will thermally segregate into the protective epoxide film, thereby reducing the amount of P-type impurities.

[0031] In the P-type pillar in the terminal region, the second surface region and the first surface region have an overlapping area. The second P-type implanted impurity is used to compensate for the reduction of P-type impurities in the first surface region, thereby improving the PN balance of the superjunction structure in the terminal region. The second P-type implanted impurity also reduces the net N-type doping amount in the second surface region of the N-type pillar in the terminal region, thereby improving the breakdown voltage of the superjunction structure in the terminal region and improving the process window of the P-type pillar.

[0032] A further improvement is that, in step three, the protective epoxide film comprises a thermally oxidized film formed using a thermal oxidation process.

[0033] A further improvement is that the first initial P-type impurity includes boron or boron fluoride.

[0034] A further improvement is that, prior to step three, the following is also included:

[0035] A P-type well is formed in the current flow region, the P-type well being located on the surface of each of the P-type pillars and extending to the surface of the adjacent N-type pillars.

[0036] A P-type ring is formed in the transition region, and the P-type ring covers the surface of each of the superjunction units in the transition region.

[0037] The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than that of the P-type pillar, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than that of the P-type pillar.

[0038] A further improvement is that the second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions for the second P-type implanted impurity include 2E11cm. -2 ~8E11cm -2 .

[0039] A further improvement is that, by adjusting the second P-type implanted impurity, the withstand voltage capability of the superjunction structure in the terminal region is adjusted to be greater than that of the superjunction structure in the current flow region, so that the withstand voltage capability of the superjunction device is determined by the withstand voltage capability of the superjunction structure in the current flow region.

[0040] A further improvement is that the process window of the P-type pillar is the window for the variation of the doping concentration of the first initial P-type impurity in the P-type pillar. The minimum doping concentration of the P-type pillar is taken as the optimal equilibrium doping concentration, and the maximum doping concentration of the P-type pillar ensures that the breakdown voltage of the superjunction device meets the minimum breakdown voltage requirement. The improved breakdown voltage of the superjunction structure in the termination region enhances the breakdown voltage of the superjunction device, increases the maximum doping concentration of the P-type pillar, and expands the process window of the P-type pillar.

[0041] A further improvement is that a first epitaxial layer is formed on the surface of the semiconductor substrate, and the superjunction structure is formed in the first epitaxial layer.

[0042] The first epitaxial layer is a single epitaxial layer with a single resistivity.

[0043] Alternatively, the first epitaxial layer is formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, wherein the resistivity of the second epitaxial sublayer is lower than that of the first epitaxial sublayer.

[0044] A further improvement is that the first epitaxial layer is N-type doped, and step one includes the following sub-steps:

[0045] Multiple trenches are formed in the first epitaxial layer.

[0046] A second epitaxial layer doped with P-type is filled in the trench, and the second epitaxial layer doped with P-type is filled in the trench as a component of the P-type pillar. The N-type pillar is composed of the first epitaxial layer between the P-type pillars.

[0047] The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type pillar.

[0048] This invention adds a second P-type implanted impurity to the second surface region of the superjunction structure in the termination region. The second P-type implanted impurity is implanted into both the P-type pillars and the N-type pillars. In the P-type pillars, the second P-type implanted impurity can compensate for the reduction in P-type impurities in the first surface region of the P-type pillars caused by the thermal segregation of P-type impurities between the semiconductor substrate and the protective epoxy film, thereby improving the PN balance between the P-type and N-type pillars in the first surface region of the termination region. The second P-type implanted impurity can also simultaneously reduce the net N-type doping in the second surface region of the N-type pillars. The reduction in net N-type doping is more conducive to the depletion of the surface region of the N-type pillars, and the change in electric field intensity in the surface region of the N-type pillars is more slow. Combined with the improvement in PN balance, the breakdown voltage of the superjunction structure in the termination region can be improved. Since the termination structure is mainly used to withstand lateral voltage, it can also improve the ability of the device termination to withstand lateral voltage, and finally improve the breakdown voltage of the entire superjunction structure. When the corresponding superjunction device is a superjunction MOSFET, the source-drain breakdown voltage (BVdss) of the device can be improved.

[0049] For superjunction devices, the P-type pillars in the superjunction structure are usually formed by a P-type epitaxial layer filled in the trench. Therefore, expanding the process window of the P-type pillars is the most critical technology for superjunction devices. This invention expands the process window of the P-type pillars by adding a second P-type implanted impurity, thereby optimizing the device performance. The main reason is that the second P-type implanted impurity of this invention can increase the breakdown voltage of the superjunction structure in the termination region. Through optimization, the breakdown voltage of the device can be determined by the breakdown voltage of the superjunction structure in the current flow region. Compared with the breakdown voltage of the superjunction structure in the termination region, which is very sensitive to the concentration of the P-type pillars, the breakdown voltage of the superjunction structure in the current flow region is less sensitive to the concentration of the P-type pillars, thus expanding the process window of the P-type pillars.

[0050] With the expansion of the process window for P-type pillars, the range of adjustment for P-type pillar concentration will increase, which is more conducive to improving the performance of superjunction devices. For example, by increasing the doping concentration of P-type pillars, the single-pulse avalanche energy (EAS) performance of the device can be further improved.

[0051] In addition, by improving the breakdown voltage capability of the superjunction structure in the termination region, this invention makes it easy to configure the superjunction device to break down first in the active region, i.e., the current flow region. Compared with the characteristic that the breakdown voltage is unstable when the breakdown occurs in the termination region, the breakdown voltage is located at the interface between the semiconductor substrate and the protective epoxy layer. When the breakdown occurs in the current flow region, the breakdown voltage is located inside the semiconductor substrate, so the breakdown voltage is stable. This can improve the consistency and stability of the breakdown voltage of the superjunction device, such as the BVdss of the superjunction MOSFET.

[0052] Furthermore, the second P-type implanted impurity of the present invention is selectively implanted and will not form in the current flow region, thus not affecting the on-resistance of the device in the current flow region.

[0053] In addition, during the reverse recovery process of the body diode of a superjunction device such as a superjunction MOSFET, the second P-type implanted impurity of the present invention is more inclined to pump holes in the terminal region during the pumping process to the P-type ring in the transition region, which is conducive to hole pumping and thus reduces the possibility of damage to the body diode. Attached Figure Description

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0055] Figure 1 This is a top view of the superjunction device according to an embodiment of the present invention;

[0056] Figure 2 This is a cross-sectional schematic diagram of the superjunction device according to an embodiment of the present invention;

[0057] Figures 3A-3I This is a cross-sectional schematic diagram of the device in each step of the manufacturing method of the superjunction device according to an embodiment of the present invention;

[0058] Figure 4 This is a flowchart of a method for manufacturing a superjunction device according to an embodiment of the present invention;

[0059] Figure 5 This is a test graph showing the relationship between the BVdss and the doping concentration of the P-type pillars of the superjunction device in this invention and existing superjunction devices. Detailed Implementation

[0060] like Figure 2 The diagram shown is a cross-sectional schematic of a superjunction device according to an embodiment of the present invention. In the terminal structure of the superjunction device according to an embodiment of the present invention, the middle region of the superjunction device is a current flow region, the terminal region surrounds the outer periphery of the current flow region, and the transition region is located between the current flow region and the terminal region. Figure 2 In this context, the current flow region is region 1, also known as the active region; the transition region is region 2; and the terminal region is region 3.

[0061] A superjunction structure is formed in the current flow region, the transition region, and the termination region. The superjunction structure is formed in the semiconductor substrate 1 and includes alternating N-type pillars and P-type pillars. Each P-type pillar has a first initial P-type impurity, and each N-type pillar has a first initial N-type impurity. The superjunction unit includes one N-type pillar and an adjacent P-type pillar.

[0062] In this embodiment of the invention, a first epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the superjunction structure is formed in the first epitaxial layer 2. The first epitaxial layer 2 is N-type doped, and the P-type pillars are composed of a second P-type doped epitaxial layer filling the trenches. The N-type pillars are composed of the first epitaxial layer 2 between the P-type pillars.

[0063] In some embodiments, the semiconductor substrate 1 is a silicon substrate. The first epitaxial layer 2 is a silicon epitaxial layer.

[0064] Figure 2 In the diagram, the trench in zone 1 is marked with a separate label 41, the trench in zone 2 is marked with a separate label 42, and the trench in zone 3 is marked with a separate label 43; the P-shaped column in zone 1 is marked with a separate label 51, the P-shaped column in zone 2 is marked with a separate label 52, and the P-shaped column in zone 3 is marked with a separate label 53. Figure 2 In the diagram, Wp1 represents the width of trench 41, which is also the width of P-type column 51; Wp2 represents the width of trench 42, which is also the width of P-type column 52; Wp3 represents the width of trench 43, which is also the width of P-type column 53; Wn1 represents the width of N-type column in zone 1; Wn2 represents the width of N-type column in zone 2; and Wn3 represents the width of N-type column in zone 3.

[0065] Figure 2 In this embodiment, the P-type pillar is composed of a second epitaxial layer doped with P-type filling the trench. In other embodiments, the P-type pillar may also be formed by stacking a second epitaxial layer doped with P-type filling the trench plus a P-type implantation layer at the bottom of the trench.

[0066] In some embodiments, the first epitaxial layer 2 is a single epitaxial layer with a uniform resistivity. In other embodiments, the first epitaxial layer 2 may also be composed of a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, wherein the resistivity of the second epitaxial sublayer is lower than that of the first epitaxial sublayer.

[0067] The terminal structure is formed in the transition region and the terminal region, and the terminal structure includes: the superjunction structure, the protective epoxide film 7, and the second P-type implanted impurity 61.

[0068] The protective epoxide film 7 covers the surface of the superjunction structure in the transition region and the terminal region.

[0069] Each of the P-type pillars 53 in the terminal region has a first surface area, and some of the P-type impurities in the first surface area will thermally segregate into the protective epoxide film 7, thereby reducing the amount of P-type impurities in the first surface area of ​​each P-type pillar.

[0070] The second P-type implanted impurity 61 is located in the second surface region of the superjunction structure in the terminal region; in the P-type pillar in the terminal region, the second surface region and the first surface region have an overlapping region. The second P-type implanted impurity 61 is used to compensate for the reduction of P-type impurities in the first surface region, thereby improving the PN balance of the superjunction structure in the terminal region. The second P-type implanted impurity 61 also reduces the net N-type doping amount in the second surface region of the N-type pillar in the terminal region, so as to improve the breakdown voltage of the superjunction structure in the terminal region and improve the process window of the P-type pillar.

[0071] The absence of the second P-type injected impurity 61 in the current flow region avoids the adverse effect of the second P-type injected impurity 61 on the on-resistance of the device.

[0072] In this embodiment of the invention, the protective epoxide film 7 comprises a thermal oxide film.

[0073] The first initial P-type impurity includes boron or boron fluoride.

[0074] During the thermal oxidation process of the thermal oxide film, boron in the first surface region of the P-type pillar is easily adsorbed into the thermal oxide film at the Si-SiO2 interface between the semiconductor substrate 1 and the protective epoxy film 7, thereby reducing the P-type doping concentration in the first surface region of the P-type pillar.

[0075] In the current flow region, a P-type well 6 is also formed on the surface of each P-type pillar, and the P-type well 6 extends to the surface of the adjacent N-type pillar.

[0076] A P-type ring 6a is formed in the transition region, and the P-type ring 6a covers the surface of each of the superjunction units in the transition region. The doping concentration of the P-type well 6 is 1 to 2 orders of magnitude higher than that of the P-type pillar, and the doping concentration of the P-type ring 6a is 1 to 2 orders of magnitude higher than that of the P-type pillar.

[0077] Figure 2In this context, the P-type well 6 is also denoted by P, and the P-type ring 6a is also denoted by P'. In some embodiments, the P-type well 6 and the P-type ring 6a are formed simultaneously using the same process.

[0078] In the current flow region and the transition region, although the amount of P-type impurities in the first surface regions of each of the P-type pillars 51 and 52 may decrease due to thermal segregation into the protective epoxy film 7, the amount of P-type impurities reduced by thermal segregation is much smaller than the P-type doping amount of the P-type well 6 and the P-type ring 6a, since both the P-type well 6 and the P-type ring 6a cover the corresponding first surface regions of the P-type pillars 51 and 52. Therefore, the impact on the P-type doping concentration of the P-type well 6 and the P-type ring 6a is negligible and will not adversely affect the device performance. In this invention, only the reduction in the amount of P-type impurities in the first surface region of the P-type pillar 53 in the terminal region will have an adverse effect, that is, it will adversely affect the PN balance of the top region of the P-type pillar 53 and the N-type pillar, and thus affect the device's breakdown voltage, i.e., the source-drain breakdown voltage will decrease.

[0079] In some embodiments, the second P-type implanted impurity 61 comprises boron or boron fluoride, and the implantation conditions of the second P-type implanted impurity 61 include 2E11cm. -2 ~8E11cm -2 .

[0080] In this embodiment of the invention, by adjusting the second P-type implanted impurity 61, the withstand voltage capability of the superjunction structure in the terminal region is adjusted to be greater than that of the superjunction structure in the current flow region, so that the withstand voltage capability of the superjunction device is determined by the withstand voltage capability of the superjunction structure in the current flow region.

[0081] The process window of the P-type pillar is the variation window of the doping concentration of the first initial P-type impurity in the P-type pillar. The lowest doping concentration of the P-type pillar is the optimal equilibrium doping concentration, and the highest doping concentration of the P-type pillar ensures that the breakdown voltage of the superjunction device meets the minimum breakdown voltage requirement. The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type pillar. The process window of the P-type pillar is the most critical feature of the superjunction device, and expanding the process window of the P-type pillar is the most critical process technology for the superjunction device. In the method of this embodiment, since the breakdown voltage of the superjunction structure in the terminal region is improved, the breakdown voltage of the entire device is also improved. Therefore, the highest doping concentration of the process window of the P-type pillar is also increased, thus expanding the process window of the P-type pillar.

[0082] In addition, by setting the process window of the P-type pillar to between the optimal equilibrium doping concentration and the maximum doping concentration, the doping concentration of the P-type pillar will be greater than or equal to the doping concentration of the N-type pillar. This not only ensures the withstand voltage but also helps to improve the EAS performance of the device.

[0083] like Figure 2 As shown in the embodiment of the present invention, the current flow region further includes:

[0084] The gate structure adopts a planar gate, which is composed of a gate oxide film 8 and a polysilicon gate 9 stacked together.

[0085] Each of the polysilicon gates 9 covers the corresponding P-type well 6 and extends to the surface of the N-type pillar between the P-type wells 6. The surface of the P-type well 6 covered by the polysilicon gate 9 is used to form a channel.

[0086] In some embodiments, a JFET region is also formed on the surface of the N-type pillar between the P-type wells 6 in the current flow region.

[0087] A source region 10, composed of N+ regions, is formed on the surface of the P-type well 6, and the source region 10 and the polysilicon gate 9 are self-aligned sideways. An N+-doped stop region 10a is included at the outermost periphery of the terminal region, and the stop region 10a and... Figure 1 The cutoff region corresponding to mark 21 in the text has the same structure.

[0088] In some embodiments, the thickness of the protective epoxide film 7 is [missing information]. The process temperature for the thermal oxidation of the protective epoxy film 7 is above 800°C.

[0089] For MOSFETs operating at 500V to 700V, i.e., superjunction MOSFETs, the thickness of the gate oxide film 8 is [missing information]. The thickness of the polysilicon gate 9 is

[0090] The process conditions for the P-type trap 6 need to meet the threshold voltage requirement. For devices with a threshold voltage of 2-4V, the ion implantation process conditions for the P-type trap 6 can be B 30-100keV, that is: the implanted impurity is boron, and the implantation dose is 3E13cm. -2 ~1E14cm -2 The injection energy is 30keV to 100keV. The P-type ring 6a is formed simultaneously using the same process as the P-type trap 6.

[0091] The ion implantation process conditions for the source region 10 are as follows: the implanted impurity is phosphorus or arsenic, and the implantation dose is 3E15cm. -2 ~5E15cm-2 The injected energy is 30keV to 100keV. The process conditions of the cutoff region 10a are the same as those of the source region 10 and are formed simultaneously.

[0092] like Figure 2 As shown, in the current flow region, the superjunction device further includes the following front-side structure:

[0093] Interlayer 11, contact hole 12a, source 14 composed of front metal layer and gate (not shown).

[0094] Contact hole 12a passes through interlayer film 11. Source region 10 is connected to source electrode 14 through corresponding contact hole 12a at the top, and polysilicon gate 9 is connected to gate electrode through corresponding contact hole 12a at the top.

[0095] The thickness of the interlayer membrane 11 is 8000 angstroms to 10000 angstroms.

[0096] The contact hole 12a corresponding to the top of the source region 10 also passes through the source region 10 and contacts the P-type well 6 at the bottom, and a P+ doped well contact region 13 is formed at the bottom of the contact hole 12a corresponding to the source region 10.

[0097] The superjunction device also includes the following back-side structure:

[0098] The N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1. The semiconductor substrate 1 adopts an N-type heavily doped structure and the drain region of the superjunction device is directly formed after the semiconductor substrate 1 is thinned. A drain electrode composed of a back metal layer 15 is formed on the back side of the drain region.

[0099] In the transition region, the P-ring 6a is connected to the source electrode 14 through the contact hole 12b.

[0100] In the terminal region, a polycrystalline silicon field plate 9a is also formed on the surface of the protective epoxy film 7. The polycrystalline silicon field plate 9a is connected to an electrode 14b composed of a front metal layer through a contact hole. The electrode 14b can be a gate.

[0101] In this embodiment of the invention, a second P-type implanted impurity 61 is added to the second surface region of the superjunction structure in the termination region. The second P-type implanted impurity 61 is implanted into both the P-type pillars and the N-type pillars. In the P-type pillars, the second P-type implanted impurity 61 can compensate for the reduction in P-type impurities in the first surface region of the P-type pillars caused by the thermal segregation of P-type impurities between the semiconductor substrate 1 and the protective epoxy film 7, thereby improving the PN balance between the P-type pillars and N-type pillars in the first surface region of the termination region. The second P-type implanted impurity 61 can also simultaneously reduce the net N-type doping in the second surface region of the N-type pillars. The reduction in the net N-type doping is more conducive to the depletion of the surface region of the N-type pillars, and the change in the electric field intensity of the surface region of the N-type pillars is more slow. Combined with the improvement in PN balance, the breakdown voltage of the superjunction structure in the termination region can be improved. Since the termination structure is mainly used to withstand lateral voltage, it can also improve the ability of the device termination to withstand lateral voltage, and finally improve the breakdown voltage of the entire superjunction structure. When the corresponding superjunction device is a superjunction MOSFET, the source-drain breakdown voltage (BVdss) of the device can be improved.

[0102] For superjunction devices, the P-type pillars in the superjunction structure are usually formed by a P-type epitaxial layer filled in the trench. Therefore, expanding the process window of the P-type pillars is the most critical technology for superjunction devices. In this embodiment of the invention, the process window of the P-type pillars can be expanded by adding a second P-type implanted impurity 61, thereby optimizing the performance of the device. The main reason is that the second P-type implanted impurity 61 of the present invention can increase the breakdown voltage of the superjunction structure in the termination region. Through optimization, the breakdown voltage of the device can be determined by the breakdown voltage of the superjunction structure in the current flow region. Compared with the breakdown voltage of the superjunction structure in the termination region, which is very sensitive to the concentration of the P-type pillars, the breakdown voltage of the superjunction structure in the current flow region is less sensitive to the concentration of the P-type pillars, thus expanding the process window of the P-type pillars.

[0103] With the expansion of the process window for P-type pillars, the range of adjustment for P-type pillar concentration will increase, which is more conducive to improving the performance of superjunction devices. For example, by increasing the doping concentration of P-type pillars, the single-pulse avalanche energy (EAS) performance of the device can be further improved.

[0104] Furthermore, by improving the withstand voltage capability of the superjunction structure in the termination region, this embodiment of the invention makes it easy to configure the superjunction device to break down first in the active region, i.e., the current flow region. Compared to the characteristic that the breakdown voltage is unstable when the breakdown occurs in the termination region, which is located at the interface between the semiconductor substrate 1 and the protective epoxy layer, the breakdown voltage is located inside the semiconductor substrate 1 when the current flow region breaks down, thus ensuring that the breakdown voltage is stable. This improves the consistency and stability of the breakdown voltage of the superjunction device, such as the BVdss of the superjunction MOSFET.

[0105] In addition, the second P-type implanted impurity 61 in this embodiment of the invention is selectively implanted and will not form in the current flow region, so it will not affect the on-resistance of the device in the current flow region.

[0106] In addition, during the reverse recovery process of the body diode of a superjunction device such as a superjunction MOSFET, the second P-type injected impurity 61 in this embodiment of the invention is more inclined to pump holes in the terminal region during the pumping process to the P-type ring 6a in the transition region, which is conducive to hole pumping and thus reduces the possibility of damage to the body diode.

[0107] Compared to existing technologies, this invention injects a certain concentration of P-type impurities into the upper part of the P-type pillars and the upper part of the N-type epitaxial layer in the termination region. This compensates for the reduction of P-type impurities at the top of the P-type pillars caused by boron segregation during the thermal oxidation film formation process after the PN pillars are formed. Simultaneously, the concentration at the top of the N-type epitaxial layer is reduced, making it easier for the PN depletion to unfold in the top region and resulting in a more uniform electric field distribution in the N region. This improves the reverse bias withstand capability of the termination region and enhances the primary-drain breakdown capability of the device. Furthermore, the increased concentration of P-type pillars at the top of the termination region reduces the sensitivity of the device's termination BVdss to the deviation between the P-pillar and N-pillar impurity concentrations, thereby expanding the process window for P-type impurity concentration and improving device consistency.

[0108] In existing device fabrication processes, after the P-type pillar is epitaxially formed, a Pwell is formed. Pwells are primarily formed in the active and transition regions of the device, typically covering the top of the P-type pillar. The impurity concentration in the Pwell is generally 1-2 orders of magnitude higher than that in the P-type pillar. When the device is reverse biased, the Pwell is connected to the source through a P+ layer implanted via a contact hole, and is at 0 potential.

[0109] After Pwell formation, existing technologies require the formation of a field oxide layer (Field OX), i.e., the protective epoxide layer. Field oxide is typically formed through thermal oxidation, with a thickness of 6000-10000 angstroms. During thermal oxidation, P-type impurities B or BF2 (B is generally used in the process) at the top of the P-type pillars are adsorbed into the thermal oxide film, causing a decrease in the P-type impurity concentration within the SI. This problem is addressed in areas with Pwell implantation, where the P-type impurity concentration in the Pwell is much higher than that in the P-type pillars; the surface concentration of the Pwell is typically approximately E17 / cm³. 3 The concentration of P-type impurities in a P-type column, including its top, is approximately E15 / cm³. 3Therefore, in the active or transition regions, the loss of boron (B) in Si during the thermal oxide film formation process has no significant impact on device performance. However, in the voltage-bearing termination region, since only P-type impurities are filled through P-type epitaxial growth, the loss of B during thermal oxide film formation will cause a net reduction in P-type impurities at the top of the P-type pillars. This affects the balance between P-type and N-type impurities at the top of the termination region, thus affecting the BVdss of the termination and consequently the BVdss of the device.

[0110] In this embodiment of the invention, by introducing photolithography to open the terminal region and then performing ion implantation in the terminal region, the reduction of P-type impurities during the thermal oxidation process can be compensated, thereby improving the PN balance in the terminal region and enhancing the device's BVdss.

[0111] Experiments have shown that this fabrication process can expand the concentration window of the P-type column, improving the fabrication capability of the device and the consistency of BVdss.

[0112] One advantage of increasing the concentration of P-type impurities at the top of the P-pillar through ion implantation in the terminal region is that, during the reverse recovery process of the body diode, the holes in the terminal region are more biased towards pumping as they are pumped into the transition region (which usually has a Pwell implantation ring), which can reduce the possibility of damage to the body diode.

[0113] like Figures 3A to 3I The diagram shown is a cross-sectional view of the device in each step of the manufacturing method of the superjunction device according to an embodiment of the present invention; the manufacturing method of the terminal structure of the superjunction device according to an embodiment of the present invention includes the following steps:

[0114] Step 1: Divide the formation region of the superjunction device into a current flow region, a transition region, and a termination region. The middle region of the superjunction device is the current flow region, the termination region surrounds the outer periphery of the current flow region, and the transition region is located between the current flow region and the termination region.

[0115] A superjunction structure is formed in the current flow region, the transition region, and the termination region. The superjunction structure is formed in the semiconductor substrate 1 and is composed of alternating N-type pillars and P-type pillars. Each P-type pillar has a first initial P-type impurity, and each N-type pillar has a first initial N-type impurity. The superjunction unit consists of one N-type pillar and an adjacent P-type pillar.

[0116] In the method of this embodiment, a first epitaxial layer 2 is formed on the surface of the semiconductor substrate 1, and the superjunction structure is formed in the first epitaxial layer 2. In some embodiments, the first epitaxial layer 2 is a single epitaxial layer with a uniform resistivity. In other embodiments, the first epitaxial layer 2 may be formed by stacking a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, wherein the resistivity of the second epitaxial sublayer is lower than the resistivity of the first epitaxial sublayer.

[0117] The semiconductor substrate 1 is a silicon substrate. The first epitaxial layer 2 is a silicon epitaxial layer.

[0118] The first initial P-type impurity includes boron or boron fluoride.

[0119] The first epitaxial layer 2 is N-type doped, and step one includes the following sub-steps:

[0120] like Figure 3A As shown, a hard mask layer 3 is formed.

[0121] The hard mask layer 3 is patterned to define the formation area of ​​the trench.

[0122] Using the hard mask layer 3 as a mask, the first epitaxial layer 2 is etched to form multiple trenches in the first epitaxial layer 2. Figure 3A In the diagram, the grooves in zones 1, 2, and 3 are marked with 41, 42, and 43, respectively, and have widths of Wp1, Wp2, and Wp3.

[0123] like Figure 3B As shown, a second epitaxial layer doped with P-type is filled in the trench, and the P-type pillar is composed of the second epitaxial layer doped with P-type filled in the trench. The N-type pillar is composed of the first epitaxial layer 2 between the P-type pillars. Figure 3B In the diagram, the P-type pillars in regions 1, 2, and 3 are marked with numerals 51, 52, and 53, respectively. In other embodiments, a P-type ion implantation region can be formed at the bottom of the trench before filling the second epitaxial layer. The P-type pillar is formed by stacking the P-type ion implantation region and the second epitaxial layer filling the trench. The P-type ion implantation region at the bottom of the P-type pillar can eliminate the problem of reduced consistency caused by inconsistent trench depth.

[0124] The method in this embodiment of the invention further includes:

[0125] like Figure 3C As shown, a P-type well 6 is formed in the current flow region, the P-type well 6 being located on the surface of each of the P-type pillars and extending to the surface of the adjacent N-type pillars.

[0126] A P-type ring 6a is formed in the transition region, the P-type ring 6a covering the surface of each of the superjunction units in the transition region. In some embodiments, the P-type ring 6a and the P-type well 6 are formed simultaneously using the same process; in other embodiments, the P-type ring 6a may be formed using separate photolithography definition and ion implantation.

[0127] The doping concentration of the P-type well 6 is 1 to 2 orders of magnitude higher than that of the P-type pillar, and the doping concentration of the P-type ring 6a is 1 to 2 orders of magnitude higher than that of the P-type pillar.

[0128] Step Two, as follows Figure 3D As shown, selective P-type ion implantation is performed to form a second P-type implanted impurity 61 in the second surface region of the superjunction structure in the terminal region; the second P-type implanted impurity 61 is absent in the current flow region. Figure 3D In the diagram, the selective P-type ion implantation is indicated by the arrow line corresponding to marker 102, and the selected implantation area is defined by the pattern of photoresist 101.

[0129] In some embodiments, the second P-type implanted impurity 61 comprises boron or boron fluoride, and the implantation conditions for the second P-type implanted impurity 61 include 2E11cm. -2 ~8E11cm -2 .

[0130] Step 3, as follows Figure 3E As shown, a protective epoxide film 7 is formed and the protective epoxide film 7 is patterned and etched so that the protective epoxide film 7 exists only on the surface of the superjunction structure in the transition region and the terminal region.

[0131] During the formation of the protective epoxide film 7, some P-type impurities in the first surface region of each P-type column will thermally segregate into the protective epoxide film 7, thereby reducing the amount of P-type impurities.

[0132] In the P-type pillar in the terminal region, the second surface region and the first surface region have an overlapping area. The second P-type implanted impurity 61 is used to compensate for the reduction of P-type impurities in the first surface region, thereby improving the PN balance of the superjunction structure in the terminal region. The second P-type implanted impurity 61 also reduces the net N-type doping amount in the second surface region of the N-type pillar in the terminal region, thereby improving the breakdown voltage of the superjunction structure in the terminal region and improving the process window of the P-type pillar.

[0133] In the method of this embodiment, the protective epoxy film 7 is formed by patterning a thermal oxide film formed by a thermal oxidation process. That is, the thermal oxide film, i.e., the thick field oxide film, is first formed, and then the thermal oxide film is patterned and etched to form the protective epoxy film 7.

[0134] In the method of this embodiment of the invention, by adjusting the second P-type implanted impurity 61, the withstand voltage capability of the superjunction structure in the terminal region is adjusted to be greater than that of the superjunction structure in the current flow region, so that the withstand voltage capability of the superjunction device is determined by the withstand voltage capability of the superjunction structure in the current flow region.

[0135] The process window of the P-type pillar is the window for the variation of the doping concentration of the first initial P-type impurity in the P-type pillar. The minimum doping concentration of the P-type pillar is taken as the optimal equilibrium doping concentration, and the maximum doping concentration of the P-type pillar ensures that the breakdown voltage of the superjunction device meets the minimum breakdown voltage requirement. The improved breakdown voltage of the superjunction structure in the termination region enhances the breakdown voltage of the superjunction device, increases the maximum doping concentration of the P-type pillar, and expands the process window of the P-type pillar.

[0136] In step one, the fluctuation range of the P-type doping concentration of the second epitaxial layer lies within the process window of the P-type pillar. It is evident that the larger the process window of the P-type pillar, the lower the precision requirement for controlling the doping concentration of the second epitaxial layer, thus being more conducive to the formation of the second epitaxial layer.

[0137] The method of this embodiment of the invention further includes the following steps:

[0138] Step 4, as follows Figure 3F As shown, a gate oxide film 8 is formed using a thermal oxidation process, followed by the formation of a polysilicon gate 9.

[0139] In the method of this embodiment of the invention, for a superjunction MOSFET with a voltage range of 500V to 700V, the thickness of the gate oxide film 8 is [missing information]. The thickness of the polysilicon gate 9 is

[0140] Step 5, as follows Figure 3F As shown, the polysilicon gate 9 and the gate oxide film 8 are sequentially etched using a photolithography-defined etching process to form the planar gate structure, which is formed by the superposition of the etched gate oxide film 8 and the polysilicon gate 9. Simultaneously with the formation of the polysilicon gate 9, a polysilicon field plate 9a is formed on the surface of the protective ring oxide film 7.

[0141] The planar gate structure is located in the current flow region and consists of an N-type pillar 2 and an adjacent P-type pillar 51 forming a superjunction unit. The polysilicon gate 9 corresponding to each of the sub-gate planar gate structures covers the corresponding P-type well 6 and extends to the top of the N-type pillar between adjacent P-type wells 6. The surface of the P-type well 6 covered by the polysilicon gate 9 is used to form a channel.

[0142] Step Six, as Figure 3G As shown, the surface of the P-type well 6, which is formed by photolithography and N+ ion implantation in the current flow region, is composed of an N+ region as the source region 10 and the cutoff region 10a is formed on the outermost side of the terminal region. The source region 10 and the polysilicon gate 9 are self-aligned.

[0143] The ion implantation process conditions for the source region 10 are as follows: the implanted impurity is phosphorus or arsenic, and the implantation dose is 3E15cm. -2 ~5E15cm -2 The injected energy is 30keV to 100keV.

[0144] Step 7, as follows Figure 3H As shown, an interlayer film 11 is deposited, and an opening for contact holes through the interlayer film 11 is formed using a photolithography and etching process. Figure 3F The openings of the intermediate contact holes are marked with 121a and 121b, respectively.

[0145] The interlayer film 11 is a combination of an undoped oxide film and a BPSG film. The thickness of the interlayer film 11 is...

[0146] During the etching of the contact hole 121a in the current flow region, the N+ at its bottom, i.e., the source region 10, needs to be etched away, which requires silicon over-etching. The silicon over-etching amount can be between 2000 angstroms and 4000 angstroms, and the specific amount needs to be determined according to the ion implantation conditions, i.e., the implantation dose and implantation energy, corresponding to the source region 10.

[0147] like Figure 3I As shown, after the contact hole openings are formed and before metal filling, a step of forming a trap contact region 13 by P+ ion implantation at the bottom of the openings 121a and 121b of the contact hole is included. Preferably, the impurities implanted in the trap contact region 13 by the P-type implantation are B, BF2, or a combination of B and BF2, and the implantation energy is generally between 30 keV and 80 keV, with an implantation dose of 1E15cm. -2 ~3E15cm -2Optimizing the injection conditions can improve the device's resistance to current surges. To further enhance the softness of the reverse recovery process of the body diode, the energy and dose of the P-type injection in the well contact region 13 can be reduced; for example, the energy can be BF2, 5keV to 40KEV, 5E14cm. -2 ~2E15 cm -2 The choice of dose can ensure the minimum dose required to form an ohmic contact, and the choice of energy mainly takes into account the capability of the ion implantation equipment.

[0148] like Figure 2 As shown, after the contact hole etching and bottom P+ ion implantation are completed, a blocking layer composed of Ti and TiN stacks is deposited. Then, tungsten (W) is deposited to fill the opening of the contact hole, forming contact holes 12a and 12b. For the opening of the contact hole with a width of 0.6 micrometers, the thickness of W can be set to 4000 angstroms. Afterwards, plasma dry etching is performed to completely remove the surface metal. When all contact hole dimensions are relatively large, for example, with an aspect ratio less than or equal to 0.5, AlCu or AlSiCu can be used to achieve complete filling, only Ti-TiN deposition is required, without W deposition and corresponding etching.

[0149] Step 8, as follows Figure 2 As shown, a front-side metal layer is formed by front-side metal deposition. A photolithography and metal etching process is used to form the gate, source 14, and electrode 14a, all composed of the front-side metal layer. Each source region 18 and its corresponding P-type well 6 are connected to the source 14 through identical top contact holes 12a. The polysilicon gate 9 is connected to the gate through a corresponding top contact hole (not shown). The polysilicon field plate 9a is connected to the electrode 14b through contact holes, and the electrode 14b can serve as the gate.

[0150] The material of the front metal layer can be AlSi, AlSiCu, or it can have a barrier layer, which can be a Ti / TiN layer, i.e., a superposition of Ti and TiN, or TiN. The total thickness of the front metal layer is generally between 4 μm and 6 μm.

[0151] Next, the semiconductor substrate 1 is thinned on the back side, and the drain region is formed by the N+ region formed in the thinned semiconductor substrate 1. The drain region can be formed directly by the heavily doped semiconductor substrate 1, or by implanting N-type heavily doped ions into the semiconductor substrate 1. Then, a back metal layer 15 is deposited on the back side of the semiconductor substrate 1, i.e., the drain region 11, to form the drain electrode.

[0152] The following example, a 650V superjunction MOSFET, will be used to further illustrate the parameters employed in the method of this invention:

[0153] The first epitaxial layer 2 can have a thickness of 50 micrometers, consisting of two layers: a top layer with a resistivity of 1.25 ohm·cm, phosphorus-doped, and a thickness of 20 micrometers; and a bottom layer with a resistivity of 1.5 ohm·cm, phosphorus-doped, and a thickness of 30 micrometers. The trench width is set to 4.5 micrometers, and the distance between the trenches is also set to 4.5 micrometers.

[0154] Figure 2 This is the device structure of the method in this embodiment of the invention. Compared with existing devices, this structure has a P-type implantation at the top of the terminal region of the device, forming a second P-type implanted impurity 61. This increases the amount of P-type impurities at the top of the P-type pillar, reduces the concentration of the N-region at the top of the terminal region, and increases the amount of impurities at the top of the P-type pillar. This fabrication process may include the following steps:

[0155] Step 1:

[0156] A dielectric film, namely the hard mask layer 3, is deposited on the first epitaxial layer 2. The area requiring trenches is defined by trench photolithography, and then the trenches are formed by dry etching. The semiconductor substrate 1 is a silicon substrate. The first epitaxial layer 2 is a silicon epitaxial layer.

[0157] After the trenches are formed, a P-type epitaxial layer, also known as the second epitaxial layer, is deposited within them. The silicon on the wafer surface is then removed using chemical mechanical polishing, thus forming P-type pillars within the trenches. The surface oxide film is then either removed or retained.

[0158] The trench depth here is typically 42 micrometers. A P-type ion implantation can also be performed at the bottom of the trench, for example, 120-180 keV, B, 1.0E12-2.0E12 / cm. 2 The dielectric film here, i.e., the hard mask layer 3, can be a single oxide film, such as an oxide film with a thickness of more than 1 micrometer. This oxide film can serve as a hard mask during trench etching. After the trench is formed, an oxide film of a certain thickness remains, such as an oxide film with a thickness of 0.1-0.2 micrometers. During the CMP process after epitaxial filling is completed, this oxide film serves as a protective layer for N-type epitaxy during CMP, so that the Si at that location is not defective due to the CMP process, causing leakage or quality problems.

[0159] The dielectric film here can also consist of an oxide film with a thickness of 0.1-0.15 micrometers, a SiN film with a thickness of 0.1-0.2 micrometers, and an oxide film with a thickness of more than 1 micrometer on top. This allows for better control of uniformity during the fabrication process: for example, after trench etching is completed, at least some SiN is left on the oxide film below it. Before epitaxial growth, the SiN is removed. This results in good uniformity of the oxide film before epitaxial growth, which also improves the uniformity of CMP.

[0160] A further improvement to the above-mentioned multilayer film structure is that the first oxide film is formed by thermal oxidation, which further improves the uniformity.

[0161] The formation step of the P-type well 6 includes:

[0162] like Figure 3C As shown, PWell regions 6 and 6a are formed in the current flow region and transition region of the device by P-well photolithography, and then P-well 6 and P-ring 6a are formed by ion implantation.

[0163] Pwell's process conditions need to meet the device threshold voltage requirements. For devices with a threshold voltage requirement of 2-4 volts, B, 30-100 keV, 3-10 E13 / cm can be used. 2 The process conditions must be carefully considered. Simultaneously, it must be ensured that punch-through does not occur at the channel when the device experiences breakdown voltage; otherwise, it will result in high leakage current and a lower breakdown voltage.

[0164] In products subjected to electron irradiation, the threshold voltage (Vth) decreases because electron irradiation traps holes in the device's gate oxide (Gox). Therefore, to achieve a Vth of 3.5-4.5V, the Pwell dose needs to be increased to 1.4E14-2.3E14 / cm². 2 .

[0165] In step two, as Figure 3D As shown, photolithography and ion implantation are performed for P-type ion implantation in the terminal region. Here, the P-type ion implantation, i.e., the second P-type implantation of impurity 61, can be performed using B or BF2. The ion implantation energy is 5-100 keV, and the dose is designed according to the impurity concentration and process of the N-type epitaxy. A further improvement is to use B for ion implantation, 60-120 keV, and a dose of 2E11 / cm. 2 ~8E11 / cm 2 A more preferred option is: B 60keV5E11 / cm 2 .

[0166] Then, through high-temperature annealing, the impurities injected into Pwell, the P-type impurities in the terminal region, namely the second P-type injected impurity 61, are pushed to the required position.

[0167] In step three, such as Figure 3E As shown, a certain thickness of field oxide film, namely protective epoxy film 7, is formed on the surface of the silicon wafer. Then, the oxide film in the current flow region is etched away by photolithography and etching of the protective epoxy film 7. The remaining oxide film covers the transition region and most or all of the terminal region.

[0168] In an improved embodiment, the protective epoxy film 7 is formed using a thermo-oxidative process at temperatures above 800°C. This reduces dangling bonds and unstable interface states at the Si-SiO2 interface, further improving the voltage withstand capability of the termination region and enhancing the consistency of the device's breakdown voltage. The thickness of this oxide film needs to be set according to the device's BVds; generally, the larger the BVds, the thicker the oxide film needs to be. Devices above 600V typically require an oxide film thickness exceeding 8000 angstroms.

[0169] In some embodiments, the method further includes: after the patterning of the protective epoxy film 7 is formed, forming a JFET region in the current flow region of the silicon wafer by ion implantation.

[0170] Because the protective epoxy film 7 protects the transition and termination regions, JFET implantation can be performed without photolithography, saving the cost of photolithography. This is because if a JFET is implanted in the termination region, it will significantly reduce the device's BVds, and if a JFET is implanted in the transition region, it will reduce the device's resistance to current surges.

[0171] In some embodiments, the JFET implantation conditions are phosphorus, 30-100 keV, 1-4 E12 / cm. 2 In other embodiments, it can also be a combination of a 30-60 keV injection and a 1-1.5 MEV injection. The high-energy injection can further reduce the specific on-resistance of the device and improve the device's Bvds by improving the charge balance around the Pwell. Experimental results show that it can improve the voltage by 10-20V for a 600V device.

[0172] In steps four and five, such as Figure 3F As shown, a gate oxide film 8 is formed by thermal oxidation. Then, N-type high-concentration polysilicon 9 is deposited, and a polysilicon electrode, i.e., the polysilicon gate 9, is formed by photolithography and etching of the polysilicon gate 9.

[0173] The gate oxide film is a thermally oxidized film; typically, the gate oxide thickness of a 500-700V MOSFET is [missing information]. The thickness of polycrystalline silicon is

[0174] After photolithography etching of the polysilicon gate 9, the polysilicon gate 9 is formed in the current flow region, and a polysilicon gate bus (gate BUS) surrounding the chip is formed on the outer periphery of the chip. This gate BUS connects to the polysilicon gate 9 in the current flow region. The size of the polysilicon at the connection point can be smaller than that in the current flow region, which allows for a larger contact hole size in the transition region without causing leakage current between the gate and source metals. This gate bus can also cover or partially cover the protective ring dielectric film of the transition region. In the termination region, mutually isolated polysilicon can also be used as a field plate 9a to smooth the termination electric field.

[0175] In step six, after the polycrystalline electrode is formed, the source region 10 is formed in the current flow region by photolithography and ion implantation. At the same time, the cutoff region 10a can be formed in the outermost region of the terminal. The cutoff region 10a can be used to prevent surface inversion in the terminal region, which improves the stability of the device's breakdown characteristics.

[0176] Source region 10 can generally be formed by AS or Phos implantation, or a combination thereof. The implantation conditions for AS and Phos are typically 30-100 keV and 3-5 E15 / cm². 2 .

[0177] In step seven, an interlayer film 11 is then deposited. The interlayer film 11 can be a combination of an undoped oxide film and a BPSG film. The openings of the contact holes are then formed through contact hole photolithography and etching. Figure 3H The diagram shows openings 121a and 121b; after forming the openings of the contact hole, a high concentration of P is injected to form the trap contact region 13, ensuring good ohmic contact between the metal and the Pwell.

[0178] In the etching of the contact hole opening, in the device current flow region, the silicon of the source region 10 of the contact hole area needs to be etched away. Therefore, the etching amount can be between 2000 angstroms and 4000 angstroms, depending on the injection conditions of the source region 10, i.e., the injection energy and dose. In the transition region, the opening of the contact hole only needs to pass through the interlayer film 11 and the protective epoxy film 7. The etching amount of silicon in this region is greater than or equal to 0, or in other words, only the oxide film in the contact hole area needs to be completely removed. Generally, the SI etching amount is set between 0-500 angstroms.

[0179] The thickness of the interlayer membrane 11 is typically 8000-10000 angstroms.

[0180] Since the contact hole connects the source metal and the Pwell region of the protection ring, i.e., the P-ring 6a, in the transition region, it ensures that the device termination structure of the same size can withstand the same voltage as the existing process in the process of this embodiment.

[0181] Since the contact hole in the current flow region penetrates the N+ region, i.e. the source region 10, the full injection of the N+ region outside the polysilicon gate 9 will not cause contact problems between Pwell and the metal, thus ensuring the normal electrical characteristics.

[0182] Here, the high-concentration P-type implantation, i.e., the implanted impurity in the trap contact region 13, can be B, BF2, or a combination thereof, with an energy of 30-80 keV and a dose of 1-3 E15 / cm2. By optimizing these implantation conditions, the device's resistance to current surges can be improved. In order to better improve the softness of the reverse recovery process of the body diode, the energy and dose of the P-type implantation can also be reduced. For example, the energy can be BF2, 5-40 keV, 5E14-2E15 / cm2. The choice of dose can ensure the minimum dose required to form an ohmic contact. The energy selection mainly takes into account the capability of the ion implantation equipment.

[0183] After contact hole etching and ion implantation, a Ti-TiN barrier layer is deposited and annealed. Typical process conditions are rapid annealing at 630-720°C. Then, tungsten (W) is deposited to fill the contact holes (for a 0.6-micron opening, the W thickness can be set to 4000 angstroms). Finally, plasma dry etching is performed to completely remove the surface metal. When all contact hole dimensions are relatively large, such as an aspect ratio less than or equal to 0.5, AlCu or AlSiCu can be used to achieve complete filling; in this case, only Ti-TiN deposition is required, without W deposition and the corresponding etching back.

[0184] In step eight, a front-side metal is deposited on the front side of the silicon wafer. Then, the gate electrode (i.e., the gate electrode) and the source metal of the device are formed through photolithography and etching of the front-side metal. The metal on the front side of the silicon wafer can be AlSi, AlSiCu, and may include a barrier layer, which can be Ti / TIN or TIN. The total thickness of the metal is typically 4-6 micrometers.

[0185] In some improved embodiments, the method may further include: depositing a dielectric film, i.e., a passivation layer, on the front side of the silicon wafer, followed by photolithography and etching to open the gate region and the source region, while protecting the termination region, transition region, etc., with the dielectric film.

[0186] In some improved embodiments, the method may further include: coating the front side of a silicon wafer with polyimide, and then, through photolithography and development, opening the gate region and the source region, while protecting the termination region, transition region, etc., with a polyimide film. The thickness of the polyimide film after baking is typically between 4 micrometers and 10 micrometers.

[0187] The silicon wafer is then thinned on the back side, and a back metal layer 15 is deposited on the back side to form the drain.

[0188] This completes the formation of a superjunction MOSFET device.

[0189] The steps of the above production process are as follows: Figure 4 As shown, Figure 4 The process steps are represented by photolithography layers, which are as follows:

[0190] Step S101, Trench photo & etch, refers to the photolithography and etching of the trench of the P-shaped pillar in step one. Trech means trench, photo means photolithography, and etch means etching.

[0191] Step S102, Pwell photo & IMP, refers to the photolithography and implantation of the P-type well 6, where IMP stands for implantation.

[0192] Step S103, Terminal B IMP photo & IMP, refers to the photolithography and implantation of the second P-type implanted impurity 61 in step two. Terminal represents the terminal region, and B represents boron.

[0193] Step S104, Gfield photo & etch, refers to the photolithography and etching of the protective epoxy film 7 in step three. Gfield is the field oxide layer, which is the protective epoxy layer 7.

[0194] Step S105, JFET blank IMP, indicates full implantation of the JFET region. blank indicates full implantation without a photomask. Step S105 does not increase the number of photolithography steps.

[0195] Step S106, poly photo & etch, refers to the photolithography and etching of the polysilicon gate 9 in step five, where poly represents the polysilicon gate 9.

[0196] Step S107, Nplus blank IMP, indicates that the source region 10 described in step six is ​​fully implanted with N+, and Nplus indicates that the source region 10 is N-type doped.

[0197] Step S108, Cont photo&etch, refers to the photolithography and etching of the contact hole described in step seven. Cont represents the contact hole.

[0198] Step S109, Metal photo & etch, refers to the photolithography and etching of the front metal layer described in step eight. Metal refers to the front metal layer.

[0199] Step S110, Passivation photo & etch, represents the photolithography and etching of the passivation layer, and passivation represents the passivation layer.

[0200] Step S111, Polyimide photo & etch, refers to the photolithography and etching of the polyimide film, where polyimide represents the polyimide film.

[0201] Depend on Figure 4 As shown, a total of 10 photolithography steps were used, among which step S105 does not require photolithography. The superjunction MOSFET device was successfully fabricated. The device's BVds has the following advantages compared to existing devices without terminal P-type injection:

[0202] During device fabrication, an electron irradiation step S112 can be introduced either before or after the polyimide process. By setting appropriate doses and annealing conditions (typically 60-300 KGY, annealing conditions 300-380℃, 30-300 min), minority carrier lifetime control can be achieved, the reverse recovery characteristics of the body diode can be improved, and the application range of the device can be expanded.

[0203] In one embodiment, electron irradiation, i.e., step S112, is performed before the polyimide process, i.e., step S111, and the relationship between the BVdss and p-type impurities of the resulting device is as follows: Figure 5 As shown in Table 1 below:

[0204] Table 1

[0205] P-type impurity concentration BVdss(V) of existing devices The BVdss(V) of the device in this embodiment of the invention P0-0.3E 710 720 P0-0.2E 730 750 P0 760 770 P0+0.2E 740 760 P0+0.3E 700 750 P0+0.4E 680 740 P0+0.5E 650 735 P0+0.6E 700

[0206] Figure 5 In the table, each point 201a on curve 201 corresponds to the BVdss of the device in the embodiment of the present invention in Table 1, and each point 202a on curve 202 corresponds to the BVdss of the existing device in Table 1. The BVdss in Table 1 is the center value measured from 135 points on each wafer. From the experimental data above, we can see that:

[0207] 1. The highest value of BVdss Med of the device in the embodiment of the present invention can be increased by 10V compared with existing devices. In Table 1, P0 represents the doping concentration of the P-type pillar when the N-type pillar and the P-type pillar are in complete PN equilibrium. The highest value of BVdss Med is achieved when the doping concentration of the P-type pillar is P0.

[0208] 2. The variation curves of BVdss and P-type impurity concentration of the device in the embodiment of the present invention are significantly slower than those of existing devices, which significantly improves the process window for P-type impurity concentration. Expanding this process window is the most critical technology for superjunction devices.

[0209] 3. With P0 as the peak and towards the densest concentration, the window of the device in this embodiment of the invention is significantly expanded. In contrast, to achieve good EAS performance, superjunction devices typically have P-type impurities concentrated towards a higher concentration. Based on the experimental results, the product is a 650V superjunction device, and the BVdss Med generally needs to be maintained at 700-710V. Considering the process window, existing devices require P0+0.15E as the production condition, with the process window only between P0 and P0+0.3E. That is, when using P0+0.15E as the production condition, process fluctuations need to be controlled within P0 to P0+0.3E. However, the doping concentration of the P-type pillars in this embodiment of the invention can be produced at P0+0.3E, with a process window from P0 to P0+0.6E, significantly expanding the process window. Furthermore, the operating point concentration of this embodiment of the invention is 0.15E higher than existing devices, resulting in a significant improvement in the device's EAS capability.

[0210] 4. The expanded P-epitaxial layer (epi) concentration window in the device of this embodiment is achieved through the optimization of the P-type injection conditions set in the termination region. This optimization allows for better BVdss and BVdss stability at the top of the N-region and the top of the P-type pillar under the termination design. One explanation for this significant improvement over existing devices is that the optimized termination results in a higher BVdss at the termination than in the active region (i.e., the current-flow region). Therefore, the measured BVdss of the device is determined by the BVdss of the active region. In contrast, in existing technologies, due to the design of the termination region, the BVdss of the termination region is lower than that of the active region, causing the device's BVdss to be determined by the BVdss of the termination region. Furthermore, in existing technologies, the BVdss of the termination is highly sensitive to the P-type pillar concentration, resulting in a small process window.

[0211] 5. Since ion implantation is performed only in the terminal region of the device, it has no effect on the active region of the device, therefore the on-resistance of the device is unaffected.

[0212] 6. Significantly Improved BVds Consistency: The improved breakdown capability of the device terminals makes it easier to design the device so that the breakdown voltage at the terminals is higher than the breakdown voltage in the charge flow region. This greatly improves the consistency of the device's BVds and enhances its resistance to current surges. The reason is that when the terminal breakdown voltage is lower than the breakdown voltage in the charge flow region, device breakdown often occurs near the Si / SiO2 interface. This interface is prone to carrier accumulation, leading to unstable breakdown voltage and poor EAS capability. However, when the terminal breakdown voltage is higher than the charge flow region, the superjunction MOSFET can be designed to ensure that the breakdown in the charge flow region occurs within the Si body, significantly improving the stability of the device's BVdss and easily achieving good EAS capability.

[0213] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A termination structure for a superjunction device, characterized in that: The middle region of the superjunction device is the current flow region, the terminal region surrounds the outer periphery of the current flow region, and the transition region is located between the current flow region and the terminal region. A superjunction structure is formed in the current flow region, the transition region, and the termination region; the superjunction structure is formed in a semiconductor substrate and includes alternating N-type pillars and P-type pillars, each P-type pillar having a first initial P-type impurity, each N-type pillar having a first initial N-type impurity, and the superjunction unit includes one N-type pillar and an adjacent P-type pillar. A terminal structure is formed in the transition region and the terminal region, and the terminal structure includes: the superjunction structure, a protective epoxide film, and a second P-type implanted impurity; The protective epoxy film covers the surface of the superjunction structure in the transition region and the terminal region; Each of the P-type columns has a first surface region, and some of the P-type impurities in the first surface region will thermally segregate into the protective epoxide film, thereby reducing the amount of P-type impurities in the first surface region of each of the P-type columns; The second P-type implanted impurity is located in the second surface region of the superjunction structure in the terminal region, and there is no second P-type implanted impurity in the current flow region; in the P-type pillar in the terminal region, the second surface region and the first surface region have an overlapping region; The second P-type implanted impurity is used to compensate for the reduction in P-type impurities in the first surface region, thereby improving the PN balance of the superjunction structure in the terminal region. The second P-type implanted impurity also reduces the net N-type doping in the second surface region of the N-type pillar in the terminal region, thereby improving the breakdown voltage of the superjunction structure in the terminal region and increasing the process window of the P-type pillar.

2. The termination structure of the superjunction device as described in claim 1, characterized in that: The protective epoxide film comprises a thermal oxide film.

3. The termination structure of the superjunction device as described in claim 1, characterized in that: The first initial P-type impurity includes boron or boron fluoride.

4. The termination structure of the superjunction device as described in claim 1, characterized in that: In the current flow region, a P-type well is also formed on the surface of each P-type pillar, and the P-type well extends to the surface of the adjacent N-type pillar. A P-type ring is formed in the transition region, and the P-type ring covers the surface of each of the superjunction units in the transition region; The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than that of the P-type pillar, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than that of the P-type pillar.

5. The termination structure of the superjunction device as described in claim 1, characterized in that: The second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions for the second P-type implanted impurity include 2E11cm. -2 ~8E11cm -2 .

6. The termination structure of the superjunction device as described in claim 1, characterized in that: By adjusting the second P-type implanted impurity, the withstand voltage of the superjunction structure in the terminal region is adjusted to be greater than that of the superjunction structure in the current flow region, so that the withstand voltage of the superjunction device is determined by the withstand voltage of the superjunction structure in the current flow region.

7. The termination structure of the superjunction device as described in claim 1, characterized in that: The process window of the P-type pillar is the window for the variation of the doping concentration of the first initial P-type impurity in the P-type pillar. The minimum doping concentration of the P-type pillar is taken as the optimal equilibrium doping concentration. The maximum doping concentration of the P-type pillar ensures that the breakdown voltage of the superjunction device meets the minimum breakdown voltage requirement. The improved breakdown voltage of the superjunction structure in the terminal region enhances the breakdown voltage of the superjunction device, and the maximum doping concentration of the P-type pillar also increases, thus expanding the process window of the P-type pillar.

8. The termination structure of the superjunction device as described in claim 7, characterized in that: A first epitaxial layer is formed on the surface of the semiconductor substrate, and the superjunction structure is formed in the first epitaxial layer; The first epitaxial layer is a single epitaxial layer with a single resistivity; Alternatively, the first epitaxial layer may be composed of a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, wherein the resistivity of the second epitaxial sublayer is lower than that of the first epitaxial sublayer.

9. The termination structure of the superjunction device as described in claim 8, characterized in that: The first epitaxial layer is N-type doped, and the P-type pillars are composed of a second P-type doped epitaxial layer filled in the trenches. The N-type pillars are composed of the first epitaxial layer between the P-type pillars. The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type pillar.

10. A method for manufacturing a termination structure of a superjunction device, characterized in that, Includes the following steps: Step 1: Divide the formation region of the superjunction device into a current flow region, a transition region, and a termination region. The middle region of the superjunction device is the current flow region, the termination region surrounds the outer periphery of the current flow region, and the transition region is located between the current flow region and the termination region. A superjunction structure is formed in the current flow region, the transition region, and the termination region. The superjunction structure is formed in a semiconductor substrate and includes alternating N-type pillars and P-type pillars. Each P-type pillar has a first initial P-type impurity, and each N-type pillar has a first initial N-type impurity. Each superjunction unit includes one N-type pillar and an adjacent P-type pillar. Step 2: Perform selective P-type ion implantation to form a second P-type implanted impurity in the second surface region of the superjunction structure in the terminal region; There are no second P-type injected impurities in the current flow region; Step 3: Form a protective epoxy film and perform patterned etching on the protective epoxy film, wherein the patterned etching causes the protective epoxy film to exist only on the surface of the superjunction structure in the transition region and the terminal region; During the formation of the protective epoxide film, some P-type impurities in the first surface region of each P-type column will thermally segregate into the protective epoxide film, thereby reducing the amount of P-type impurities. In the P-type pillar in the terminal region, the second surface region and the first surface region have an overlapping area. The second P-type implanted impurity is used to compensate for the reduction of P-type impurities in the first surface region, thereby improving the PN balance of the superjunction structure in the terminal region. The second P-type implanted impurity also reduces the net N-type doping amount in the second surface region of the N-type pillar in the terminal region, thereby improving the breakdown voltage of the superjunction structure in the terminal region and improving the process window of the P-type pillar.

11. The method for manufacturing the termination structure of the superjunction device as described in claim 10, characterized in that: In step three, the protective epoxide film comprises a thermally oxidized film formed using a thermal oxidation process.

12. The method for manufacturing the termination structure of the superjunction device as described in claim 10, characterized in that: The first initial P-type impurity includes boron or boron fluoride.

13. The method for manufacturing the termination structure of the superjunction device as described in claim 10, characterized in that: Before step three, the following is also included: A P-type well is formed in the current flow region, the P-type well being located on the surface of each of the P-type pillars and extending to the surface of the adjacent N-type pillars; A P-type ring is formed in the transition region, and the P-type ring covers the surface of each of the superjunction units in the transition region; The doping concentration of the P-type well is 1 to 2 orders of magnitude higher than that of the P-type pillar, and the doping concentration of the P-type ring is 1 to 2 orders of magnitude higher than that of the P-type pillar.

14. The method for manufacturing the termination structure of the superjunction device as described in claim 10, characterized in that: The second P-type implanted impurity includes boron or boron fluoride, and the implantation conditions for the second P-type implanted impurity include 2E11cm. -2 ~8E11cm -2 .

15. The method for manufacturing the termination structure of the superjunction device as described in claim 10, characterized in that: By adjusting the second P-type implanted impurity, the withstand voltage of the superjunction structure in the terminal region is adjusted to be greater than that of the superjunction structure in the current flow region, so that the withstand voltage of the superjunction device is determined by the withstand voltage of the superjunction structure in the current flow region.

16. The method for manufacturing the termination structure of the superjunction device as described in claim 10, characterized in that: The process window of the P-type pillar is the window for the variation of the doping concentration of the first initial P-type impurity in the P-type pillar. The minimum doping concentration of the P-type pillar is taken as the optimal equilibrium doping concentration. The maximum doping concentration of the P-type pillar ensures that the breakdown voltage of the superjunction device meets the minimum breakdown voltage requirement. The improved breakdown voltage of the superjunction structure in the terminal region enhances the breakdown voltage of the superjunction device, and the maximum doping concentration of the P-type pillar also increases, thus expanding the process window of the P-type pillar.

17. The method for manufacturing the termination structure of the superjunction device as described in claim 16, characterized in that: A first epitaxial layer is formed on the surface of the semiconductor substrate, and the superjunction structure is formed in the first epitaxial layer; The first epitaxial layer is a single epitaxial layer with a single resistivity; Alternatively, the first epitaxial layer may be composed of a first epitaxial sublayer and a second epitaxial sublayer located on the top surface of the first epitaxial sublayer, wherein the resistivity of the second epitaxial sublayer is lower than that of the first epitaxial sublayer.

18. The method for manufacturing the termination structure of the superjunction device as described in claim 17, characterized in that: The first epitaxial layer is N-type doped, and step one includes the following sub-steps: Multiple trenches are formed in the first epitaxial layer; A second epitaxial layer doped with P-type is filled in the trench, and the second epitaxial layer doped with P-type is filled in the trench as a component of the P-type pillar. The N-type pillar is composed of the first epitaxial layer between the P-type pillars. The fluctuation range of the P-type doping concentration of the second epitaxial layer is within the process window of the P-type pillar.

Images