NPT-IGBT device and manufacturing method thereof

Abstract

The NPT-IGBT device comprises a drift region, a well region formed on the surface of the drift region, a gate structure, and an emitter region which is formed on the surface of the well region and is self-aligned with the gate structure. And the second semiconductor material layer is formed on the back surface of the semiconductor substrate, and the forbidden bandwidth of the second semiconductor material layer is smaller than that of the semiconductor substrate. The top surface of the collector region is flush with the top surface of the second semiconductor material layer or located below the top surface of the second semiconductor material layer, and the top surface of the collector region is in contact with the bottom surface of the drift region to form a back PN junction. The invention further discloses a manufacturing method of the NPT-IGBT device. According to the invention, the material of the collector region is improved, so that the turn-on voltage of a back PN junction and the conduction voltage drop and the conduction loss of the whole device can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power devices, and in particular to a non-punchthrough (NPT) insulated gate bipolar transistor (IGBT) device; the present invention also relates to an NPT-IGBT device and a manufacturing method thereof. Background Art

[0002] IGBT devices are voltage-driven devices composed of metal oxide semiconductor field effect transistors (MOSFET) and bipolar junction transistors (BJT). MOSFET has high input impedance and fast switching speed, but low carrier density and high on-resistance; BJT has high current density and low on-voltage drop, but large driving current; IGBT combines the advantages of both, with low driving loss and fast switching speed, as well as the advantage of low on-voltage drop, so it is widely used in medium and high voltage fields such as home appliances, photovoltaics, industrial control, new energy vehicles, and rail transportation.

[0003] The collector side of the NPT-IGBT device has a PN junction diode structure. When the device is turned on, the channel on the front of the device is opened, and electrons are injected from the emitter region into the drift region; at the same time, the PN junction on the collector side is opened, and a large number of holes are injected from the collector region into the drift region, so a large number of carriers are accumulated in the drift region, forming a conductivity modulation effect. This greatly reduces the on-resistance of the IGBT, and thus reduces its conduction loss.

[0004] In the prior art, in Si-based devices, NPT-IGBT devices are formed on a silicon substrate. Since the bandgap width of Si is about 1.12eV, the turn-on voltage of the silicon-based PN junction diode is 0.7V, which is almost half of the on-state voltage drop of the existing IGBT. This means that 50% of the IGBT conduction loss is caused by the PN junction diode on the collector side. Therefore, if the structure of the collector area can be further improved to reduce the turn-on voltage of the PN junction diode on the collector side, the conduction loss of the device will be greatly reduced.

[0005] like Figure 1 As shown, it is a schematic diagram of the structure of an existing NPT-IGBT device; the existing NPT-IGBT device usually adopts an N-type device. Taking the N-type device as an example, the existing NPT-IGBT device includes:

[0006] The drift region 103 is composed of an N-type lightly doped region formed on the surface of the silicon substrate.

[0007] A P-type doped well region 105 is formed on the surface of the drift region 103 .

[0008] The gate structure includes a gate oxide layer 104 and a polysilicon gate 106 stacked in sequence. Figure 1 In the embodiment, the gate structure is a trench gate, the gate oxide layer 104 is formed on the inner surface of the gate trench, the polysilicon gate 106 is filled in the gate trench, the gate trench vertically passes through the well region 105, and the surface of the well region 105 covered by the side of the gate structure is used as the channel region. The gate structure can also adopt a planar gate.

[0009] An N-type heavily doped emitter region 107 is formed on the surface of the well region 105 and is self-aligned with the gate structure.

[0010] A P-type heavily doped collector region 101 is formed on the back side of the drift region 103 .

[0011] The top surface of the collector region 101 and the bottom surface of the drift region 103 are in contact with each other and form a back PN junction.

[0012] The turn-on voltage of the back PN junction is mainly determined by the bandgap width of the silicon material. The bandgap width of silicon is about 1.12 eV. The turn-on voltage of the back PN junction is about 0.7V.

[0013] The front metal layer 109 is patterned to form a gate and an emitter. Figure 1 Only the emitter is shown, and the gate composed of the front metal layer 109 is not shown. Figure 1 The gate is connected to the polysilicon gate 106 at the bottom, and the emitter is connected to the emitter region 107 at the bottom. A well contact region 108 is also formed on the surface of the well region 105. The well contact region 108 is heavily doped with the second conductivity type, and the emitter is also connected to the well contact region 108.

[0014] A collector electrode composed of a back metal layer 102 is formed on the back side of the collector region 101 . Summary of the invention

[0015] The technical problem to be solved by the present invention is to provide an NPT-IGBT device, which can improve the material of the collector region, thereby reducing the turn-on voltage of the back PN junction, and further reducing the conduction voltage drop and conduction loss of the entire device. To this end, the present invention also provides a method for manufacturing the NPT-IGBT device.

[0016] In order to solve the above technical problems, the NPT-IGBT device provided by the present invention comprises:

[0017] The drift region is composed of a first conductivity type lightly doped region formed on the surface of the semiconductor substrate.

[0018] A well region doped with the second conductivity type is formed on the surface of the drift region.

[0019] The gate structure comprises a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0020] An emitter region heavily doped with the first conductivity type is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region between the emitter region and the drift region serves as a channel region and is covered by the gate structure.

[0021] A second semiconductor material layer is formed on the back side of the semiconductor substrate, wherein the bandgap width of the second semiconductor material layer is lower than the bandgap width of the semiconductor substrate.

[0022] A collector region of the second conductive type that is heavily doped, the top surface of the collector region is flush with or below the top surface of the second semiconductor material layer, the bottom surface of the drift region also extends to the top surface of the collector region, the top surface of the collector region and the bottom surface of the drift region are in contact with each other to form a back PN junction; the interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer, so that the turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower bandgap width of the second semiconductor material layer is used to reduce the turn-on voltage of the back PN junction.

[0023] A further improvement is that the material of the semiconductor substrate includes Si.

[0024] A further improvement is that the material of the second semiconductor material layer includes Ge and GeSi.

[0025] A further improvement is that the second semiconductor material layer is a deposition layer formed on the back side of the semiconductor substrate.

[0026] Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the second semiconductor material layer is a GeSi layer formed by backside Ge implantation into Si.

[0027] A further improvement is that the second semiconductor material layer has been subjected to annealing treatment, and the collector region has been subjected to back-side laser annealing treatment.

[0028] The annealing of the second semiconductor material layer is performed by furnace annealing or back laser annealing.

[0029] A further improvement is that the doping impurities in the collector region are back-implanted impurities heavily doped with the second conductivity type or in-situ doping impurities in the second semiconductor material layer.

[0030] A bottom surface of the collector region is flush with a bottom surface of the second semiconductor material layer.

[0031] The junction depth of the collector region is 1 μm to 5 μm.

[0032] The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 1 μm to 7 μm.

[0033] A further improvement is that the gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region.

[0034] Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

[0035] In order to solve the above technical problems, the present invention provides a method for manufacturing an NPT-IGBT device, comprising the following steps:

[0036] Step 1: Complete the front process to form the front process structure of the NPT-IGBT device.

[0037] The front process structure of the NPT-IGBT device includes:

[0038] The drift region is composed of a first conductivity type lightly doped region formed on the surface of the semiconductor substrate.

[0039] A well region doped with the second conductivity type is formed on the surface of the drift region.

[0040] The gate structure comprises a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0041] An emitter region heavily doped with the first conductivity type is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region between the emitter region and the drift region serves as a channel region and is covered by the gate structure.

[0042] Step 2: thinning the back side of the semiconductor substrate.

[0043] Step three: forming a second semiconductor material layer on the back side of the thinned semiconductor substrate; the bandgap width of the second semiconductor material layer is lower than the bandgap width of the semiconductor substrate.

[0044] Step 4: Form a collector region heavily doped with the second conductivity type, wherein the top surface of the collector region is flush with or below the top surface of the second semiconductor material layer, and the bottom surface of the drift region also extends to the top surface of the collector region, and the top surface of the collector region and the bottom surface of the drift region are in contact with each other to form a back PN junction.

[0045] The interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer. The turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower bandgap width of the second semiconductor material layer is used to reduce the turn-on voltage of the back PN junction.

[0046] A further improvement is that the material of the semiconductor substrate includes Si.

[0047] A further improvement is that the material of the second semiconductor material layer includes Ge and GeSi.

[0048] A further improvement is that in step three, a deposition process is used to form the second semiconductor material layer on the back side of the thinned semiconductor substrate.

[0049] Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the process of forming the second semiconductor material layer in step three includes: performing back-side Ge injection, the Ge injected from the back-side Ge and the Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer.

[0050] A further improvement is that the second semiconductor material layer has been subjected to annealing treatment, and the collector region has been subjected to back-side laser annealing treatment.

[0051] The annealing of the second semiconductor material layer is performed by furnace annealing or back laser annealing.

[0052] A further improvement is that, when the annealing of the second semiconductor material layer includes the furnace tube annealing, the furnace tube annealing of the second semiconductor material layer is performed after step three and before step four.

[0053] The backside laser annealing is performed after step 4 is completed.

[0054] A further improvement is that in step five, the collector region is formed by back ion implantation with heavy doping of the second conductivity type.

[0055] Alternatively, when a deposition process is used to form the second semiconductor material layer in step three, step five is omitted, and in step three, the second semiconductor material layer is doped in situ, and the in-situ doped impurities of the second semiconductor material layer are used as doping impurities for the collector region.

[0056] A bottom surface of the collector region is flush with a bottom surface of the second semiconductor material layer.

[0057] The junction depth of the collector region is 1 μm to 5 μm.

[0058] The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 1 μm to 7 μm.

[0059] A further improvement is that the gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region.

[0060] Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

[0061] A further improvement is that the NPT-IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the NPT-IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0062] Unlike the prior art, in which the collector region of the NPT-IGBT device is directly formed by injection on the back side of the thinned semiconductor substrate, the present invention adds a second semiconductor material layer with a lower bandgap width on the back side of the semiconductor substrate after the back side of the semiconductor substrate is thinned, forms a collector region on the basis of the second semiconductor material layer, and lowers the top surface of the collector region to be set below the top surface of the second semiconductor material layer, so that the interface of the back PN junction formed between the collector region and the drift region on the top of the collector region is located inside the second semiconductor material layer, and part or all of the built-in space charge region is located inside the second semiconductor material layer. Therefore, the turn-on voltage of the back PN junction of the present invention will be determined by the second semiconductor material layer, while the turn-on voltage of the back PN junction in the existing NPT-IGBT device is determined by the material of the semiconductor substrate; since the lower the bandgap width of the material constituting the PN junction, the lower the turn-on voltage of the PN junction, the present invention can reduce the bandgap width of the constituent materials of the back PN junction, thereby reducing the turn-on voltage of the back PN junction, that is, the present invention uses the lower bandgap width of the second semiconductor material layer to reduce the turn-on voltage of the back PN junction. In summary, the present invention can improve the material of the collector region so that the collector region is located inside the second semiconductor material layer with a bandgap width lower than that of the semiconductor substrate, thereby reducing the turn-on voltage of the back PN junction and further reducing the conduction voltage drop and conduction loss of the entire device. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0064] Figure 1 It is a schematic diagram of the structure of an existing NPT-IGBT device;

[0065] Figure 2 is a schematic structural diagram of an NPT-IGBT device according to a first embodiment of the present invention;

[0066] Figure 3 is a schematic structural diagram of an NPT-IGBT device according to a third embodiment of the present invention;

[0067] Figure 4 is a flow chart of a method for manufacturing an NPT-IGBT device according to a first embodiment of the present invention;

[0068] Figure 5 FIG. 4 is a flow chart of a method for manufacturing an NPT-IGBT device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0069] The first embodiment of the present invention is an NPT-IGBT device:

[0070] like Figure 2FIG. 1 is a schematic diagram of the structure of an NPT-IGBT device according to a first embodiment of the present invention. The NPT-IGBT device according to a first embodiment of the present invention comprises:

[0071] The drift region 203 is composed of a first conductivity type lightly doped region formed on the surface of the semiconductor substrate.

[0072] A well region 205 doped with the second conductivity type is formed on the surface of the drift region 203 .

[0073] The gate structure includes a gate dielectric layer 204 and a gate conductive material layer 206 stacked in sequence.

[0074] An emitter region 207 heavily doped with the first conductivity type is formed on the surface of the well region 205 and is self-aligned with the gate structure; the surface of the well region 205 between the emitter region 207 and the drift region 203 serves as a channel region and is covered by the gate structure.

[0075] In the first embodiment of the present invention, the gate structure is a trench gate, the gate dielectric layer 204 is formed on the inner surface of the gate trench, the gate conductive material layer 206 is filled in the gate trench, the gate trench vertically passes through the well region 205, and the surface of the well region 205 covered by the side of the gate structure is used as the channel region. In some embodiments, the gate dielectric layer 204 is a gate oxide layer, and the gate conductive material 206 is a polysilicon gate.

[0076] A second semiconductor material layer 301 is formed on the back side of the semiconductor substrate, and the bandgap width of the second semiconductor material layer 301 is lower than the bandgap width of the semiconductor substrate. Figure 2 In the figure, the back side of the semiconductor substrate is separately marked with a mark 303, and the surface 303 is also the top surface of the second semiconductor material layer 301.

[0077] A collector region 201 that is heavily doped with the second conductivity type, the top surface of the collector region 201 is flush with the top surface of the second semiconductor material layer 301 or is located below the top surface of the second semiconductor material layer 301, the bottom surface of the drift region 203 also extends to the top surface of the collector region 201, the top surface of the collector region 201 and the bottom surface of the drift region 203 are in contact with each other to form a back PN junction. Figure 2 In the figure, the collector region 201 is located in the region indicated by the curly brackets corresponding to the mark 201 .

[0078] The interface of the back PN junction is located inside the second semiconductor material layer 301 or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer 301. The turn-on voltage of the back PN junction is determined by the second semiconductor material layer 301 and the lower bandgap width of the second semiconductor material layer 301 is used to reduce the turn-on voltage of the back PN junction. Figure 2 In the figure, the interface of the back PN junction is marked with a mark 302 , and it can be seen that the interface 302 is located below the surface 303 .

[0079] In the first embodiment of the present invention, the material of the semiconductor substrate includes Si.

[0080] In some embodiments, an epitaxial layer is further formed on the surface of the semiconductor substrate, and the drift region 203 is formed in the epitaxial layer; the semiconductor substrate is completely removed after the back side is thinned.

[0081] The material of the second semiconductor material layer 301 includes Ge. Since the bandgap width of Si is about 1.12eV and the bandgap width of Ge is about 0.67eV, after the space charge region of the back PN junction is located inside Ge, the turn-on voltage will be reduced to about 0.3V, which is lower than the turn-on voltage of about 0.7V of the PN junction in the Si material. In other embodiments, the material of the second semiconductor material layer 301 can also be GeSi or other semiconductor materials with a bandgap width lower than the bandgap width of Si.

[0082] The second semiconductor material layer 301 is a deposition layer formed on the back of the semiconductor substrate. In some embodiments, the deposition process of the second semiconductor material layer 301 includes: molecular beam epitaxy, organic chemical vapor deposition, pulsed laser deposition, magnetron sputtering, plasma enhanced chemical vapor deposition, low temperature germanium buffer layer deposition, etc.

[0083] In the first embodiment of the present invention, the second semiconductor material layer 301 has been subjected to annealing treatment, and the collector region 201 has been subjected to back laser annealing treatment. The second semiconductor material layer 301 can repair Ge crystallization after annealing treatment; the collector region 201 can achieve impurity activation after the back laser annealing treatment.

[0084] In some embodiments, the annealing of the second semiconductor material layer 301 adopts furnace tube annealing or the back laser annealing. The process conditions of the furnace tube annealing include: annealing temperature of 400℃~500℃, annealing time of 40min. In other embodiments, it can also be: the annealing of the second semiconductor material layer 301 only adopts the back laser annealing, and does not need to adopt furnace tube annealing, so that the crystallization repair of the second semiconductor material layer 301 and the impurity activation of the collector region 201 are achieved by the same back laser annealing.

[0085] In some embodiments, the doping impurities of the collector region 201 are back-implanted impurities heavily doped with the second conductivity type. In other embodiments, the doping impurities of the collector region 201 can also be in-situ doping impurities of the second semiconductor material layer 301 .

[0086] The bottom surface of the collector region 201 is flush with the bottom surface of the second semiconductor material layer 301 .

[0087] The first embodiment of the present invention further includes: a front metal layer 209, wherein the front metal layer 209 is patterned to form a gate and an emitter. Figure 2 Only the emitter is shown, and the gate composed of the front metal layer 209 is not shown. Figure 2 The gate is connected to the gate conductive material layer 206 at the bottom, and the emitter is connected to the emitter region 207 at the bottom. A well contact region 208 is also formed on the surface of the well region 205. The well contact region 208 is heavily doped with the second conductivity type, and the emitter is also connected to the well contact region 208. In some embodiments, the front metal layer 209 includes multiple layers, and each layer of the front metal layer 209 is isolated by an interlayer film and connected by a through hole passing through the interlayer film.

[0088] A collector electrode composed of a back metal layer 202 is formed on the back side of the collector region 201 .

[0089] In some embodiments, the junction depth of the collector region 201 is about 1 um to 5 μm. The thickness of the second semiconductor material layer 301 is greater than the junction depth of the collector region 201 and the thickness of the second semiconductor material layer 301 is 1 μm to 7 μm.

[0090] In the first embodiment of the present invention, the NPT-IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. The NPT-IGBT device is an N-type device, which means that the carriers of the conductive channel formed by the surface inversion of the channel region controlled by the gate structure are electrons. The doping impurities of the collector region 201 include boron, and the doping concentration is 1E18cm -3 ~1E19cm-3 between.

[0091] In other embodiments, the NPT-IGBT device may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0092] Different from the prior art, in which the collector region 201 of the NPT-IGBT device is directly formed by injection on the back side of the thinned semiconductor substrate, in the first embodiment of the present invention, after the back side of the semiconductor substrate is thinned, a second semiconductor material layer 301 with a lower bandgap width is added on the back side of the semiconductor substrate, the collector region 201 is formed on the basis of the second semiconductor material layer 301, and the top surface of the collector region 201 is lowered to be set below the top surface of the second semiconductor material layer 301, so that the interface of the back PN junction formed between the collector region 201 and the drift region on the top of the collector region 201 is located inside the second semiconductor material layer 301 and the built-in space electric Part or all of the collector region is located inside the second semiconductor material layer 301, so the turn-on voltage of the back PN junction of the first embodiment of the present invention will be determined by the second semiconductor material layer 301, while the turn-on voltage of the back PN junction in the existing NPT-IGBT device is determined by the material of the semiconductor substrate; since the lower the bandgap width of the material constituting the PN junction, the lower the turn-on voltage of the PN junction, the first embodiment of the present invention can achieve a reduction in the bandgap width of the constituent materials of the back PN junction, thereby reducing the turn-on voltage of the back PN junction, that is, the first embodiment of the present invention uses the lower bandgap width of the second semiconductor material layer 301 to reduce the turn-on voltage of the back PN junction. In short, the first embodiment of the present invention can improve the material of the collector region 201, so that the collector region 201 is located inside the second semiconductor material layer 301 with a lower bandgap width than the semiconductor substrate, thereby reducing the turn-on voltage of the back PN junction, and further reducing the conduction voltage drop and conduction loss of the entire device.

[0093] The NPT-IGBT device of the second embodiment of the present invention:

[0094] The difference between the NPT-IGBT device of the second embodiment of the present invention and the NPT-IGBT device of the first embodiment of the present invention is as follows:

[0095] In the NPT-IGBT device of the second embodiment of the present invention, the material of the semiconductor substrate is Si and the material of the second semiconductor material layer 301 is GeSi, and the second semiconductor material layer 301 is a GeSi layer formed by backside Ge implantation into Si. The GeSi layer formed by backside Ge implantation combined with annealing can make the GeSi layer crystallize well.

[0096] The third embodiment of the present invention is an NPT-IGBT device:

[0097] The difference between the NPT-IGBT device of the third embodiment of the present invention and the NPT-IGBT device of the first embodiment of the present invention is as follows:

[0098] In the NPT-IGBT device of the third embodiment of the present invention, Figure 3 As shown, the gate structure is a planar gate, the gate dielectric layer 204a covers the top surface of the well region 205 and extends to the top surface of the drift region 203 adjacent to the well region 205, the gate conductive material layer 206a is superimposed on the top surface of the gate dielectric layer 204, and the surface of the well region 205 covered by the gate structure from the top side of the well region 205 serves as the channel region. Figure 3 In the figure, the gate dielectric layer is represented by a mark 204a alone, the gate conductive material layer is represented by a mark 206a alone, and the surfaces of other structures are not changed.

[0099] The manufacturing method of the NPT-IGBT device according to the first embodiment of the present invention:

[0100] like Figure 4 FIG. 1 is a method for manufacturing an NPT-IGBT device according to a first embodiment of the present invention. The method for manufacturing an NPT-IGBT device according to the first embodiment of the present invention can manufacture Figure 2 The first embodiment of the present invention is a NPT-IGBT device and Figure 3 The NPT-IGBT device of the third embodiment of the present invention shown in FIG. 1 can also obtain the NPT-IGBT device of the second embodiment of the present invention. Figure 2 Taking the structure shown in FIG. 1 as an example, the manufacturing method of the NPT-IGBT device of the first embodiment of the present invention includes the following steps:

[0101] Step 1: Complete the front process to form the front process structure of the NPT-IGBT device. Step 1 corresponds to Figure 4 Step S101, the front process is completed.

[0102] The front process structure of the NPT-IGBT device includes:

[0103] The drift region 203 is composed of a first conductivity type lightly doped region formed on the surface of the semiconductor substrate.

[0104] A well region 205 doped with the second conductivity type is formed on the surface of the drift region 203 .

[0105] The gate structure includes a gate dielectric layer 204 and a gate conductive material layer 206 stacked in sequence.

[0106] An emitter region 207 heavily doped with the first conductivity type is formed on the surface of the well region 205 and is self-aligned with the gate structure; the surface of the well region 205 between the emitter region 207 and the drift region 203 serves as a channel region and is covered by the gate structure.

[0107] In the method of the first embodiment of the present invention, the material of the semiconductor substrate includes Si.

[0108] In some embodiments, an epitaxial layer is formed on the surface of the semiconductor substrate, and the drift region 203 is formed in the epitaxial layer. The semiconductor substrate will be completely removed in a subsequent backside thinning process.

[0109] The gate structure is a trench gate, the gate dielectric layer 204 is formed on the inner surface of the gate trench, the gate conductive material layer 206 is filled in the gate trench, the gate trench vertically passes through the well region 205, and the surface of the well region 205 covered by the side of the gate structure serves as the channel region.

[0110] When used to manufacture Figure 3 In the NPT-IGBT device of the third embodiment of the present invention shown, the gate structure is a planar gate, the gate dielectric layer 204 covers the top surface of the well region 205 and extends to the top surface of the drift region 203 adjacent to the well region 205, the gate conductive material layer 206 is superimposed on the top surface of the gate dielectric layer 204, and the surface of the well region 205 covered by the gate structure from the top side of the well region 205 serves as the channel region.

[0111] In the method of the first embodiment of the present invention, the front process structure of the NPT-IGBT device further includes: a front metal layer 209, and the front metal layer 209 is patterned to form a gate and an emitter. Figure 2 Only the emitter is shown, and the gate composed of the front metal layer 209 is not shown. Figure 2 The gate is connected to the gate conductive material layer 206 at the bottom, and the emitter is connected to the emitter region 207 at the bottom. A well contact region 208 is also formed on the surface of the well region 205. The well contact region 208 is heavily doped with the second conductivity type, and the emitter is also connected to the well contact region 208. In some embodiments, the front metal layer 209 includes multiple layers, and each layer of the front metal layer 209 is isolated by an interlayer film and connected by a through hole passing through the interlayer film.

[0112] Step 2: thinning the back side of the semiconductor substrate. Step 2 corresponds to Figure 4 Step S102, back side thinning.

[0113] Step three: forming a second semiconductor material layer 301 on the back side of the thinned semiconductor substrate; the bandgap width of the second semiconductor material layer 301 is lower than the bandgap width of the semiconductor substrate.

[0114] In the method of the first embodiment of the present invention, the material of the second semiconductor material layer 301 is Ge, and the Ge layer is formed by a deposition process. Step three corresponds to Figure 4 In step S103, Ge layer deposition.

[0115] In other embodiments, the material of the second semiconductor material layer 301 can also be GeSi or other semiconductor materials with a bandgap width lower than the bandgap width of Si.

[0116] In some embodiment methods, the deposition process of the second semiconductor material layer 301 includes: molecular beam epitaxy, organic chemical vapor deposition, pulsed laser deposition, magnetron sputtering, plasma enhanced chemical vapor deposition, low temperature germanium buffer layer deposition, etc.

[0117] In other embodiments, the semiconductor substrate is made of Si and the second semiconductor material layer 301 is made of GeSi, and the process of forming the second semiconductor material layer 301 includes: performing backside Ge injection, wherein the Ge injected from the backside Ge and the Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer 301. The device formed at this time corresponds to the NPT-IGBT device of the second embodiment of the present invention.

[0118] In the method of the first embodiment of the present invention, after step three is completed, the method further includes:

[0119] The second semiconductor material layer 301 is subjected to furnace annealing to repair the crystallization of the Ge layer. This step corresponds to Figure 4 The process conditions of the furnace tube annealing include: annealing temperature of 400° C. to 500° C., and annealing time of 40 minutes.

[0120] Step 4: Form a collector region 201 heavily doped with the second conductivity type, wherein the top surface of the collector region 201 is flush with the top surface of the second semiconductor material layer 301 or is located below the top surface of the second semiconductor material layer 301, and the bottom surface of the drift region 203 also extends to the top surface of the collector region 201, and the top surface of the collector region 201 and the bottom surface of the drift region 203 are in contact with each other to form a back PN junction.

[0121] In the method of the first embodiment of the present invention, the collector region 201 is formed by back ion implantation with heavy doping of the second conductivity type.

[0122] In the method of the first embodiment of the present invention, the NPT-IGBT device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the second conductivity type is P-type; therefore, the second conductivity type is heavily doped with P-type; step four corresponds to Figure 4 Step S105, back Pplus injection, Pplus represents P-type heavy doping injection, i.e., second conductivity type heavy doping injection, the injected impurities include boron, the doping concentration of the collector region 201 is 1E18cm -3 ~1E19cm -3 In other embodiments, the NPT-IGBT device may be a P-type device, the first conductivity type is P-type, the second conductivity type is N-type, and the collector region 201 may be implanted by back-side Nplus implantation.

[0123] In other embodiments, the method can also be as follows: when the second semiconductor material layer 301 is formed by a deposition process in step 3, step 4 is omitted. In step 3, the second semiconductor material layer 301 is doped in situ, and the in-situ doped impurities of the second semiconductor material layer 301 are used as doping impurities of the collector region 201. Figure 4 There is a description in the brackets of step S105, which is: if the Ge layer is in-situ doped, skip this process.

[0124] In the method of the first embodiment of the present invention, the bottom surface of the collector region 201 is flush with the bottom surface of the second semiconductor material layer 301;

[0125] In some embodiments, the junction depth of the collector region 201 is about 1 um to 5 μm.

[0126] The thickness of the second semiconductor material layer 301 is greater than the junction depth of the collector region 201 and the thickness of the second semiconductor material layer 301 is 1 μm to 7 μm.

[0127] After step 4, it also includes:

[0128] Perform back laser annealing to activate the impurities in the collector region 201. This step corresponds to Figure 4 Step S106, laser annealing.

[0129] The interface of the back PN junction is located inside the second semiconductor material layer 301 or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer 301. The turn-on voltage of the back PN junction is determined by the second semiconductor material layer 301 and the lower bandgap width of the second semiconductor material layer 301 is used to reduce the turn-on voltage of the back PN junction.

[0130] The follow-up also includes:

[0131] A collector electrode composed of a back metal layer 202 is formed on the back of the collector region 201. The back metal layer 202 is usually formed by a metal sputtering process. Figure 4 Step S107, metal sputtering.

[0132] The manufacturing method of the NPT-IGBT device according to the second embodiment of the present invention:

[0133] like Figure 5 FIG. 1 is a method for manufacturing an NPT-IGBT device according to a second embodiment of the present invention. The difference between the method for manufacturing an NPT-IGBT device according to the second embodiment of the present invention and the method for manufacturing an NPT-IGBT device according to the first embodiment of the present invention is as follows:

[0134] In the method for manufacturing an NPT-IGBT device according to the second embodiment of the present invention, the annealing performed on the second semiconductor material layer 301 does not include the furnace annealing. Figure 5 Omitted Figure 4 In this way, the annealing for crystallization repair of the second semiconductor material layer 301 directly adopts the back laser annealing for activating the collector region 201 .

[0135] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. An NPT-IGBT device, characterized in that: include: A drift region, consisting of a first conductivity type lightly doped region formed on the surface of the semiconductor substrate; A well region doped with a second conductivity type is formed on the surface of the drift region; A gate structure, comprising a gate dielectric layer and a gate conductive material layer stacked in sequence; An emitter region heavily doped with a first conductivity type is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region between the emitter region and the drift region serves as a channel region and is covered by the gate structure; A second semiconductor material layer formed on the back side of the semiconductor substrate, wherein the bandgap width of the second semiconductor material layer is lower than the bandgap width of the semiconductor substrate; A collector region heavily doped with a second conductivity type, wherein a top surface of the collector region is flush with or below a top surface of the second semiconductor material layer, and a bottom surface of the drift region further extends to the top surface of the collector region, and the top surface of the collector region and the bottom surface of the drift region are in contact with each other to form a back PN junction; The interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer.

2. The NPT-IGBT device according to claim 1, characterized in that: The material of the semiconductor substrate includes Si.

3. The NPT-IGBT device according to claim 2, characterized in that: The material of the second semiconductor material layer includes Ge and GeSi.

4. The NPT-IGBT device according to claim 3, characterized in that: The second semiconductor material layer is a deposition layer formed on the back side of the semiconductor substrate; Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the second semiconductor material layer is a GeSi layer formed by backside Ge implantation into Si.

5. The NPT-IGBT device according to claim 1, characterized in that: The turn-on voltage of the back PN junction is determined by the second semiconductor material layer, and the turn-on voltage of the back PN junction is reduced by utilizing the lower bandgap width of the second semiconductor material layer.

6. The NPT-IGBT device according to claim 1, characterized in that: The doping impurities in the collector region are back-implanted impurities heavily doped with the second conductivity type or in-situ doping impurities in the second semiconductor material layer; The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer; The junction depth of the collector region is 5 μm; The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 5 μm to 7 μm.

7. The NPT-IGBT device according to claim 1, characterized in that: The gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region; Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

8. A method for manufacturing an NPT-IGBT device, characterized in that: The steps include: Step 1: completing the front process to form the front process structure of the NPT-IGBT device; The front process structure of the NPT-IGBT device includes: A drift region, consisting of a first conductivity type lightly doped region formed on the surface of the semiconductor substrate; A well region doped with a second conductivity type is formed on the surface of the drift region; A gate structure, comprising a gate dielectric layer and a gate conductive material layer stacked in sequence; An emitter region heavily doped with a first conductivity type is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region between the emitter region and the drift region serves as a channel region and is covered by the gate structure; Step 2, thinning the back side of the semiconductor substrate; Step 3: forming a second semiconductor material layer on the back side of the thinned semiconductor substrate; the bandgap width of the second semiconductor material layer is lower than the bandgap width of the semiconductor substrate; Step 4: forming a heavily doped collector region of the second conductivity type, wherein the top surface of the collector region is flush with or below the top surface of the second semiconductor material layer, and the bottom surface of the drift region further extends to the top surface of the collector region, and the top surface of the collector region and the bottom surface of the drift region are in contact with each other to form a back PN junction; The interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer. The turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower bandgap width of the second semiconductor material layer is used to reduce the turn-on voltage of the back PN junction.

9. The method for manufacturing an NPT-IGBT device according to claim 8, characterized in that: The material of the semiconductor substrate includes Si.

10. The method for manufacturing the NPT-IGBT device according to claim 9, characterized in that: The material of the second semiconductor material layer includes Ge and GeSi.

11. The method for manufacturing an NPT-IGBT device according to claim 10, characterized in that: In step three, a deposition process is used to form the second semiconductor material layer on the back side of the thinned semiconductor substrate; Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the process of forming the second semiconductor material layer in step three includes: performing back-side Ge injection, the Ge injected from the back-side Ge and the Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer.

12. The method for manufacturing an NPT-IGBT device according to claim 11, characterized in that: The second semiconductor material layer has been subjected to annealing treatment, and the collector region has been subjected to backside laser annealing treatment; The annealing of the second semiconductor material layer is performed by furnace annealing or back laser annealing.

13. The method for manufacturing an NPT-IGBT device according to claim 12, characterized in that: When the annealing of the second semiconductor material layer includes the furnace tube annealing, the furnace tube annealing of the second semiconductor material layer is performed after step three and before step four; The backside laser annealing is performed after step 4 is completed.

14. The method for manufacturing an NPT-IGBT device according to claim 10, characterized in that: In step 5, the collector region is formed by back ion implantation with heavy doping of the second conductivity type; Alternatively, when the second semiconductor material layer is formed by a deposition process in step 3, step 5 is omitted, and in step 3, the second semiconductor material layer is doped in situ, and the in-situ doped impurities of the second semiconductor material layer are used as doping impurities of the collector region; The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer; The junction depth of the collector region is 1 μm to 5 μm; The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 1 μm to 7 μm.

15. The method for manufacturing an NPT-IGBT device according to claim 8, characterized in that: The gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region; Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

16. The method for manufacturing a NPT-IGBT device according to any one of claims 8 to 15, characterized in that: The NPT-IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the NPT-IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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