A multi-stage trench multi-channel integrated schottky diode MISFET and a manufacturing method thereof

Abstract

The application discloses a kind of multistage trench multi-channel integrated schottky diode's MISFET, comprising: gallium oxide substrate, drain, gallium oxide epitaxial layer, source;Gallium oxide epitaxial layer upper portion is equipped with including M≥2 level sub-trench multistage trench, the opening distance of first level sub-trench to M level sub-trench successively reduces;High resistance zone is equipped in gallium oxide epitaxial layer between multistage trench and the bottom of multistage trench, and N type low resistance zone is equipped on high resistance zone except the bottom of M level sub-trench;Schottky diode is integrated in M level sub-trench;Sub-trench bottom and sidewall except M level are deposited with gate dielectric layer, gate electrode is deposited on the surface of gate dielectric layer, and gate electrode and source are covered with interlayer dielectric layer.The application reduces the electric field at the surface of device, reduces the dependence of device on gate dielectric material thickness, while reducing the forward conduction resistance and third quadrant conduction resistance of device, improves the voltage resistance and reliability of gallium oxide MISFET device.

Description

A MISFET for a multi-level trench multi-channel integrated Schottky diode and its fabrication method Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a multi-level trench multi-channel integrated Schottky diode MISFET and its fabrication method. Background Technology

[0002] In recent years, ultra-wide bandgap semiconductor materials with band gaps larger than SiC and GaN have been considered an exciting and challenging new research field due to their superior optical and electrical properties. The larger band gap allows devices to be used in many extreme environments: in geothermal energy production and oil and gas extraction, they enable higher drilling speeds and lower failure rates; in high-temperature environments, they allow for higher operating temperatures in aluminum plants, steel mills, and coal-fired and gas-fired power plants controlled by electronic sensors, thereby improving the energy efficiency of these industrial processes. Among wide bandgap semiconductor materials, Ga2O3 has a bandgap of 4.8 eV, an ideal breakdown electric field strength of 8 MV / cm, and a BFOM value as high as 3400, approximately four times that of GaN and ten times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga2O3 materials have greater research significance and broader market application prospects. In contrast to the ease of n-type doping, there are currently no reports of successful p-type doping in Ga2O3, which limits the application of Ga2O3 in bipolar power devices compared to materials that can be bipolar-doped.

[0003] Because gallium oxide (GaO) lacks an effective P-type semiconductor, it cannot be fabricated into conventional MOSFET structures like SiC and GaN. Instead, it can only be used to create heterojunction JFETs or MISFETs where the drain, source, and drift region are all N-type conductive. In GaO MISFETs and JFETs, a work function difference exists between the gate metal, polysilicon, and P-type semiconductor and the GaO epitaxial layer, resulting in a depletion layer in the conductive path, affecting the device's operating characteristics. In planar GaO MISFETs, the conductive path is only partially depleted at 0V, not completely depleted, making it a depletion-type device under forward bias. When the device is reverse biased, the gate electrode can shield some of the electric field, but because the depletion region on the GaO epitaxial surface is insufficient, the electric field shielding ability is limited, and the electric field at the metal-semiconductor interface remains strong. As the reverse voltage increases, more and more electrons flow from the source to the drain, resulting in a large reverse leakage current and deteriorating device reliability. On the other hand, when devices operate under high current conditions, they generate a large amount of heat. Since gallium oxide itself has low thermal conductivity, this leads to an increase in device temperature, reducing carrier mobility and consequently decreasing the output current. Therefore, there is a need to further develop junction-enhanced devices that are less affected by temperature and can integrate Schottky diodes.

[0004] To achieve enhancement-mode devices and reduce the electric field at the metal-semiconductor interface, an enhancement-mode MISFET (EMISFET) device is fabricated by etching a gallium oxide epitaxial layer to form trenches on its surface, and then depositing insulating dielectrics such as SiO2 and Al2O3 into the trenches to form the gate dielectric. Compared to planar MISFET devices, EMISFETs exhibit normally-off characteristics because the metal or polysilicon gate can completely deplete the conductive channels. Furthermore, the gate electrode has a certain depth, which can effectively shield part of the electric field under reverse bias, reducing the surface electric field and minimizing leakage current. However, due to the characteristics of gallium oxide, achieving a large depth of gate dielectric deposition cannot be achieved through thermal oxidation; instead, deep trenches must be formed in the gallium oxide material, and then the gate dielectric is deposited on the surface of these trenches. However, the significant depth of these trenches leads to uneven thickness of the gate dielectric layer within the trenches, affecting the uniformity of the device's threshold voltage. While EMISFETs effectively reduce the surface electric field during reverse operation, the limited trench depth means the peak electric field is close to the surface, allowing some field lines to still penetrate the gate and reach the source. This results in a still strong electric field at the metal-semiconductor interface, leading to significant leakage current and impacting device reliability. More importantly, the thin gate dielectric material typically used for enhancement-mode devices means the gate dielectric can only withstand a small voltage when the peak electric field shifts from the surface to the bulk trench, making breakdown more likely. Therefore, the breakdown voltage and forward conduction characteristics of EMISFETs are affected by the gate dielectric thickness, preventing the full utilization of gallium oxide's high breakdown field strength. Furthermore, deeper trenches result in higher channel resistance, requiring a larger voltage to conduct the same current. Due to gallium oxide's low thermal conductivity, heat cannot dissipate quickly enough, causing the device temperature to rise and affecting the output current. Additionally, existing devices operating in the third quadrant are also affected by the depletion layer of the conductive channel, increasing on-resistance and negatively impacting third-quadrant performance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a MISFET device unit structure for a multi-level trench multi-channel integrated Schottky diode, which further reduces the electric field at the device surface, reduces the device's dependence on the thickness of the gate dielectric material, and simultaneously reduces the device's forward conduction resistance and third quadrant conduction resistance, thereby improving the voltage withstand capability and reliability of the gallium oxide MISFET device.

[0006] To achieve the above objectives, the present invention adopts the following technical solution.

[0007] This invention provides a multi-level trench multi-channel integrated Schottky diode MISFET, comprising: a gallium oxide substrate, a drain located on the bottom side of the gallium oxide substrate, a gallium oxide epitaxial layer located on the upper side of the gallium oxide substrate, and a source located above the gallium oxide epitaxial layer; the upper part of the gallium oxide epitaxial layer is provided with multi-level trenches, the multi-level trenches including M≥2 sub-trenches, the opening distance of the first-level sub-trench to the Mth-level sub-trench decreasing sequentially; high-resistance regions are provided between the multi-level trenches and within the gallium oxide epitaxial layer at the bottom of the multi-level trenches, and N-type low-resistance regions are provided on the high-resistance regions except at the bottom of the Mth-level sub-trench; Schottky metal is deposited in the Mth-level sub-trench to form a Schottky diode; a gate dielectric layer is deposited at the bottom and sidewalls of the sub-trenches except the Mth-level sub-trench, a gate electrode is deposited on the surface of the gate dielectric layer, and an interlayer dielectric layer covers the gate electrode and the source.

[0008] In some embodiments, the Schottky Schottky diode is located at the bottom and / or sidewall of the Mth sub-trench.

[0009] In some embodiments, the high-resistivity region is obtained by ion implantation of nitrogen into the gallium oxide epitaxial layer, or by annealing the gallium oxide epitaxial layer in an oxygen atmosphere at 1000–1400°C for 1–24 hours.

[0010] In some embodiments, the high-resistivity region is a P-type oxide, which is one of NiO and Cu2O.

[0011] In some embodiments, the N-type low-resistivity region is obtained by ion implantation of Si elements from the high-resistivity region.

[0012] In some embodiments, the material of the gate dielectric layer is selected from p-type oxide and Al2O3.

[0013] In some embodiments, the gate electrode is made of metal or polycrystalline silicon.

[0014] The present invention also provides a method for fabricating the above-mentioned multi-level trench multi-channel integrated Schottky diode MISFET, comprising the following steps:

[0015] S1. Deposit drain metal on the bottom side of a gallium oxide substrate including a gallium oxide epitaxial layer to form a drain;

[0016] S2. A high-resistivity region is formed on the gallium oxide epitaxial layer;

[0017] S3. An N-type low-resistance region is formed on the high-resistance region;

[0018] S4. Etch the gallium oxide epitaxial layer to form a multi-level trench including M-level sub-trenches;

[0019] S5. A high-resistivity region is formed on the gallium oxide epitaxial layer at the bottom of the multi-level trench;

[0020] S6. An N-type low-resistivity region is formed on the high-resistivity region except for the bottom of the Mth sub-trench;

[0021] S7. Deposit gate dielectric at the bottom and sidewalls of sub-trenches other than the Mth stage to form a patterned gate dielectric layer;

[0022] S8. Deposit a gate electrode on the surface of the gate dielectric layer;

[0023] S9. Deposit an insulating medium on the surface of the epitaxial layer, pattern it to form an interlayer dielectric layer, and then remove the insulating medium from the bottom and sidewalls of the Mth sub-trench;

[0024] S10. Deposit Schottky metal on the surface of the Mth sub-trench to pattern and form a Schottky diode;

[0025] S11. Re-graphicalize the interlayer dielectric, and open a window in the region above the N-type low-resistivity region;

[0026] S12. Deposit source metal to fill multi-level trenches and form the source electrode.

[0027] In some embodiments, in steps S2 and S5, the method for forming the high-resistivity region is to ion implant N element into the gallium oxide epitaxial layer, or to anneal the gallium oxide epitaxial layer in an oxygen atmosphere at 1000–1400°C for 1–24 hours.

[0028] In some embodiments, in steps S2 and S5, the method for forming the high-resistivity region is to deposit a P-type oxide on the surface of the gallium oxide epitaxial layer.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] (1) The epitaxial layer of this invention uses multi-level trenches to fabricate multi-channel MISFET devices, which reduces channel resistance, increases output current, and reduces the influence of temperature on the device. Carriers can flow in the crystal direction with the highest mobility, which can fully utilize the material properties. At the same time, a Schottky diode is integrated in the last trench. Since the Schottky diode is inside the trench of the epitaxial layer, it has a small on-resistance, which can reduce the on-state voltage drop of the device. When the device is operating in the third quadrant, it can be used as a freewheeling diode, reducing the cost of external devices.

[0031] (2) The epitaxial layer of this invention adopts multi-level trenches and forms a high-resistivity layer by ion implantation. On the one hand, it can realize enhancement-mode devices without the trench spacing being too close, thus increasing the photolithography process window. On the other hand, the high-resistivity layer can serve as a quasi-P-type layer, enabling channel inversion and shielding the electric field. The high-resistivity layer formed by implantation can enable current to flow in different crystal directions, reducing on-resistance and enabling transmission in the crystal direction with the highest carrier mobility. The high-resistivity layer at the bottom of adjacent trenches can shield the high electric field during reverse operation, reducing the surface electric field strength of the device and the surface electric field strength of the Schottky barrier. This is beneficial for protecting the Schottky barrier and gate dielectric from premature breakdown, reducing device leakage current, and improving device reliability. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the MISFET device structure in Example 1;

[0033] Figure 2 is a schematic diagram of the fabrication process of the MISFET device in Example 1;

[0034] Figure 3 is a schematic diagram of the operating current path of the MISFET device in Example 1;

[0035] Figure 4 is a schematic diagram of the MISFET device structure in Example 2;

[0036] Figure 5 is a schematic diagram of the MISFET device structure in Example 3. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to specific embodiments, so that those skilled in the art can more clearly understand the present invention. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention. In the embodiments of the present invention, unless otherwise specified, all raw material components are commercially available products well known to those skilled in the art; unless specifically specified, the technical means used are all conventional means well known to those skilled in the art.

[0038] This invention provides a multi-level trench multi-channel integrated Schottky diode MISFET, comprising: a gallium oxide substrate, a drain located on the bottom side of the gallium oxide substrate, a gallium oxide epitaxial layer located on the top side of the gallium oxide substrate, and a source located above the gallium oxide epitaxial layer; a multi-level trench is provided on the upper part of the gallium oxide epitaxial layer, the multi-level trench including M≥2 sub-trenches, the opening distance from the first sub-trench to the Mth sub-trench decreasing sequentially; a high-resistance region is provided between the multi-level trenches and in the gallium oxide epitaxial layer at the bottom of the multi-level trenches, and an N-type low-resistance region is provided on the high-resistance region except at the bottom of the Mth sub-trench; a Schottky metal is deposited in the Mth sub-trench to form a Schottky diode; a gate dielectric layer is deposited at the bottom and sidewalls of the sub-trenches except the Mth sub-trench, a gate electrode is deposited on the surface of the gate dielectric layer, and an interlayer dielectric layer covers the gate electrode and the source.

[0039] In some implementations, the Schottky Schottky diode is located at the bottom and / or sidewall of the Mth sub-trench.

[0040] In some embodiments, the high-resistivity region is obtained by ion implantation of nitrogen into the gallium oxide epitaxial layer, or by annealing the gallium oxide epitaxial layer in an oxygen atmosphere at 1000–1400°C for 1–24 hours.

[0041] In some embodiments, the high-resistivity region is a P-type oxide, which is one of NiO and Cu2O.

[0042] In some implementations, the N-type low-resistivity region is obtained by ion implantation of Si elements as a high-resistivity region.

[0043] In some embodiments, the material of the gate dielectric layer is selected from p-type oxide and Al2O3.

[0044] In some implementations, the gate electrode is made of metal or polycrystalline silicon.

[0045] The method for fabricating the multi-level trench multi-channel integrated Schottky diode MISFET provided in this embodiment of the invention includes the following steps:

[0046] S1. Deposit drain metal on the bottom side of a gallium oxide substrate including a gallium oxide epitaxial layer to form a drain;

[0047] S2. A high-resistivity region is formed on the gallium oxide epitaxial layer;

[0048] S3. An N-type low-resistance region is formed on the high-resistance region;

[0049] S4. Etch the gallium oxide epitaxial layer to form a multi-level trench including M-level sub-trenches;

[0050] S5. A high-resistivity region is formed on the gallium oxide epitaxial layer at the bottom of the multi-level trench;

[0051] S6. An N-type low-resistivity region is formed on the high-resistivity region except for the bottom of the Mth sub-trench;

[0052] S7. Deposit gate dielectric at the bottom and sidewalls of sub-trenches other than the Mth stage to form a patterned gate dielectric layer;

[0053] S8. Deposit a gate electrode on the surface of the gate dielectric layer;

[0054] S9. Deposit an insulating medium on the surface of the epitaxial layer, pattern it to form an interlayer dielectric layer, and then remove the insulating medium from the bottom and sidewalls of the Mth sub-trench;

[0055] S10. Deposit Schottky metal on the surface of the Mth sub-trench to pattern and form a Schottky diode;

[0056] S11. Re-graphicalize the interlayer dielectric, and open a window in the region above the N-type low-resistivity region;

[0057] S12. Deposit source metal to fill multi-level trenches and form the source electrode.

[0058] In some embodiments, in steps S2 and S5, the method for forming the high-resistivity region is to ion implant N element into the gallium oxide epitaxial layer, or to anneal the gallium oxide epitaxial layer in an oxygen atmosphere at 1000–1400°C for 1–24 hours.

[0059] In some embodiments, in steps S2 and S5, the method for forming the high-resistivity region is to deposit a P-type oxide on the surface of the gallium oxide epitaxial layer.

[0060] Example 1

[0061] The MISFET device structure of a multi-level trench multi-channel integrated Schottky diode provided in this embodiment is shown in Figure 1. A drain 3 is deposited on the bottom side of a gallium oxide substrate 1, and a gallium oxide epitaxial layer 2 is deposited on the top side of the gallium oxide substrate 1. Secondary trenches are provided on the upper part of the gallium oxide epitaxial layer 2, and the opening distance of the first-level sub-trench is greater than that of the second-level sub-trench. High-resistance regions 5 are provided between the secondary trenches and in the gallium oxide epitaxial layer 2 at the bottom of the secondary trenches. High-resistance regions 501, except for the bottom of the second-level sub-trench, are provided. N-type low-resistance region 6 is provided on 502; the thickness of high-resistance regions 501 and 502 is less than the depth of adjacent sub-trench; Schottky metal is deposited on the bottom and sidewalls of the second-stage sub-trench, and a Schottky diode 7 is formed on the sidewall; a gate dielectric layer 8 is deposited on the bottom and sidewalls of the first-stage sub-trench, a gate electrode 9 is deposited on the surface of the gate dielectric layer 8, and an interlayer dielectric layer 10 is covered on the surface of the gate electrode 9 to isolate the gate electrode 9 from the source electrode 4; a portion of the N-type low-resistance regions 601 and 602 are in contact with the source electrode 4.

[0062] The specific fabrication process of the multi-level trench multi-channel integrated Schottky diode MISFET provided in this embodiment is shown in Figure 2. First, a drain metal Ti / Au is deposited on the bottom side of the gallium oxide substrate 1, including the gallium oxide epitaxial layer 2, to form a back ohmic contact and form the drain 3. Then, N elements are ion implanted into the surface of the gallium oxide epitaxial layer 2 to form a high-resistivity region 501. Then, an N-type low-resistivity region 601 is formed on the high-resistivity region 501 by ion implantation of Si elements. Next, the gallium oxide epitaxial layer 2 is etched to form a secondary trench. N elements are ion implanted into the gallium oxide epitaxial layer 2 at the bottom of the secondary trench to form high-resistivity regions 502 and 503. An N-type low-resistivity region 602 is formed on the high-resistivity region 502 at the bottom of the first sub-trench by ion implantation of Si elements. Al2O3 insulating dielectric is deposited at the bottom and sidewalls of the first sub-trench and patterned to form gate dielectric layer 8; polysilicon is deposited on the surface of gate dielectric layer 8 and patterned to form gate electrode 9; then SiO2 insulating dielectric is deposited on the entire surface of the epitaxial layer and patterned to form interlayer dielectric layer 10, and then the SiO2 insulating dielectric at the bottom and sidewalls of the second sub-trench is removed; Schottky metal Ni is deposited at the bottom and sidewalls of the second sub-trench and patterned, and Schottky diode 7 is formed on the sidewall of the second sub-trench; the interlayer dielectric is patterned again, and a window is opened in the region above the N-type low-resistivity regions 601 and 602; finally, source metal Ti / Au is deposited to form ohmic contact with the N-type low-resistivity regions 601 and 602, filling the trench to form source 4.

[0063] Figure 3 shows the current path diagrams of the multi-channel integrated Schottky diode MISFET device in this embodiment during forward conduction and operation in the third quadrant. A represents the current path during conduction in the third quadrant, and B represents the current path during forward conduction. It can be seen that during forward conduction, multiple channels participate in conduction, reducing the on-resistance. During conduction in the third quadrant, the Schottky diode on the sidewall of the second-stage trench conducts, resulting in a shorter conduction path and reduced conduction losses.

[0064] Example 2

[0065] The MISFET device structure of a multi-level trench multi-channel integrated Schottky diode provided in this embodiment is shown in Figure 4. A drain 3 is deposited on the bottom side of a gallium oxide substrate 1, and a gallium oxide epitaxial layer 2 is deposited on the top side of the gallium oxide substrate 1. Three levels of trenches are provided on the upper part of the gallium oxide epitaxial layer 2, and the opening distance from the first level sub-trench to the third level sub-trench decreases sequentially. High-resistance regions 5 are provided between the three levels of trenches and in the gallium oxide epitaxial layer 2 at the bottom of the three levels of trenches. High-resistance regions 501 and 502 are provided except for the bottom of the third level sub-trench. N-type low-resistance region 6 is provided on 503; the thickness of high-resistance regions 501, 502, and 503 is less than the depth of adjacent sub-trenches; Schottky metal is deposited on the bottom and sidewalls of the third-stage sub-trench, forming a Schottky diode 7 on the sidewalls; gate dielectric layer 8 is deposited on the bottom and sidewalls of the first and second-stage sub-trenches, gate electrode 9 is deposited on the surface of gate dielectric layer 8, and an interlayer dielectric layer 10 is covered on the surface of gate electrode 9 to isolate gate electrode 9 from source electrode 4; N-type low-resistance regions 601 and 603 are in contact with the source electrode in some areas.

[0066] The specific fabrication process of the multi-level trench multi-channel integrated Schottky diode MISFET provided in this embodiment is as follows: First, a drain metal Ti / Au is deposited on the bottom side of a gallium oxide substrate 1, including a gallium oxide epitaxial layer 2, to form a back ohmic contact and create a drain 3; then, the gallium oxide epitaxial layer 2 is annealed at 1400°C in an oxygen atmosphere for 1 hour to form a high-resistance region 501; then, an N-type low-resistance region 601 is formed on the high-resistance region 501 by ion implantation of Si; next, the gallium oxide epitaxial layer 2 is etched to form a three-level trench; the gallium oxide epitaxial layer 2 is annealed again at 1400°C in an oxygen atmosphere for 1 hour to form high-resistance regions 502, 503, and 504 on the gallium oxide epitaxial layer 2 at the bottom of the three-level trench; ion implantation of Si is performed on the high-resistance regions 502 and 503 at the bottom of the first and second level sub-trenches. Elements are used to form N-type low-resistivity regions 602 and 603; Al2O3 insulating dielectric is deposited at the bottom and sidewalls of the first and second sub-trenches and patterned to form gate dielectric layer 8; polysilicon is deposited on the surface of gate dielectric layer 8 and patterned to form gate electrode 9; then SiO2 insulating dielectric is deposited on the entire surface of the epitaxial layer and patterned to form interlayer dielectric layer 10, and then the SiO2 insulating dielectric at the bottom and sidewalls of the third sub-trench is removed; Schottky metal Ni is deposited at the bottom and sidewalls of the third sub-trench and patterned, and Schottky diode 7 is formed on the sidewall of the third sub-trench; the interlayer dielectric is patterned again, and a window is opened in the region above the N-type low-resistivity regions 601 and 603; finally, source metal Ti / Au is deposited to form ohmic contact with the N-type low-resistivity regions 601 and 603, filling the trench to form source 4.

[0067] Example 3

[0068] The MISFET device structure of a multi-level trench multi-channel integrated Schottky diode provided in this embodiment is shown in Figure 5. A drain 3 is deposited on the bottom side of a gallium oxide substrate 1, and a gallium oxide epitaxial layer 2 is deposited on the top side of the gallium oxide substrate 1. A secondary trench is provided on the upper part of the gallium oxide epitaxial layer 2, and the opening distance of the first-level sub-trench is greater than that of the second-level sub-trench. High-resistance regions 5 are provided between the secondary trenches and in the gallium oxide epitaxial layer 2 at the bottom of the secondary trenches. N-type low-resistance regions are provided on the high-resistance regions 501 and 502 except at the bottom of the second-level sub-trench. 6; The high-resistivity regions 502 and 503 at the bottom of the first-stage sub-trench are connected to the second-stage sub-trench, and the high-resistivity region 503 at the bottom of the second-stage sub-trench is discontinuous; Schottky metal is deposited at the bottom of the second-stage sub-trench, forming a Schottky diode 7 at the bottom; A gate dielectric layer 8 is deposited at the bottom and sidewalls of the first-stage sub-trench, and a gate electrode 9 is deposited on the surface of the gate dielectric layer 8. An interlayer dielectric layer 10 is covered on the surface of the gate electrode 9 to isolate the gate electrode 9 from the source electrode 4; Parts of the N-type low-resistivity regions 601 and 602 are in contact with the source electrode 4.

[0069] Example 4

[0070] This embodiment provides a MISFET device structure for a multi-level trench multi-channel integrated Schottky diode. The difference between this embodiment and Embodiment 1 is that the high-resistivity region is formed by depositing a P-type oxide NiO on the surface of the gallium oxide epitaxial layer 2 during the fabrication process.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A MISFET for a multi-level trench multi-channel integrated Schottky diode, characterized in that, include: A gallium oxide substrate, a drain located on the bottom side of the gallium oxide substrate, a gallium oxide epitaxial layer located on the top side of the gallium oxide substrate, and a source located above the gallium oxide epitaxial layer; the upper part of the gallium oxide epitaxial layer is provided with multi-level trenches, the multi-level trenches include M≥2 sub-trenches, the opening distance from the first sub-trench to the Mth sub-trench decreases sequentially, and the opening distance of the trench closer to the bottom of the trench is smaller; high-resistance regions are provided between the multi-level trenches and in the gallium oxide epitaxial layer at the bottom of the multi-level trenches, and N-type low-resistance regions are provided on the high-resistance regions except at the bottom of the Mth sub-trench; Schottky metal is deposited in the Mth sub-trench to form a Schottky diode; a gate dielectric layer is deposited on the bottom and sidewalls of the sub-trenches except the Mth sub-trench, a gate electrode is deposited on the surface of the gate dielectric layer, and an interlayer dielectric layer covers the gate electrode and the source.

2. The MISFET of the multi-level trench multi-channel integrated Schottky diode according to claim 1, characterized in that, The Schottky diode is located at the bottom and / or sidewall of the Mth sub-trench.

3. The MISFET of the multi-level trench multi-channel integrated Schottky diode according to claim 1, characterized in that, The high-resistivity region is obtained by ion implantation of nitrogen element into the gallium oxide epitaxial layer, or by annealing the gallium oxide epitaxial layer in an oxygen atmosphere at 1000~1400℃ for 1~24h.

4. The MISFET of the multi-level trench multi-channel integrated Schottky diode according to claim 1, characterized in that, The high-resistivity region is a P-type oxide, which is either NiO or Cu2O.

5. The MISFET of the multi-level trench multi-channel integrated Schottky diode according to claim 1, characterized in that, The N-type low-resistivity region is obtained by ion implantation of Si elements into the high-resistivity region.

6. The MISFET of the multi-level trench multi-channel integrated Schottky diode according to claim 1, characterized in that, The material of the gate dielectric layer is selected from either P-type oxide or Al2O3.

7. The MISFET of the multi-level trench multi-channel integrated Schottky diode according to claim 1, characterized in that, The gate electrode is made of metal or polycrystalline silicon.

8. A method for fabricating a MISFET of a multi-level trench multi-channel integrated Schottky diode according to any one of claims 1 to 7, characterized in that, Includes the following steps: S1. Deposit drain metal on the bottom side of a gallium oxide substrate including a gallium oxide epitaxial layer to form a drain; S2. Form a high-resistivity region on the gallium oxide epitaxial layer; S3. Form an N-type low-resistivity region on the high-resistivity region; S4. Etch the gallium oxide epitaxial layer to form a multi-level trench including M-level sub-trenches; S5. Form a high-resistivity region on the gallium oxide epitaxial layer at the bottom of the multi-level trenches; S6. Form an N-type low-resistivity region on the high-resistivity region except at the bottom of the M-level sub-trench; S7. Deposit gate dielectric at the bottom and sidewalls of sub-trenches other than the Mth stage to form a patterned gate dielectric layer; S8. Deposit a gate electrode on the surface of the gate dielectric layer; S9. Deposit an insulating dielectric on the surface of the epitaxial layer to form an interlayer dielectric layer, and then remove the insulating dielectric from the bottom and sidewalls of the Mth sub-trench; S10. Deposit Schottky metal on the surface of the Mth sub-trench to form a Schottky diode; S11. Re-graphicalize the interlayer dielectric, opening a window in the region above the N-type low-resistivity region; S12. Deposit source metal to fill multi-level trenches and form the source.

9. The method for fabricating a MISFET of a multi-level trench multi-channel integrated Schottky diode according to claim 8, characterized in that, In steps S2 and S5, the method for forming the high-resistivity region is to implant N element into the gallium oxide epitaxial layer, or to anneal the gallium oxide epitaxial layer in an oxygen atmosphere at 1000~1400℃ for 1~24h.

10. The method for fabricating a MISFET of a multi-level trench multi-channel integrated Schottky diode according to claim 8, characterized in that, In steps S2 and S5, the method for forming the high-resistivity region is to deposit a P-type oxide on the surface of the gallium oxide epitaxial layer.

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