IGBT structure and semiconductor device

Abstract

The invention discloses an IGBT structure and a semiconductor device, the IGBT structure comprises a substrate, a drift, a collector region of a first conduction type, an active gate, a body region of the first conduction type, a first emitter region of a second conduction type and a virtual gate, and the virtual gate extends from a second main surface of the substrate to a first main surface of the substrate into the drift region; wherein the drift region comprises first column regions of a first conduction type and second column regions of a second conduction type, and the first column regions and the second column regions are alternately arranged in the horizontal direction; one end, facing the first main surface, of the active gate extends into the second column region, and one end, facing the first main surface, of the virtual gate extends into the first column region. According to the IGBT structure and the semiconductor device provided by the invention, the conduction loss can be obviously reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an IGBT structure and a semiconductor device. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a MOS-bipolar compound transistor developed on the basis of power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It has the common advantages of power bipolar transistors and power MOSFETs, and has different advantages in on-state voltage drop and switching, making it a core device in power supply, drive and control circuits.

[0003] In order to meet different application scenarios, IGBT needs to achieve a good balance and trade-offs in conduction and switching, and should also achieve lower conduction losses as much as possible to improve power conversion efficiency.

[0004] In the existing IGBT structure, the carrier flow path in the drift region is usually relatively single, resulting in a problem of large conduction loss.

[0005] Therefore, improvements are needed to at least partially solve the above problems. Summary of the invention

[0006] The present invention aims to at least partially solve the above problems. To this end, one object of the present invention is to provide an IGBT structure having lower conduction loss. Another object of the present invention is to provide a semiconductor device having the IGBT structure.

[0007] The IGBT structure according to an embodiment of the present invention includes:

[0008] A substrate, the substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a vertical direction;

[0009] a drift region, wherein the drift region is disposed between the first main surface and the second main surface;

[0010] A collector region of a first conductivity type, the collector region being disposed on a side of the drift region facing the first main surface, and a side of the collector region away from the drift region constituting at least a portion of the first main surface;

[0011] an active gate extending from the second main surface to the first main surface into the drift region;

[0012] a body region of a first conductivity type, the body region being disposed on a side of the drift region facing the second main surface and located on both sides of the active gate in a horizontal direction;

[0013] A first emitter region of a second conductivity type, the first emitter region being arranged on a side of the body region facing the second main surface, and a side of the first emitter region away from the body region constituting a part of the second main surface;

[0014] A dummy gate extending from the second main surface to the first main surface into the drift region;

[0015] Wherein, the drift region includes a first column region of a first conductivity type and a second column region of a second conductivity type, and the first column region and the second column region are alternately arranged in a horizontal direction;

[0016] One end of the active gate facing the first main surface extends into the second column region, and one end of the dummy gate facing the first main surface extends into the first column region.

[0017] Optionally, the IGBT structure further includes a second emitter region of the first conductivity type, the second emitter region is arranged in the first emitter region, and a side of the second emitter region away from the first main surface constitutes at least a part of the second main surface.

[0018] Optionally, the IGBT structure further includes:

[0019] an insulating layer, the insulating layer being disposed on the second main surface, and a contact hole being disposed on a portion of the insulating layer corresponding to the second emitter region;

[0020] An emitter metal, the emitter metal is disposed on a side of the insulating layer away from the second main surface and in the contact hole, and the emitter metal is in contact with the second emitter region;

[0021] A collector metal is provided on the first main surface.

[0022] Optionally, the virtual gate includes a first gate trench extending from the second main surface to the first main surface to the first column region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench;

[0023] The first polysilicon gate contacts the emitter metal.

[0024] Optionally, the virtual gate includes a first gate trench extending from the second main surface to the first main surface to the first column region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench;

[0025] The first polysilicon gate is a floating gate.

[0026] Optionally, the IGBT structure further includes a doped region of a second conductivity type, the doped region is located on both sides of the virtual gate in the horizontal direction and is in contact with the first emitter region, and a side of the doped region away from the first main surface constitutes at least a portion of the second main surface.

[0027] Optionally, the IGBT structure further includes a field stop region of the second conductivity type, and the field stop region is arranged between the collector region and the drift region.

[0028] Optionally, the active gate includes a second gate trench extending from the second main surface to the first main surface to the second column region, a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench.

[0029] Optionally, the first conductivity type is P type;

[0030] The second conductivity type is N type.

[0031] The semiconductor device according to the embodiment of the present invention includes the IGBT structure as described above.

[0032] According to the IGBT structure and semiconductor device of the present invention, the drift region includes a first column region of a first conductivity type and a second column region of a second conductivity type alternately arranged in a horizontal direction. The arrangement of the first column region and the second column region can increase the carrier flow path, improve the unbalanced carrier injection efficiency, and reduce the conduction voltage drop in the drift region. The arrangement of the virtual gate can enhance the carrier storage effect in the first column region, further reduce the conduction voltage drop in the first column region, and thus significantly reduce the conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The following drawings of the present application are hereby used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the device and principle of the present application. In the drawings,

[0034] Figure 1 is a schematic cross-sectional view of an IGBT structure according to an embodiment of the present application;

[0035] Figure 2is a schematic diagram of the principle of an IGBT structure according to an embodiment of the present application;

[0036] Figure 3-Figure 9 Schematic cross-sectional views of various steps of a method for manufacturing an IGBT structure according to an embodiment of the present application.

[0037] Description of reference numerals:

[0038] 10-substrate, 11-first pillar, 12-second pillar, 13-first gate trench, 14-second gate trench, 15-second doping region;

[0039] 100-substrate, 101-first main surface, 102-second main surface, 110-drift region, 111-first column region, 112-second column region, 120-collector region, 130-active gate, 140-body region, 150-first emitter region, 160-dummy gate, 170-second emitter region, 180-doped region, 190-field stop region;

[0040] 200-insulating layer, 210-contact hole;

[0041] 300-emitter metal;

[0042] 400 - Collector Metal. DETAILED DESCRIPTION

[0043] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0044] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0045] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0046] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to display the actual shape of the device and are not intended to limit the scope of the present application.

[0049] See attached Figure 1 , 2 The structure of an IGBT according to an embodiment of the present invention is described as an example. In the following description, N and P represent the conductivity type of the semiconductor. In the following description, the first conductivity type is set as P type and the second conductivity type is set as N type.

[0050] The IGBT structure mainly includes: a substrate 100 , a drift region 110 , a collector region 120 of a first conductivity type, an active gate 130 , a body region 140 of a first conductivity type, a first emitter region 150 of a second conductivity type, and a dummy gate 160 .

[0051] The substrate 100 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101. The first main surface 101 and the second main surface 102 are vertically aligned. Figure 1 The interval setting is in the up and down directions.

[0052] The drift region 110 is disposed between the first main surface 101 and the second main surface 102. The drift region 110 determines the saturation voltage drop and voltage level of the IGBT and is the main region that affects the switching speed of the IGBT.

[0053] The collector region 120 of the first conductivity type is disposed on a side of the drift region 110 facing the first main surface 101 , and a side of the collector region 120 away from the drift region 110 constitutes at least a portion of the first main surface 101 .

[0054] The active gate 130 extends from the second main surface 102 to the first main surface 101 into the drift region 110. The active gate 130 is a gate structure that actually plays a controlling role in the IGBT and can form a conductive channel. When a gate voltage is applied to the active gate 130, a conductive channel can be formed around the active gate 130, so that electrons and holes can move in the channel, thereby controlling the on and off of the IGBT.

[0055] The first conductive type body region 140 is disposed on a side of the drift region 110 facing the second main surface 102 and is located at a position between the active gate 130 and the active gate 130 in the horizontal direction (ie, Figure 1 on both sides of the left and right direction).

[0056] The first emitter region 150 of the second conductivity type is disposed on the side of the body region 140 facing the second main surface 102, and the side of the first emitter region 150 away from the body region 140 constitutes a part of the second main surface 102. Exemplarily, the first emitter region 150 is also called a source region.

[0057] The dummy gate 160 extends from the second main surface 102 to the first main surface 101 into the drift region 110. The dummy gate 160 is a gate structure that exists in the IGBT structure but does not directly participate in the conduction, and it usually cannot form a conductive channel. Exemplarily, the dummy gate 160 can also be called a dummy cell narrow groove gate (dummy gate).

[0058] In this embodiment, the drift region 110 includes a first column region 111 of a first conductivity type and a second column region 112 of a second conductivity type, and the first column region 111 and the second column region 112 (i.e., a P column region and an N column region) are alternately arranged in a horizontal direction, that is, the drift region 110 forms a super junction structure. The active gate 130 extends to the second column region 112 at one end toward the first main surface 101, and the dummy gate 160 extends to the first column region 111 at one end toward the first main surface 101.

[0059] On the one hand, the drift region 110 includes the first column region 111 and the second column region 112 which are alternately arranged to increase the carrier flow path. Figure 2 In addition to being able to enter the second column region 112 from bottom to top, carriers (such as holes) can also enter the second column region 112 from bottom to top. Figure 2As shown in A, carriers (such as holes) can also enter the second column region 112 from the first column region 111 in the horizontal direction, and carriers (such as electrons) in the second column region 112 can also enter the first column region 111 in the horizontal direction. For a conventional IGBT structure, the drift region 110 is usually all of the second conductivity type, and carriers (such as holes) can only enter the second column region 112 from bottom to top. Therefore, the IGBT structure of this embodiment effectively increases the unbalanced carrier flow path, improves the unbalanced carrier injection efficiency, enhances the conductivity modulation effect, reduces the conduction voltage drop of the drift region 110, and thus reduces the conduction loss.

[0060] On the other hand, the drift region 110 forms a cellular structure in which the first column region 111 and the second column region 112 alternate in the horizontal direction. In the cut-off state, the first column region 111 and the second column region 112 constituting the super junction structure are in a completely depleted state, and the electric field distribution in the space charge region is approximately a rectangular distribution (e.g. Figure 2 As shown at B in the figure, the entire drift region 110 is more uniform when subjected to voltage, and each part can effectively share the voltage, thereby effectively improving the forward withstand voltage capability of the IGBT structure.

[0061] In addition, since one end of the virtual gate 160 toward the first main surface 101 extends into the first column region 111, when the IGBT structure is turned on, no electron channel is generated at the virtual gate 160, and the path of holes passing through the first column region 111 to the emitter region is blocked (e.g., Figure 2 As shown in C in the middle, the carrier storage effect in the first column region 111 is enhanced, which can effectively increase the number of unbalanced carriers in the drift region 110, further reduce the conduction voltage drop of the first column region 111, and thus reduce the conduction loss.

[0062] Further, see Appendix Figure 1 The IGBT structure further includes a second emitter region 170 of the first conductivity type, the second emitter region 170 is disposed in the first emitter region 150, and the side of the second emitter region 170 away from the first main surface 101 constitutes at least a portion of the second main surface 102. The provision of the second emitter region 170 can effectively reduce the on-resistance and improve the switching speed. Exemplarily, the doping concentration of the second emitter region 170 is higher than the doping concentration of the body region 140.

[0063] Further, see Appendix Figure 1 The IGBT structure further includes: an insulating layer 200 , an emitter metal 300 and a collector metal 400 .

[0064] The insulating layer 200 is disposed on the second main surface 102, and a contact hole 210 is disposed in a portion of the insulating layer 200 corresponding to the second emitter region 170. The insulating layer 200 covers the side of the source gate 130 away from the first main surface 101, the side of the dummy gate 160 away from the first main surface 101, and the side of the first emitter region 150 away from the first main surface 101 on the second main surface 102. The second emitter region 170 is exposed at the bottom of the contact hole 210. Exemplarily, the insulating layer 200 is also called an interlayer dielectric layer, which can be a silicon dioxide layer.

[0065] The emitter metal 300 is disposed on the side of the insulating layer 200 away from the second main surface 102 and is disposed in the contact hole 210. The emitter metal 300 contacts the second emitter region 170 to form a conductive connection. The collector metal 400 is disposed on the first main surface 101 and contacts the collector region 120 to form a conductive connection. The emitter metal 300 and the collector metal 400 are used to realize the electrical extraction of the second emitter region 170 and the collector region 120, respectively.

[0066] Furthermore, the virtual gate 160 includes a first gate trench extending from the second main surface 102 to the first main surface 101 to the first column region 111, a first gate dielectric layer located on the inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench. The active gate 130 includes a second gate trench extending from the second main surface 102 to the first main surface 101 to the second column region 112, a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench.

[0067] The first polysilicon gate contacts the emitter metal 300 (the specific contact position is not shown in the figure), that is, the virtual gate 160 is short-circuited with the emitter. By short-circuiting the virtual gate 160 with the emitter, the virtual gate 160 can have the same properties as the emitter, with negative charge, and when a large number of holes pass through the second column region 112 and the body region 140, some holes can be attracted to transfer to the virtual gate 160 (such as Figure 2 As shown in D in the figure, the number of holes flowing under the first emitter is reduced, that is, the number of holes flowing in the channel is reduced, thereby reducing the risk of latch-up effect under high current conditions.

[0068] In some other embodiments, the first polysilicon gate in the virtual gate 160 may be a floating gate, that is, the first polysilicon gate is a gate that is not directly electrically connected to an external circuit. It is surrounded by an insulating layer (that is, the first gate dielectric layer and the insulating layer 200), is in a "floating" state, and is not directly connected to a fixed potential point such as a power supply or ground.

[0069] Further, see Appendix Figure 1The IGBT structure further includes a doping region 180 of the second conductivity type, which is located on both sides of the virtual gate 160 in the horizontal direction and in contact with the first emitter region 150. The side of the doping region 180 away from the first main surface 101 constitutes at least a part of the second main surface 102. Specifically, in this embodiment, the body region 140 is arranged on the side of the second column region 112 facing the second main surface 102, and is located on both sides of the active gate 130 in the horizontal direction. The part of the first column 11 on the side of the virtual gate 160 facing the active gate 130 is also used to realize the function of the body region 140. The doping region 180 located on the side of the virtual gate 160 facing the active gate 130 is in contact with the first emitter region 150 and is used to realize the function of the first emitter region 150. The doping region 180 located on the side of the virtual gate 160 away from the active gate 130 can play a blocking role, limit the movement of holes, and enhance the carrier storage effect. In this embodiment, the doped region 180 located on the side of the dummy gate 160 facing the active gate 130 may also be in contact with the second emission region 170 .

[0070] In some other embodiments, the first emission region 150 may be disposed only on both sides of the active gate 130 , and the doping region 180 may not be disposed on both sides of the dummy gate 160 . The side of the first column region 111 away from the first main surface 101 constitutes part of the second main surface 102 .

[0071] Further, see Appendix Figure 1 The IGBT structure also includes a field stop region 190 of the second conductivity type, which is arranged between the collector region 120 and the drift region 110, and the doping concentration of the field stop region 190 is higher than the doping concentration of the drift region 110. The main function of the field stop region 190 is to terminate the electric field when the IGBT is turned off, to prevent the electric field from penetrating into the collector region 120, thereby improving the withstand voltage capability of the device. When a high voltage is applied, the field stop region 190 can withstand a part of the electric field, so that the electric field gradually weakens before reaching the collector region 120, thereby avoiding breakdown of the collector region 120. The field stop region 190 can also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. The reduction of the tail current helps to reduce the turn-off loss.

[0072] Please refer to the attached Figure 3-9 Attachment Figure 1 The manufacturing method of the semiconductor device shown in FIG. 1 is exemplarily described.

[0073] First, see the attached Figure 3 , providing a substrate 10 of a second conductivity type.

[0074] Then, see Appendix Figure 4, first pillars 11 and second pillars 12 are alternately formed on the substrate 10, and the first pillars 11 and the second pillars 12 are of the first conductivity type and the second conductivity type, respectively. Specifically, a groove can be etched on the substrate 10 at a position corresponding to the first pillar 11, and then the groove is filled with a material of the first conductivity type to form the first pillar 11. The remaining substrate 10 after etching forms the second pillar 12.

[0075] Then, see Appendix Figure 5 A first gate trench and a second gate trench are etched on the first pillar 11 and the second pillar 12 respectively.

[0076] Then, see Appendix Figure 6 , a dummy gate 160 and an active gate 130 are respectively formed in the first gate trench 13 and the second gate trench 14. Specifically, a first gate oxide layer and a second gate oxide layer can be respectively formed on the inner surfaces of the first gate trench 13 and the second gate trench 14 by a thermal oxidation process, and then polysilicon is respectively deposited in the first gate trench 13 and the second gate trench 14 to form a first polysilicon gate and a second polysilicon gate.

[0077] Then, see Appendix Figure 7 , firstly, doping ions of the first conductivity type are implanted on both sides of the active gate 130 at the upper part of the second pillar 12 to form a first doping region, and then doping ions of the second conductivity type are implanted on both sides of the upper part of the first doping region and the upper part of the first pillar 11 to form a second doping region 15. The part of the first pillar 11 and the part of the second pillar 12 that are not implanted with doping ions are the first pillar region 111 and the second pillar region 112, respectively, and the part of the first doping region between the second pillar region 112 and the second doping region 15 is the body region 140. The part of the first pillar region 111 facing the active gate 130 also realizes the function of the body region 140.

[0078] Then, see Appendix Figure 8 An insulating layer 200 is formed on the first emitter region 150, the active gate 130 and the dummy gate 160, and a contact hole 210 is etched in the insulating layer 200. Then, doping ions of the first conductive type are implanted in the contact hole 210 to form a second emitter region 170 in the second doping region 15. The portions of the second doping region 15 on both sides of the active gate 130 that are not implanted with doping ions constitute the first emitter region 150, and the portions of the second doping region 15 on both sides of the dummy gate 160 that are not implanted with doping ions constitute the doping region 180.

[0079] Then, see Appendix Fig. 9Metal is deposited on the insulating layer 200 and in the contact hole 210 to form an emitter metal 300. A field stop region 190, a collector region 120 and a collector metal 400 are sequentially formed at the lower side of the first stud region 111 and the second stud region 112.

[0080] The present application also provides a semiconductor device, which includes the IGBT structure described above. The semiconductor device may be a power semiconductor device.

[0081] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0083] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0084] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0085] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0086] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0087] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. An IGBT structure, characterized in that: include: A substrate (100), the substrate (100) having a first main surface (101) and a second main surface (102) on the opposite side of the first main surface (101), the first main surface (101) and the second main surface (102) being arranged at an interval in the vertical direction; A drift region (110), the drift region (110) being arranged between the first main surface (101) and the second main surface (102); A collector region (120) of a first conductivity type, the collector region (120) being arranged on a side of the drift region (110) facing the first main surface (101), and a side of the collector region (120) away from the drift region (110) constituting at least a portion of the first main surface (101); an active gate (130), the active gate (130) extending from the second main surface (102) toward the first main surface (101) into the drift region (110); A body region (140) of a first conductivity type, the body region (140) being arranged on a side of the drift region (110) facing the second main surface (102) and located on both sides of the active gate (130) in a horizontal direction; a first emitter region (150) of a second conductivity type, the first emitter region (150) being arranged on a side of the body region (140) facing the second main surface (102), and a side of the first emitter region (150) away from the body region (140) constituting a portion of the second main surface (102); a virtual gate (160), the virtual gate (160) extending from the second main surface (102) toward the first main surface (101) into the drift region (110); The drift region (110) comprises a first column region (111) of a first conductivity type and a second column region (112) of a second conductivity type, and the first column region (111) and the second column region (112) are alternately arranged in a horizontal direction; One end of the active gate (130) facing the first main surface (101) extends into the second column region (112), and one end of the dummy gate (160) facing the first main surface (101) extends into the first column region (111).

2. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a second emitter region (170) of the first conductivity type, wherein the second emitter region (170) is arranged in the first emitter region (150), and a side of the second emitter region (170) away from the first main surface (101) constitutes at least a part of the second main surface (102).

3. The IGBT structure according to claim 2, characterized in that: The IGBT structure further includes: An insulating layer (200), the insulating layer (200) being disposed on the second main surface (102), and a contact hole (210) being disposed in a portion of the insulating layer (200) corresponding to the second emission region (170); an emitter metal (300), the emitter metal (300) being disposed on a side of the insulating layer (200) away from the second main surface (102) and disposed in the contact hole (210), the emitter metal (300) being in contact with the second emitter region (170); A collector metal (400), wherein the collector metal (400) is provided on the first main surface (101).

4. The IGBT structure according to claim 3, characterized in that: The virtual gate (160) comprises a first gate trench extending from the second main surface (102) to the first main surface (101) to the first column region (111), a first gate dielectric layer located on the inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench; The first polysilicon gate is in contact with the emitter metal (300).

5. The IGBT structure according to claim 1, characterized in that: The virtual gate (160) comprises a first gate trench extending from the second main surface (102) to the first main surface (101) to the first column region (111), a first gate dielectric layer located on the inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench; The virtual gate (160) is a floating gate.

6. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a doped region (180) of a second conductivity type, wherein the doped region (180) is located on both sides of the virtual gate (160) in a horizontal direction and is in contact with the first emitter region (150), and a side of the doped region (180) away from the first main surface (101) constitutes at least a portion of the second main surface (102).

7. The IGBT structure according to claim 1, characterized in that: The IGBT structure further comprises a field stop region (190) of the second conductivity type, wherein the field stop region (190) is arranged between the collector region (120) and the drift region (110).

8. The IGBT structure according to claim 1, characterized in that: The active gate (130) comprises a second gate trench extending from the second main surface (102) to the first main surface (101) to the second column region (112), a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench.

9. The IGBT structure according to any one of claims 1 to 8, characterized in that: The first conductivity type is P type; The second conductivity type is N type.

10. A semiconductor device, characterized in that: The invention comprises the IGBT structure according to any one of claims 1 to 9.

Images