Method for manufacturing back-illuminated large-area-array photoelectric device based on local thinning method and photoelectric device
By forming a photosensitive region and a device edge support region on the silicon wafer through local thinning method, the problems of high fragmentation rate of large-surface back-illuminated photoelectric devices in the prior art are solved, and the manufacturing difficulty of ultraviolet-band response devices are achieved. Three-dimensional integration and thin photosensitive element back-illumination process improve process yield and device performance.
Patent Information
- Application Number
- CN202411361702.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2024-12-31
AI Technical Summary
The fragmentation rate of existing large-surface back-illuminated photoelectric devices is high, especially when manufacturing ultraviolet-band responsive devices, the thinning process is difficult and cannot be compatible with the three-dimensional integrated process, resulting in too thin device thickness and small response area.
The local thinning method is adopted to form a hard mask layer on the silicon wafer, expose the light to form a local thinning area, and etching to form a photosensitive area and a device edge support area. Combined with wet corrosion and other processes, it is made into a backlighting large Surface array optoelectronic devices.
It improves the yield of the backlighting process and is compatible with three-dimensional integrated processes, such as indium column re-welding and 3D packaging, reduces costs and realizes the thin photosensitive element backlighting process, solving the problems of device thickness and response area.
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Figure CN119230660A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor optoelectronic device technology, and in particular to a method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method and an optoelectronic device. Background Art
[0002] The current large-area back-illuminated optoelectronic devices are generally based on various bonding processes, such as adhesive bonding, silicon-silicon bonding, etc. The back-thinned detector generally thins the device to 100-200μm (determined by the response wavelength) and then performs back-illuminated related processes. The fragmentation rate of the array detector made in this way is more than 50%, which is too high. In addition, the back-illuminated thinned array detector process is difficult to thin the chip using existing technology due to the shallow absorption depth of the ultraviolet band. The thickness of the manufactured chip is too thin. Summary of the invention
[0003] In view of the above-mentioned shortcomings of the prior art, the present application provides a method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method and an optoelectronic device, which are used to solve at least one defect in the prior art.
[0004] To achieve the above-mentioned purpose and other purposes, the present application provides a method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method, comprising: providing a silicon wafer; forming a hard mask layer on the silicon wafer; exposing part of the hard mask layer by exposure to form a local thinning area; etching the local thinning area to form a photosensitive area and a device edge support area; and performing other processes on the photosensitive area and the device support area.
[0005] In one embodiment of the present invention, the step of exposing part of the hard mask layer by exposure to form a local thinning area includes: forming a photoresist layer on the surface of the hard mask layer away from the silicon wafer; exposing and developing the photoresist layer to form a developed area and a non-developed area, and using the developed area as the local thinning area, wherein the developed area exposes the hard mask layer.
[0006] In one embodiment of the present invention, the step of etching the local thinned area includes: etching the hard mask layer in the local thinned area to expose the silicon wafer; and performing deep silicon etching on the exposed silicon wafer to form a photosensitive area and a device edge support area.
[0007] In one embodiment of the present invention, before the step of forming a hard mask layer on the silicon wafer, the method further includes: thinning the silicon wafer, and the thickness of the silicon wafer after thinning is 350 μm.
[0008] In one embodiment of the present invention, the deep silicon etching adopts Bosch etching, the etching non-uniformity is less than 3%, and the side wall angle is greater than 88°.
[0009] In one embodiment of the present invention, the difference between the stress of the hard mask layer and the stress of the silicon wafer is within a preset range.
[0010] In one embodiment of the present invention, when etching the developing area, the depth of the thinning area is greater than 250μm; after etching the developing area, the width of the device edge support area is greater than 4mm, the thickness of the device edge support area is 350μm, and the remaining thickness of the thinning area is 35μm.
[0011] In one embodiment of the present invention, after the step of performing deep silicon etching on the developing area, the method further includes:
[0012] The photosensitive area is wet-etched; when the silicon wafer is an epitaxial wafer, the wet etching is a self-stop etching, and the etching stops at the epitaxial layer; when the silicon wafer is a single crystal silicon wafer, the surface etching defects generated by etching the thinned area are compounded by wet etching.
[0013] In one embodiment of the present invention, if the silicon wafer is an epitaxial wafer, the thickness of the epitaxial layer of the silicon wafer is greater than 20 μm, and the resistivity of the substrate is less than 0.02 Ω.cm.
[0014] In order to achieve the above-mentioned purpose and other purposes, the present application provides a back-illuminated large-area array optoelectronic device, which is manufactured using the manufacturing method of the back-illuminated large-area array optoelectronic device.
[0015] Beneficial effects of this application:
[0016] The present application discloses a method for manufacturing a large-area back-illuminated optoelectronic device based on a local thinning method, comprising: providing a silicon wafer; forming a hard mask layer on the silicon wafer; exposing part of the hard mask layer by exposure to form a local thinning area; etching the local thinning area to form a photosensitive area and a device edge support area; and performing other processes on the photosensitive area and the device support area. The large-area back-illuminated optoelectronic device manufactured by the above method can be perfectly compatible with most three-dimensional integration processes, such as indium column reverse soldering, 3D packaging, etc., and can also enable some detectors to realize a thin photosensitive element back-illuminated process; and greatly improve the back-illuminated process yield.
[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0019] Figure 1 It is a schematic diagram of the structure of a back-illuminated optoelectronic device realized by bonding in the prior art;
[0020] Figure 2 This is a flow chart of a method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to an embodiment of the present application;
[0021] Figure 3 It is a schematic structural diagram of an optoelectronic device manufactured by a method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to an embodiment of the present application. DETAILED DESCRIPTION
[0022] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0023] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0024] Although the terms "first", "second", "A", and "B", etc. may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the following technology. The term "and / or" includes a combination of multiple related items or any of the multiple related items.
[0025] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.
[0026] Before the detailed description, it is intended to clarify that the division of components in this specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main function of the component, each component to be described below can also perform some or all of the functions of other components, and some of the main functions of each component can be exclusively performed by other components.
[0027] The current large-area back-illuminated optoelectronic devices are generally developed based on various bonding processes, such as adhesive bonding, silicon-silicon bonding, etc. Among them, the schematic diagram of the structure of the back-illuminated optoelectronic device realized by bonding is as follows: Figure 1 As shown, the device is composed of a support sheet 140, a bonding medium 130 (generally bonding glue, silicon dioxide, etc.), a front circuit structure 120 of the optoelectronic device, and a back-illuminated surface 110 of the epitaxial layer of the optoelectronic device from bottom to top. However, the optoelectronic device developed based on the bonding process has the following disadvantages: 1. The circuit layer of the bonding process is inside the device, and the subsequent front process cannot be performed after the device is completed; 2. Due to the presence of the bonding medium, the bonding sheet cannot be subjected to high-temperature processes, and processes above 200°C generally cause internal damage to the bonding sheet; 3. The device fragmentation rate of the back-illuminated thinned array detector process (thickness 100-200μm) is very high, generally >50%; 4. It is difficult to manufacture ultraviolet band response devices with the back-illuminated thinned array detector process, because the absorption depth of the ultraviolet band is shallow, and if a general thinning process is used, the chip thickness is too thin; 5. The area of the photosensitive element that can be manufactured with the back-illuminated thinned array detector process is small. Therefore, it is difficult to carry out three-dimensional integrated production of existing large-array high-resolution back-illuminated optoelectronic devices on the existing basis, such as integrating signal acquisition optoelectronic devices and signal processing CMOS devices to complete module miniaturization.
[0028] In view of the defects of optoelectronic devices made by bonding process, the present application provides a method for manufacturing back-illuminated large-area optoelectronic devices based on local thinning method. Through this method, after the device is completed, only the photosensitive area is thinned, and the periphery is used as the mechanical support area and wiring area to avoid the above problems.
[0029] See also Figure 2 , Figure 2 This is a flow chart of a method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to an embodiment of the present application. Figure 2As shown, a method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method comprises:
[0030] Step S210, providing a silicon wafer 310;
[0031] It should be noted that the silicon wafer 310 may be an epitaxial wafer or a single crystal silicon wafer.
[0032] It should also be noted that different devices select different silicon wafers and have different requirements. For CCD devices, epitaxial wafers need to be selected as silicon wafers. If the silicon wafer is an epitaxial wafer, the silicon wafer includes an epitaxial layer and a silicon substrate, the thickness of the epitaxial layer is greater than 20μm, and the resistivity of the substrate is less than 0.02Ω.cm.
[0033] Step S220, forming a hard mask layer 3101 on the silicon wafer 310;
[0034] Specifically, the step of forming the hard mask layer 3101 on the silicon wafer 310 includes: growing silicon dioxide on the silicon wafer 310 as the hard mask layer 3101 , and the thickness of the hard mask layer 3101 is 3 μm.
[0035] It should be noted that the hard mask layer 3101 includes a first surface and a second surface, the first surface is above the second surface, and the first surface and the second surface are arranged parallel to each other.
[0036] The hard mask layer 3101 is formed on the silicon wafer 310, the surface in contact with the silicon wafer 310 is the second surface, and the first surface is the surface away from the silicon wafer 310. That is, the photoresist layer 3102 is formed on the first surface of the hard mask layer 3101.
[0037] In the embodiment of the present application, before the step of forming a hard mask layer on the silicon wafer, the method further includes: thinning the silicon wafer, and the thickness of the silicon wafer after thinning is about 350 μm.
[0038] Step S230, exposing a portion of the hard mask layer by exposure to form a local thinning area;
[0039] In an embodiment of the present application, the step of exposing a portion of the hard mask layer by exposure to form a local thinning area includes:
[0040] Step S2301, forming a photoresist layer 3102 on a surface of the hard mask layer 3101 away from the silicon wafer;
[0041] It should be noted that the thickness of the photoresist layer generally needs to be greater than 6 μm.
[0042] Step S2302 , exposing and developing the photoresist layer 3102 to form a developed area and a non-developed area, and using the developed area as a local thinning area 330 , wherein the developed area exposes the hard mask layer.
[0043] The exposure and development of the photoresist layer 3102 can be achieved by a double-sided photolithography machine, and the alignment mark uses the device front side mark.
[0044] When the photolithography machine processes the photoresist layer 3102, the pattern on the mask is transferred to the hard mask coated with photoresist, and then exposure, development and other processing processes are performed to obtain an accurate replication of the mask pattern in the photoresist, thereby forming a local thinning area 330 by exposure.
[0045] Step S240, etching the local thinned area to form a photosensitive area 340 and a device edge support area 350;
[0046] In an embodiment of the present application, the step of etching the local thinning area includes:
[0047] Step S2401, etching the hard mask layer in the local thinning area to expose the silicon wafer;
[0048] Step S2402 , performing deep silicon etching on the exposed silicon wafer to form a photosensitive area 330 and a device edge support area 340 .
[0049] In the embodiment of the present application, when deep silicon etching is performed, the depth of deep silicon etching is determined by the device requirements, generally between 200-300 μm. The deep silicon etcher adopts Bosch etching, the etching non-uniformity is less than 3%, and the side wall angle is greater than 88°. By controlling the above parameters, the uniformity and yield rate of the photosensitive element response can be improved.
[0050] It should be noted that in order to reduce etching defects generated during deep silicon etching, it is necessary to keep the stress difference between the hard mask layer and the silicon wafer within a preset range, that is, to ensure that the stress difference between the hard mask layer and the silicon wafer is not large, otherwise the silicon wafer may be easily damaged.
[0051] In an embodiment of the present application, when etching the local thinning area, the depth of the thinning area is greater than 250μm; after etching the local thinning area, the width of the device edge support area is greater than 4mm, the thickness of the device edge support area is 350μm, and the remaining thickness of the thinning area is 35μm.
[0052] The width of the device edge support area is greater than 4mm, which can ensure the mechanical strength of the device and thus meet the impact and stress changes brought about by the three-dimensional integration of the device.
[0053] In an embodiment of the present application, after the step of performing deep silicon etching on the developing area, the method further includes: performing wet etching on the photosensitive area; when the silicon wafer is an epitaxial wafer, the wet etching is a self-stop etching, and the etching is stopped at the epitaxial layer; when the silicon wafer is a single crystal silicon wafer, the surface etching defects generated by etching the thinned area are compounded by wet etching.
[0054] It should be noted that before wet etching the photosensitive area, the front side of the silicon wafer needs to be protected. Specifically, the front side of the silicon wafer is generally protected by film protection, and of course other protection methods can also be used, which will not be described here.
[0055] Wet etching has different purposes depending on the silicon wafer. If the silicon wafer is an epitaxial wafer, the wet etching is a self-stopping etching, and the etching stops at the epitaxial layer; if the silicon wafer is a single crystal silicon wafer, the purpose of wet etching is mainly to reduce the dark current of the device, and wet etching is used to compound surface etching defects.
[0056] When performing wet etching, the main components of the etching solution used are hydrofluoric acid, nitric acid and glacial acetic acid.
[0057] It should be noted that different devices may use different silicon wafers, so the requirements for etching solutions are different. Different silicon wafers need to use etching solutions with different proportions. For detectors, the silicon wafer is single crystal silicon, so the hydrofluoric acid in the etching solution needs to be increased in proportion. The specific proportion can be selected according to the machine.
[0058] It should also be noted that the local thinning of devices cannot include processes that cause vibration, such as flushing and drying, and must be carried out using overflow and vacuum drying.
[0059] Step S250, performing other processes on the photosensitive area and the device supporting area.
[0060] This step is also determined according to the type and needs of the device. Generally, it is the production of anti-reflection film 360. If necessary, it can also be produced by processes such as through-hole or back pressure point. It should be noted that the production of high-temperature processes such as anti-reflection film and alloy requires a temperature of ≤300℃.
[0061] At this point, the optoelectronic device is completed. Its specific structure can be referred to Figure 3 . Subsequently, three-dimensional integration or multi-device splicing can be carried out as needed.
[0062] In summary, the present application sets a silicon wafer; forms a hard mask layer on the silicon wafer; exposes part of the hard mask layer by exposure to form a local thinning area; etches the local thinning area to form a photosensitive area and a device edge support area; performs other processes on the photosensitive area and the device support area; through the above steps, not only can the large-area back-illuminated optoelectronic device be perfectly compatible with most three-dimensional integration processes, such as indium column reverse soldering, 3D packaging, etc., but also some detectors can realize the thin photosensitive element back-illuminated process. At the same time, it also greatly improves the back-illuminated process yield, shortens the back-illuminated production cycle, and reduces costs; the optoelectronic device made by this method can be used as a final product or as an intermediate product, which improves the process flexibility.
[0063] The present application provides a back-illuminated large-area array optoelectronic device, which is manufactured using the manufacturing method of the back-illuminated large-area array optoelectronic device of the aforementioned embodiment.
[0064] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.
Claims
1. A method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method, characterized in that: include: Disposing a silicon wafer; forming a hard mask layer on the silicon wafer; Exposing a portion of the hard mask layer by exposure to form a local thinning area; Etching the local thinned area to form a photosensitive area and a device edge support area; Other processes are performed on the photosensitive area and the device supporting area.
2. The method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to claim 1, characterized in that: The step of exposing a portion of the hard mask layer by exposure to form a local thinning area includes: forming a photoresist layer on a surface of the hard mask layer away from the silicon wafer; The photoresist layer is exposed and developed to form a development area and a non-development area, and the development area is used as a local thinning area, wherein the development area exposes the hard mask layer.
3. The method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to claim 1, characterized in that: The step of etching the developing area comprises: Etching the hard mask layer in the local thinned area to expose the silicon wafer; The exposed silicon wafer is subjected to deep silicon etching to form a photosensitive area and a device edge support area.
4. The method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to claim 1, characterized in that: Before the step of forming a hard mask layer on the silicon wafer, the method further includes: thinning the silicon wafer, and the thickness of the silicon wafer after thinning is 350 μm.
5. The method for manufacturing a back-illuminated large-area array optoelectronic device according to claim 1, characterized in that: The deep silicon etching adopts Bosch etching, the etching non-uniformity is less than 3%, and the side wall angle is greater than 88°.
6. The method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to claim 1, characterized in that: The difference between the stress of the hard mask layer and the stress of the silicon wafer is within a preset range.
7. The method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to claim 1, characterized in that: When etching the local thinning area, the depth of the thinning area is greater than 250μm; after etching the local thinning area, the width of the device edge support area is greater than 4mm, the thickness of the device edge support area is 350μm, and the remaining thickness of the thinning area is 35μm.
8. The method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to claim 1, characterized in that: After the step of performing deep silicon etching on the developing area, the method further comprises: Performing wet etching on the photosensitive area; When the silicon wafer is an epitaxial wafer, the wet etching is a self-stop etching, and the etching stops at the epitaxial layer; When the silicon wafer is a single crystal silicon wafer, the surface etching defects generated by etching the thinned area are compounded by wet etching.
9. The method for manufacturing a back-illuminated large-area array optoelectronic device based on a local thinning method according to claim 1 or 8, characterized in that: If the silicon wafer is an epitaxial wafer, the thickness of the epitaxial layer of the silicon wafer is greater than 20 μm, and the resistivity of the substrate is less than 0.02 Ω.cm.
10. A back-illuminated large-area array optoelectronic device, characterized in that: The method is produced according to any one of claims 1 to 9.