TBC battery and preparation method thereof

Abstract

The invention discloses a TBC battery and a preparation method thereof. The method comprises the following steps: providing an N-type silicon substrate; the N-type silicon substrate comprises a front surface and a back surface, and the back surface comprises first regions and second regions which are alternately arranged in an interdigital manner; preparing a first tunneling oxide layer, a first doping layer and a first protection layer in the first region by using a preset high-temperature condition; preparing a second tunneling oxide layer, a second doping layer and a second protection layer in the second region; performing front surface texturing on the front surface, and preparing a third protective layer on the front surface; and performing silk-screen printing and high-temperature sintering on the first region and the second region to form a first electrode in contact with the first doping layer on the surface of one side, deviating from the N-type silicon substrate, of the first protection layer and form a second electrode in contact with the second doping layer on the surface of one side, deviating from the N-type silicon substrate, of the second protection layer, so as to prepare the TBC battery. By utilizing the method, high-temperature top-speed doping of the first region is realized, the preparation time of the battery is shortened, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a TBC cell and a preparation method thereof. Background Art

[0002] The renewal and iteration of photovoltaic cell structure has led to the continuous accumulation of old production capacity, and cost reduction and efficiency improvement have become the key issues of the photovoltaic industry. Compared with P-type crystalline silicon cells, N-type crystalline silicon cells have a long minority carrier lifetime, no photoinduced degradation, good weak light effect, and a small temperature coefficient. They are the hope for crystalline silicon solar cells to break through the theoretical maximum efficiency. TBC cells are crystalline silicon solar cells with a back contact structure. They use P+ and N+ Poly-Si as the emitter and back surface field (Back Surface Field, BSF) respectively. They are solar cells that deposit a tunneling oxide layer between Poly-Si and the silicon substrate to increase the selectivity of carriers, reduce the recombination of minority carriers, and increase the open circuit voltage of the cell. The light-receiving surface of the cell is not blocked by any metal grid lines, that is, the light-receiving surface has no electrode, so that the light incident on the cell surface can be used to a greater extent. At the same time, the back side (non-light-receiving surface) can allow wider metal grid lines to reduce the series resistance and thus improve the fill factor, plus the open circuit voltage gain brought by the front surface field of the cell and the excellent passivation effect, thereby improving the cell conversion efficiency.

[0003] The existing preparation of the P-region polysilicon layer of the TBC battery with an N-type silicon substrate generally adopts a uniform emitter, which results in a lower doping temperature of the P-region polysilicon layer. In order to avoid the breakdown of the doping source through the tunneling oxide layer, the polysilicon layer deposited in the P-region is usually thicker. However, the thicker polysilicon layer will cause the doping concentration of the P-region polysilicon layer to be low, reducing the open circuit voltage of the battery and reducing the conversion efficiency of the TBC battery. Summary of the invention

[0004] The present invention provides a TBC battery and a preparation method thereof, which utilizes an ultra-high temperature doping temperature to increase the doping concentration of a first doping layer, improve the passivation effect, and further improve the open circuit voltage and conversion efficiency of the TBC battery.

[0005] In a first aspect, the present invention provides a method for preparing a TBC battery, comprising:

[0006] An N-type silicon substrate is provided; the N-type silicon substrate comprises a front surface and a back surface, and the back surface comprises a first region and a second region alternately arranged in an interdigitated shape;

[0007] Using a preset high temperature condition, a first tunneling oxide layer and a first doping layer are prepared in a first region;

[0008] forming a second tunneling oxide layer and a second doping layer in the second region;

[0009] Performing front texturing on the front side, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing;

[0010] The first region and the second region are screen printed and sintered at high temperature to form a first electrode in contact with the first doping layer in the first region and a second electrode in contact with the second doping layer in the second region, thereby manufacturing a TBC battery.

[0011] Optionally, using a preset high temperature condition, preparing a first tunneling oxide layer and a first doping layer in the first region includes:

[0012] Using a deposition process, preparing a first tunneling oxide layer and a first intrinsic silicon layer in the first region and the second region;

[0013] The boron diffusion process is adopted to dope the N-type silicon substrate forming the first intrinsic silicon layer with boron under a preset high temperature condition to form a first doped layer.

[0014] Optionally, a boron diffusion process is used to boron-dope the N-type silicon substrate forming the first intrinsic silicon layer under a preset high temperature condition to form a first doped layer, including:

[0015] The first doping layer is formed by using a tubular diffusion device and a boron diffusion process to perform boron doping on an N-type silicon substrate forming a first intrinsic silicon layer under a preset high temperature condition.

[0016] Optionally, the preset high temperature condition T satisfies: T>1000°C.

[0017] Optionally, the time for forming the first doping layer is a preset time, and the preset time t satisfies: 30min≤t≤40min.

[0018] Optionally, the thickness h of the first doping layer satisfies: 250 nm ≤ h ≤ 380 nm; and / or the concentration n of the first doping layer satisfies: n>7e19 cm-3.

[0019] Optionally, the reaction chamber of the tube diffusion device is used to introduce boron trichloride and oxygen, and the ratio m between the flow rate of the introduced boron trichloride and the flow rate of the introduced oxygen satisfies: 1:2.5≤m≤1:3.

[0020] Optionally, the sheet resistance of the first doped layer is 90Ω / sq-130Ω / sq.

[0021] Optionally, a boron diffusion process is used to dope the N-type silicon substrate forming the first intrinsic silicon layer with boron under a preset high temperature condition, and after the first doped layer is formed, the method further includes:

[0022] Forming a first mask layer on the front side and the first doped layer surface away from the N-type silicon substrate;

[0023] Removing the first mask layer, the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region;

[0024] Preparing a second tunneling oxide layer and a second doping layer in the second region includes:

[0025] Using a deposition process, a second tunneling oxide layer and a second intrinsic silicon layer are formed on the exposed second region of the N-type silicon substrate and the surface of the first mask layer on a side away from the N-type silicon substrate;

[0026] The phosphorus diffusion process is adopted to dope the N-type silicon substrate forming the second intrinsic silicon layer with phosphorus to form a second doped layer.

[0027] Optionally, after phosphorus diffusion process is used to dope the N-type silicon substrate forming the second intrinsic silicon layer with phosphorus, and the second doped layer is formed, the method further includes:

[0028] Forming a second mask layer on the front surface and on the surface of the second doped layer on one side away from the N-type silicon substrate;

[0029] The second mask layer, the second doping layer and the second tunneling oxide layer in the first region are removed.

[0030] Optionally, performing front texturing on the front side, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing, including:

[0031] removing the first mask layer and the second mask layer deposited on the front side;

[0032] The velvet making process is adopted to make velvet on the front side to form a velvet structure;

[0033] removing the first mask layer in the first area and the second mask layer in the second area;

[0034] A deposition process is used to prepare a first protective layer on the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and a second protective layer is prepared on the surface of the suede structure on the side away from the N-type silicon substrate.

[0035] Optionally, before preparing the first tunnel oxide layer and the first doping layer in the first region under a preset high temperature condition, the method further includes:

[0036] The front and back sides of the N-type silicon substrate are double-sided polished.

[0037] In a second aspect, the present invention provides a TBC battery, which is manufactured using the above-mentioned TBC battery manufacturing method.

[0038] The technical solution of the present invention is to provide an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side, and the back side includes a first region and a second region arranged alternately in a forked shape; using a preset high temperature condition, a first tunneling oxide layer and a first doping layer are prepared in the first region; a second tunneling oxide layer and a second doping layer are prepared in the second region; a front surface is textured on the front side, and a first protective layer is prepared on the surface of the first doping layer and the second doping layer on the back side away from the N-type silicon substrate, and a second protective layer is prepared on the front side after the front surface is textured; screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, so as to prepare a TBC battery. Through the above method, the doping temperature under the preset high temperature condition is used to increase the doping concentration of the first doping layer, improve the passivation effect, and thus improve the open circuit voltage and conversion efficiency of the TBC battery.

[0039] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A flow chart of a method for preparing a TBC battery provided by an embodiment of the present invention;

[0042] Figure 2 A schematic diagram of the structure of a TBC battery provided by an embodiment of the present invention;

[0043] Figure 3 A flow chart of a method for preparing a second TBC battery provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, preparation method, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] In one embodiment, Figure 1 A flowchart of a method for preparing a TBC battery provided by an embodiment of the present invention, Figure 2 Schematic diagram of the structure of a TBC battery provided by an embodiment of the present invention. This embodiment is applicable to the case where the doping temperature and doping concentration of the first doping layer formed in the first region are low, such as Figure 1 and Figure 2 As shown, the method includes:

[0047] S110 , providing an N-type silicon substrate.

[0048] Among them, the N-type silicon substrate 1 includes a front side and a back side, and the back side includes a first region and a second region alternately arranged in a forked shape. Usually, the first region may be an n region or a p region, and correspondingly, the second region may be a p region or an n region. In this embodiment, the first region may be a p region. The resistivity range of the N-type silicon substrate 1 is 1Ωcm-18Ωcm. Exemplarily, the resistivity of the N-type silicon substrate 1 may be 1Ωcm, 5Ωcm, 10Ωcm, 15Ωcm or 18Ωcm, etc., which can be determined according to actual conditions and is not limited here.

[0049] S120, preparing a first tunneling oxide layer and a first doping layer in the first region using a preset high temperature condition.

[0050] The first tunneling oxide layer 21 is used to allow the majority carriers (electrons) to pass smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes), so as to achieve selective collection of carriers, reduce surface recombination, and increase the open circuit voltage and fill factor of the battery, thereby improving the photoelectric conversion efficiency of the TBC battery. The first doping layer 22 is a boron-doped polysilicon layer, which is a special semiconductor layer with a high doping concentration formed by doping boron elements.

[0051] Specifically, a deposition process is used to sequentially deposit a first tunneling oxide layer 21 and a first intrinsic silicon layer in a first region. After the first intrinsic silicon layer is formed, the first intrinsic silicon layer needs to be doped with elements to form a first doped layer 22 after the first intrinsic silicon layer is doped. In this process, a preset high temperature condition needs to be used, wherein the preset high temperature condition is greater than 1000°C. By doping the first intrinsic silicon layer in an ultra-high temperature environment, a highly concentrated doped first doped layer 22 can be obtained in a very short time, thereby improving the passivation effect and the open circuit voltage and conversion efficiency of the TBC battery.

[0052] S130, preparing a second tunneling oxide layer and a second doping layer in the second region.

[0053] The second tunneling oxide layer 31 is used to allow the majority carriers (electrons) to pass smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes), so as to achieve selective collection of carriers, reduce surface recombination, and increase the open circuit voltage and fill factor of the battery, thereby improving the photoelectric conversion efficiency of the TBC battery. The second doping layer 32 is a phosphorus-doped polysilicon layer, which is a special semiconductor layer with a high doping concentration formed by doping phosphorus.

[0054] Specifically, the second tunnel oxide layer 31 and the second intrinsic silicon layer are prepared by deposition and other processes in the second region, and the second intrinsic silicon layer is doped with elements so that the elements diffuse into the second intrinsic silicon layer to form the second doped layer 32. The deposition to form the second tunnel oxide layer 31 and the second intrinsic silicon layer includes but is not limited to low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or physical vapor deposition, etc., which can be determined according to actual conditions and are not limited here.

[0055] S140, performing front texturing on the front side, preparing a first protective layer on the surface of the first doping layer and the second doping layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing.

[0056] Among them, front texturing refers to the special treatment of the front surface of the N-type silicon substrate 1 of the TBC cell during the production process of the TBC cell to form a rough, velvet-like structure. The first protective layer and the second protective layer both include a passivation layer and an anti-reflection layer, which are used to reduce the reflection of sunlight, increase the absorption of sunlight, improve the conversion efficiency of the TBC cell, reduce surface recombination, increase the mobility of carriers, and improve the overall performance of the TBC cell.

[0057] Specifically, a texturing process is used to perform texturing on the front side of the N-type silicon substrate 1 to form a front velvet structure. After the front texturing is completed, a first protective layer 4 needs to be prepared on the surface of the first doping layer 22 and the second doping layer 32 on the back side away from the N-type silicon substrate 1. Specifically, it can be prepared and formed by deposition and other processes, which are not limited here. In addition, it is also necessary to prepare a second protective layer 5 on the front surface after the front texturing to reduce the surface reflection of the TBC battery, increase the surface area of ​​the TBC battery, and reduce the reflection of sunlight, improve the light trapping effect of the battery and the absorption rate of sunlight, generate more photogenerated carriers, and improve the conversion efficiency of the TBC battery. The texturing process may include but is not limited to trough texturing and other processes. The process for preparing the first protective layer 4 and the second protective layer 5 includes but is not limited to low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition or physical vapor deposition, etc., which can be determined according to actual conditions and are not limited here.

[0058] In an optional embodiment, a trough texturing process is used to texturize the front surface in a preset alkaline solution to form a front velvet structure. The preset alkaline solution may be an alkaline solution formed by a sodium hydroxide solution with a concentration of 0.5%-3% and a texturing additive in a preset ratio.

[0059] S150, screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, to manufacture a TBC battery.

[0060] Among them, screen printing is one of the core processes in the manufacturing process of TBC battery cells, and is mainly used for electrode forming of TBC batteries. This process uses the basic principle that the mesh holes of the graphic part of the screen are transparent to the slurry, and the mesh holes of the non-graphic part are not transparent to the slurry for printing. During the printing process, the slurry is accurately squeezed onto the N-type silicon substrate 1 through the mesh holes of the screen to form the required electrode pattern. Generally, the slurry for screen printing can include but is not limited to silver paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed on the surface of the battery cell at high temperature so that the metal grid lines form a good ohmic contact with the N-type silicon substrate 1.

[0061] Specifically, after forming the first protective layer 4 on the back, it is necessary to form an electrode on the back so that the photogenerated carriers generated by the solar energy are converted into current and then flow to the external circuit. In this embodiment, the first and second regions on the back are screen printed so that metal grid lines are formed on the surfaces of the first and second regions. After forming the metal grid lines, the formed metal grid lines need to be sintered at high temperature so that the metal grid lines after high temperature sintering can contact the first doping layer 22 and the second doping layer 32 to form an ohmic contact. Specifically, after high temperature sintering, a first electrode 6 in contact with the first doping layer 22 is formed in the first region, and a second electrode 7 in contact with the second doping layer 32 is formed in the second region, thereby preparing a TBC battery. In addition, the polarities of the first electrode 6 and the second electrode 7 are opposite. When the first electrode 6 is a positive electrode, the corresponding second electrode 7 is a negative electrode; when the first electrode 6 is a negative electrode, the corresponding second electrode 7 is a positive electrode. In this embodiment, the first region is a p region, the second region is an n region, and the corresponding first electrode 6 formed in the p region is a positive electrode, and the second electrode 7 formed in the n region is a negative electrode.

[0062] The technical solution of the present invention is to provide an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side, and the back side includes a first region and a second region arranged alternately in a forked shape; using a preset high temperature condition, a first tunneling oxide layer and a first doping layer are prepared in the first region; a second tunneling oxide layer and a second doping layer are prepared in the second region; a front surface is textured on the front side, and a first protective layer is prepared on the surface of the first doping layer and the second doping layer on the back side away from the N-type silicon substrate, and a second protective layer is prepared on the front side after the front surface is textured; screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, so as to prepare a TBC battery. Through the above method, the doping temperature under the preset high temperature condition is used to increase the doping concentration of the first doping layer, improve the passivation effect, and thus improve the open circuit voltage and conversion efficiency of the TBC battery.

[0063] Optionally, before S120, using preset high temperature conditions, preparing the first tunneling oxide layer 21 and the first doping layer 22 in the first region, it also includes: double-sided polishing the front and back sides of the N-type silicon substrate 1 to remove mechanical damage layers, dirt, i.e., oil stains, etc. on the front and back sides to ensure the flatness and neatness of the surface of the N-type silicon substrate 1.

[0064] Figure 3 This is a flow chart of a second method for preparing a TBC battery provided by an embodiment of the present invention. This embodiment refines the method for preparing a TBC battery of the above embodiment. For the contents not yet fully described in this embodiment, please refer to the above embodiment, and no further description will be given here. Figure 2 and Figure 3 As shown, the method includes:

[0065] S210 , providing an N-type silicon substrate.

[0066] S211 , preparing a first tunneling oxide layer and a first intrinsic silicon layer in the first region and the second region by using a deposition process.

[0067] The deposition process includes low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, etc., which can be determined according to the specific situation and are not limited here. The first intrinsic silicon layer is a silicon material layer with intrinsic semiconductor properties. Intrinsic semiconductors refer to semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs in the material itself.

[0068] Specifically, by using a deposition process, such as a low-pressure chemical vapor deposition process, a certain flow rate of oxygen is introduced into the reaction chamber of the deposition process, and an ultra-thin first tunnel oxide layer 21 can be deposited in the first region and the second region, and the thickness of the formed first tunnel oxide layer 21 is 0.1nm-2nm. After the first tunnel oxide layer 21 is formed, a certain flow rate of silane is introduced into the reaction chamber of the deposition process, for example, the flow rate is 100sccm-400sccm, and at a preset deposition temperature, a first intrinsic silicon layer is deposited on the surface of the first tunnel oxide layer 21 away from the N-type silicon substrate 1, and the thickness of the first intrinsic silicon layer is 50nm-280nm.

[0069] S212, using a boron diffusion process to perform boron doping on the N-type silicon substrate forming the first intrinsic silicon layer under a preset high temperature condition to form a first doped layer.

[0070] S213, preparing a first mask layer on the front surface and on the surface of the first doped layer facing away from the N-type silicon substrate.

[0071] Among them, step S212 can be refined as follows: using tubular diffusion equipment and adopting a boron diffusion process to boron-dope the N-type silicon substrate forming the first intrinsic silicon layer under preset high temperature conditions to form a first doped layer.

[0072] Among them, the tubular diffusion equipment is an important equipment used in semiconductor manufacturing to achieve key process steps such as oxidation, diffusion, and annealing. The tubular diffusion equipment also plays an important role in the production of solar cells, and is used to form a uniform high-quality pn junction on the surface of the N-type silicon substrate 1. In this embodiment, the tubular diffusion equipment can achieve the temperature in the diffusion reaction chamber to reach a preset high temperature condition during the boron diffusion process to form a first doping layer 22 with a high doping concentration. The boron diffusion process is a doping technology used to introduce boron atoms into the first intrinsic silicon layer to form a P-type doping region.

[0073] Specifically, boron trichloride and oxygen are introduced into the reaction chamber of the tubular diffusion device, and the flow rate of the introduced boron trichloride and the flow rate of oxygen are set to be between 1:2.5-1:3, and the diffusion temperature, that is, the preset high temperature condition T is set to T>1000°C. Under the diffusion condition, a layer of boron is deposited at low temperature on the surface of the first intrinsic silicon layer away from the N-type silicon substrate 1 by using the chemical reaction between boron trichloride, oxygen and the first intrinsic silicon layer. After the boron is deposited, the boron is pushed at high temperature to make the boron doping diffuse into the first intrinsic silicon layer to form the first doping layer 22. In this process, the time for forming the first doping layer 22, that is, the preset time t satisfies 30min≤t≤40min, and the square resistance of the formed first doping layer 22 is 90Ω / sq-130Ω / sq. The concentration of the first doping layer 22 can be determined by the square resistance of the first doping layer. In this embodiment, the concentration of the first doping layer 22 is n>7e19cm-3. After high-temperature doping to form the first doping layer 22, the boron in the doping process usually does not completely react to enter the first intrinsic silicon layer, and a certain amount of residual organic matter will be generated during the reaction. In order to prevent the residual organic matter from affecting the first doping layer 22, the residual organic matter can be post-oxidized by introducing a certain flow rate of oxygen into the post-oxidation reaction chamber so that the residual organic matter reacts with oxygen to form a first mask layer. Usually, the first mask layer is a borosilicate glass layer.

[0074] It is understandable that the equipment for the boron diffusion process includes but is not limited to a boron diffusion furnace. When boron diffusion is performed in the equipment, double-sided diffusion is usually performed, or the N-type silicon substrate 1 is subjected to boron diffusion in a double-insertion manner. In this process, it cannot be guaranteed that the borosilicate glass layer produced by post-oxidation is only formed on the back side of the N-type silicon substrate 1. In the actual production process, the borosilicate glass layer will also be generated on the front side at the same time.

[0075] S214, removing the first mask layer, the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region.

[0076] Among them, this step can be refined as follows: using laser technology to pattern the back side to remove the first mask layer in the second area and retain the first mask layer in the first area; using an alkaline etching process to remove the first doping layer 22 in the second area; using an acid etching process to remove the first tunneling oxide layer 21 in the second area to expose the N-type silicon substrate 1.

[0077] Among them, the laser technology is a process of using a laser to remove the first mask layer of the second area on the back side according to a preset pattern. The alkaline etching process is a process of using a configured alkaline solution to chemically react with the first doping layer 22 to remove the first doping layer 22. The acid etching process, i.e., chain acid etching, is a wet etching technology widely used in the field of solar cell manufacturing, which mainly involves using a configured acidic solution to chemically treat the surface of the silicon wafer to achieve the purpose of removing a specific material layer or forming a specific structure.

[0078] Specifically, since the first tunneling oxide layer 21 and the first doping layer 22 are formed by full-surface deposition and diffusion on the back side, and the back side of the TBC battery needs to be provided with two interdigitated first and second regions for forming electrodes, it is necessary to remove the first mask layer, the first doping layer 22 and the first tunneling oxide layer 21 formed in the second region. In this embodiment, the output power of the laser is set to 1W-500W, and the laser frequency is set to 100kHz-1000kHz. The picosecond laser emitted under this condition is used to pattern the back side of the N-type silicon substrate 1, and the first mask layer in the second region is removed. At this time, the first doping layer 22 in the second region is exposed, and the width caused by laser bombardment is 90um-220um. Secondly, an alkaline solution such as sodium hydroxide or potassium hydroxide with a mass ratio of 5%-10% is introduced into the reaction chamber of the alkaline etching process, and an etching additive is added to configure the alkaline solution and the etching additive in a first preset ratio. The configured alkaline solution is used to remove the first doping layer 22 in the second region through a chemical reaction between the alkaline solution and the first doping layer 22 under certain etching temperature and etching time conditions, thereby exposing the first tunneling oxide layer 21 in the second region. After removing the first doping layer 22, an acid etching process is used to set an acidic solution such as hydrofluoric acid, and the concentration of the hydrofluoric acid is set in a certain range, such as 5%-30%. The hydrofluoric acid will react chemically with the first tunneling oxide layer 21 to remove the first tunneling oxide layer 21 in the second region, thereby exposing the N-type silicon substrate 1 in the second region. It can be understood that in order to reduce the battery preparation time, the removal of the first doping layer 22 and the first tunneling oxide layer 21 can be etched and removed in different tanks in the tank cleaning equipment.

[0079] S215 , using a deposition process, preparing a second tunneling oxide layer and a second intrinsic silicon layer on the surface of the N-type silicon substrate in the exposed second region and the first mask layer on a side away from the N-type silicon substrate.

[0080] The second intrinsic silicon layer has the same meaning as the first intrinsic silicon layer, and reference may be made to the above description, which will not be repeated here.

[0081] Specifically, after the N-type silicon substrate 1 in the second region is exposed, a deposition process can be used to introduce nitrogen oxide gas with a flow rate of 20 slm and an introduction time of 40s-90s into the reaction chamber of the deposition process, and a second tunneling oxide layer 31 with a thickness of 1nm-2nm is deposited on the first region and the second region on the back side of the N-type silicon substrate 1 under the conditions of a deposition temperature of 370°C-470°C, a deposition pressure of 100pa-400pa, and a deposition power of 0.6kW-1.2kW. After the second tunneling oxide layer 31 is formed, a certain flow rate of silane is introduced into the reaction chamber of the deposition process, and under the preset deposition conditions, a second intrinsic silicon layer with a thickness of 50nm-280nm is deposited on the surface of the second tunneling oxide layer 31 away from the N-type silicon substrate 1.

[0082] S216, using a phosphorus diffusion process to perform phosphorus doping on the N-type silicon substrate forming the second intrinsic silicon layer to form a second doped layer.

[0083] S217, preparing a second mask layer on the front surface and on the surface of the second doped layer facing away from the N-type silicon substrate.

[0084] The phosphorus diffusion process is a process for forming an N-type region by phosphorus diffusion on an N-type silicon substrate 1, thereby forming a PN junction. The PN junction is responsible for separating photogenerated carriers (electron-hole pairs) to achieve photoelectric conversion.

[0085] Specifically, similar to the formation process of the first doping layer 22, a certain flow of nitrogen and oxygen is introduced into the reaction chamber of the low-temperature deposition process, phosphorus oxychloride is doped in the nitrogen, and phosphorus oxychloride is the doping source of the phosphorus diffusion process. Under the deposition conditions of a deposition temperature of 380°C-450°C and a deposition pressure controlled between 100Pa-400Pa, a layer of phosphorus can be deposited on the surface of the second intrinsic silicon layer away from the N-type silicon substrate 1 by using the chemical reaction between phosphorus oxychloride, oxygen and the second intrinsic silicon layer. After the phosphorus is formed, the phosphorus is pushed at high temperature, and the phosphorus is diffused into the second intrinsic silicon layer by setting the pushing temperature of the high-temperature pushing to form a second doping layer 32. The square resistance of the second doping layer 32 is 1Ω / sq-40Ω / sq. After the second doping layer 32 is formed, the residual organic matter generated in the doping process is post-oxidized, and a certain flow of oxygen is introduced into the post-oxidation reaction chamber, so that the residual organic matter reacts with oxygen to form a second mask layer. Usually, the second mask layer is a phosphorus silicon glass layer.

[0086] It is understandable that the equipment for the phosphorus diffusion process includes but is not limited to a phosphorus diffusion furnace. When phosphorus diffusion is performed in the equipment, double-sided diffusion is usually performed, or the N-type silicon substrate 1 is phosphorus diffused in a double-insertion manner. In this process, it cannot be guaranteed that the phosphosilicate glass layer produced by post-oxidation is only formed on the back side of the N-type silicon substrate 1. In the actual production process, the phosphosilicate glass layer will also be generated on the front side at the same time.

[0087] It can also be understood that in order to increase the doping concentration of the second doping layer 32, the second doping layer 32 formed after doping can be annealed. Specifically, a tubular annealing furnace can be used with the temperature controlled at 690°C-890°C to activate phosphorus for 1000s-3000s to increase the doping concentration of the second doping layer 32.

[0088] S218, removing the second mask layer, the second doping layer, and the second tunneling oxide layer in the first region.

[0089] This step can be refined as follows: using laser technology to remove the second mask layer in the first region; using alkaline etching to remove the second doping layer 32 in the first region; and using acid etching to remove the second tunneling oxide layer 31 in the first region.

[0090] Specifically, the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer are all deposited on the entire surface, that is, the above three-layer structure is also deposited in the first region. At this time, the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer in the first region need to be removed. In this embodiment, the output power of the laser is set to 1W-500W, and the laser frequency is 100kHz-1000kHz. The picosecond laser emitted under this condition is used to etch and remove the second mask layer in the first region to expose the second doping layer 32 in the first region. Then, an alkali etching process is used to introduce an alkali solution such as sodium hydroxide or potassium hydroxide with a mass of 5%-10% into the reaction chamber of the alkali etching process, and an etching additive is added so that the alkali solution and the etching additive are configured in a second preset ratio. Under this etching condition, the second doping layer 32 in the first region is removed by a chemical reaction between the alkali solution and the second doping layer 32, and the second tunneling oxide layer 31 in the first region is exposed. After exposing the second tunnel oxide layer 31 of the first region, an acid etching process is used to set an acid solution such as hydrofluoric acid and set the concentration of the hydrofluoric acid within a certain range. The hydrofluoric acid will chemically react with the second tunnel oxide layer 31 to remove the second tunnel oxide layer 31 of the first region.

[0091] It should be noted that in order to prevent a short circuit between the first region and the second region, when the second tunneling oxide layer 31, the second doping layer 32 and the second mask layer of the first region are etched and removed, the area connecting the first region and the second region will also be removed synchronously, so that there is a preset spacing distance between the first region and the second region to ensure the performance of the TBC battery.

[0092] S219, removing the first mask layer and the second mask layer deposited on the front side.

[0093] Specifically, before the front surface is textured, the normally deposited first mask layer and the second mask layer need to be removed. Specifically, they can be etched and removed using an acidic solution formed by a third preset ratio of 1%-30% hydrofluoric acid, 10%-30% nitric acid and 1%-20% sulfuric acid to expose the front surface of the N-type silicon substrate 1.

[0094] S220, adopting the velvet making process, velveting is performed on the front side to form a velvet structure.

[0095] S221 , removing the first mask layer in the first area and the second mask layer in the second area.

[0096] Specifically, after removing the first mask layer and the second mask layer on the front side, the front side can be textured under preset texture conditions using a texture making process. The specific texture making process can be set according to actual conditions and is not limited here. After the texture making is completed, the first mask layer in the first area and the second mask layer in the second area need to be etched and removed. They can also be etched and removed using an acidic solution such as hydrofluoric acid that has been preset. The process steps for removing the first mask layer in the first area and the second mask layer in the second area are set after the texture making process on the front side. The purpose is to not affect the first doping layer 22 and the second doping layer 32 on the back side during the texture making process on the front side. The first mask layer and the second mask layer play a protective role to ensure the performance of the TBC battery.

[0097] S222, using a deposition process, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the surface of the suede structure on the side away from the N-type silicon substrate.

[0098] Specifically, after the first mask layer in the first region and the second mask layer in the second region are removed, it is necessary to prepare a first protective layer 4 on the surface of the first doped layer 22 and the second doped layer 32 on the back side away from the N-type silicon substrate 1. The first protective layer 4 includes a first passivation layer and a first anti-reflection layer. In this embodiment, an atomic layer deposition process is used to deposit a first passivation layer on the surface of the first doped layer 22 and the second doped layer 32 on the back side. The components of the first passivation layer include but are not limited to aluminum oxide, silicon oxide, or a combination of aluminum oxide and silicon oxide. The thickness of the first passivation layer is 1nm-70nm. Then, a deposition process such as plasma enhanced chemical vapor deposition is used to deposit a first anti-reflection layer on the surface of the first passivation layer away from the N-type silicon substrate 1. The components of the first anti-reflection layer may include but are not limited to silicon nitride, or a combination of silicon nitride and silicon oxide, or silicon oxynitride. The thickness of the first anti-reflection layer is 1nm-110nm. In addition, a second protective layer 5 needs to be prepared on the front side. The second protective layer 5 includes a second passivation layer and a second anti-reflection layer. Specifically, the second passivation layer can be deposited on the surface of the velvet structure on the front side away from the N-type silicon substrate 1 by using an atomic layer deposition process at a temperature of 200°C-300°C and a deposition time of 9min-15min. The components of the second passivation layer include but are not limited to aluminum oxide, silicon oxide, or a combination of aluminum oxide and silicon oxide. The thickness of the formed second passivation layer is 1nm-70nm. After the second passivation layer is formed, a second anti-reflection layer can be deposited on the surface of the second passivation layer away from the N-type silicon substrate 1 by using a deposition process such as plasma enhanced chemical vapor deposition. The components of the second anti-reflection layer can include but are not limited to silicon nitride, or a combination of silicon nitride and silicon oxide, or silicon oxynitride. The thickness of the formed second anti-reflection layer is 1nm-110nm, thereby forming the second protective layer 5.

[0099] It should be noted that, usually, in the process of preparing the passivation layer on the front and back sides, an atomic layer deposition process is usually used to deposit the passivation layer on the front and back sides simultaneously, so as to reduce the process flow and shorten the preparation time.

[0100] S223, screen printing and high-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, to manufacture a TBC battery.

[0101] The technical solution of the embodiment of the present invention comprises the following steps: using a deposition process to prepare a first tunneling oxide layer and a first intrinsic silicon layer in a first region and a second region; using a boron diffusion process to boron-dope an N-type silicon substrate forming the first intrinsic silicon layer under a preset high temperature condition to form a first doping layer, and forming a first mask layer on the front surface and the surface of the first doping layer; removing the first mask layer, the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region; using a deposition process to prepare a second tunneling oxide layer and a second intrinsic silicon layer on the surface of the N-type silicon substrate and the first mask layer in the exposed second region away from the N-type silicon substrate; using a phosphorus diffusion process to dope the N-type silicon substrate in the second region to form a first doping layer; and The method comprises the following steps: using a dispersion process to dope the N-type silicon substrate forming the second intrinsic silicon layer with phosphorus to form a second doped layer; forming a second mask layer on the front surface and the surface of the second doped layer; removing the second mask layer, the second doped layer and the second tunneling oxide layer in the first region; removing the first mask layer and the second mask layer on the front surface; using a texturing process to perform front texturing on the front surface to form a velvet structure; removing the first mask layer in the first region and the second mask layer in the second region; using a deposition process to prepare a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the surface of the velvet structure away from the N-type silicon substrate. The above method is used to realize the preparation of TBC batteries, improve the passivation effect, effectively inhibit the recombination of electrons and holes, reduce surface defects, improve the opening voltage and fill factor of TBC batteries, and thus improve the conversion rate and surface quality of TBC batteries.

[0102] Based on the same inventive concept, an embodiment of the present invention further provides a TBC battery, which is manufactured using the above-mentioned TBC battery preparation method and has functional modules and beneficial effects corresponding to the execution method.

[0103] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0104] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a TBC battery, characterized in that: include: Providing an N-type silicon substrate; The N-type silicon substrate comprises a front side and a back side, wherein the back side comprises a first region and a second region alternately arranged in an interdigitated shape; Using a preset high temperature condition, preparing a first tunneling oxide layer and a first doping layer in the first region; preparing a second tunneling oxide layer and a second doping layer in the second region; Performing front texturing on the front side, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing; The first region and the second region are screen printed and sintered at high temperature to form a first electrode in contact with the first doping layer in the first region, and a second electrode in contact with the second doping layer in the second region, so as to manufacture a TBC battery.

2. The preparation method according to claim 1, characterized in that: Using a preset high temperature condition, preparing a first tunneling oxide layer and a first doping layer in the first region, including: Using a deposition process, preparing the first tunneling oxide layer and the first intrinsic silicon layer in the first region and the second region; The first doping layer is formed by boron diffusion process, and the N-type silicon substrate forming the first intrinsic silicon layer is doped with boron under the preset high temperature condition.

3. The preparation method according to claim 2, characterized in that: The method comprises: adopting a boron diffusion process to dope the N-type silicon substrate forming the first intrinsic silicon layer with boron under the preset high temperature condition to form the first doped layer, comprising: The first doping layer is formed by boron doping the N-type silicon substrate forming the first intrinsic silicon layer with boron under the preset high temperature conditions by using tubular diffusion equipment and adopting a boron diffusion process.

4. The preparation method according to claim 3, characterized in that: The preset high temperature condition T satisfies: T>1000°C.

5. The preparation method according to claim 3, characterized in that: The time for forming the first doping layer is a preset time, and the preset time t satisfies: 30min≤t≤40min.

6. The preparation method according to claim 3, characterized in that: The thickness h of the first doping layer satisfies: 250nm≤h≤380nm; and / or the concentration n of the first doping layer satisfies: n>7e19cm-3.

7. The preparation method according to claim 3, characterized in that: The reaction chamber of the tubular diffusion device is used to introduce boron trichloride and oxygen, and the ratio m between the flow rate of the introduced boron trichloride and the flow rate of the introduced oxygen satisfies: 1:2.5≤m≤1:

3.

8. The preparation method according to claim 3, characterized in that: The sheet resistance of the first doped layer is 90Ω / sq-130Ω / sq.

9. The preparation method according to claim 2, characterized in that: The method further comprises: adopting a boron diffusion process to dope the N-type silicon substrate forming the first intrinsic silicon layer with boron under the preset high temperature conditions, and after forming the first doped layer, the method further comprises: forming a first mask layer on the front surface and on a surface of the first doped layer facing away from the N-type silicon substrate; removing the first mask layer, the first doping layer and the first tunneling oxide layer in the second region to expose the N-type silicon substrate in the second region; Preparing a second tunneling oxide layer and a second doping layer in the second region includes: Using the deposition process, forming the second tunneling oxide layer and the second intrinsic silicon layer on the surface of the N-type silicon substrate and the first mask layer in the exposed second region facing away from the N-type silicon substrate; The N-type silicon substrate forming the second intrinsic silicon layer is doped with phosphorus by a phosphorus diffusion process to form the second doped layer.

10. The preparation method according to claim 9, characterized in that: The method further comprises: adopting a phosphorus diffusion process to phosphorus-dope the N-type silicon substrate forming the second intrinsic silicon layer, and after the second doped layer is formed, the method further comprises: Preparing a second mask layer on the front surface and on a surface of the second doped layer facing away from the N-type silicon substrate; The second mask layer, the second doping layer and the second tunneling oxide layer in the first region are removed.

11. The preparation method according to claim 10, characterized in that: Performing front texturing on the front side, preparing a first protective layer on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and preparing a second protective layer on the front side after the front texturing, including: removing the first mask layer and the second mask layer deposited on the front side; A velvet making process is adopted to perform velvet making on the front surface to form a velvet structure; removing the first mask layer in the first area and the second mask layer in the second area; By using the deposition process, a first protective layer is prepared on the surface of the first doped layer and the second doped layer on the back side away from the N-type silicon substrate, and a second protective layer is prepared on the surface of the suede structure away from the N-type silicon substrate.

12. The preparation method according to claim 1, characterized in that: Before preparing the first tunnel oxide layer and the first doping layer in the first region under the preset high temperature condition, the method further includes: The front side and the back side of the N-type silicon substrate are double-sided polished.

13. A TBC battery, characterized in that: The TBC battery is prepared by the preparation method of any one of claims 1 to 12.

Images