Filter chip, filter chip manufacturing method and filter device

Abstract

The present application relates to the technical field of filter, in particular to a filter chip and a preparation method thereof, the filter chip comprises a piezoelectric substrate, IDT electrodes and a frequency tuning dielectric layer. The IDT electrodes are arranged on the piezoelectric substrate at intervals, and the frequency tuning dielectric layer covers the piezoelectric substrate and the IDT electrodes. Wherein, the final thickness of the frequency tuning dielectric layer on the IDT electrode and the piezoelectric substrate is determined by formula (1), formula (1) is as follows: H1=[F1-(F2+△F S +△F IDT )] / A; H1 is the final thickness of the frequency tuning dielectric layer, F1 is the target frequency of the frequency tuning dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after depositing the IDT electrode, △F S is the electrical frequency affected by the piezoelectric substrate, △F IDT is the frequency compensation value of the IDT electrode process, and A is the sensitive coefficient. Therefore, the electrical stability of the filter chip can be effectively improved, and the product yield can be ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of filter technology, in particular to a filter chip, a filter chip manufacturing method and a filter device, which can be used for elastic wave filters. BACKGROUND

[0002] An elastic wave device is a solid device that performs various functions by processing acoustic signals propagating on the surface of a piezoelectric substrate using the characteristics of an acoustic-electric transducer. An elastic wave filter is mainly composed of a substrate material having piezoelectric characteristics and interdigitated transducers (IDTs) composed of metal thin films formed on the polished surface of the material.

[0003] At present, a known frequency bandwidth adjustment method is to uniformly coat an insulating film to the entire surface of a piezoelectric substrate of a filter containing interdigital electrodes, and to etch the insulating film to provide a thickness according to the required frequency. The following describes the manufacturing process of an elastic wave filter according to this method.

[0004] First, a piezoelectric substrate is prepared. After polishing the piezoelectric substrate, a resist pattern formed by a photoresist is added to the surface of the substrate using a known technique. Then, a metal film made of Al or Au with high electrical conductivity is deposited thereon by a technique such as vapor deposition to provide a predetermined thickness.

[0005] Second, the obtained product is immersed in a solvent, and then simultaneously melted or simultaneously peeled off by ultrasonic irradiation, so that the resist pattern and the metal film coated on the resist pattern are removed. At this time, the IDT electrodes having the required pattern are formed from the remaining metal film.

[0006] Then, an insulating film made of a material such as SiO2 having an etching rate different from that of the electrodes is deposited on the entire piezoelectric substrate including the electrodes and attached by sputtering or chemical vapor deposition (CVD) to provide a predetermined thickness.

[0007] An electrical signal is added to the electrodes using a wafer probe to measure the frequency, and the difference between the measured frequency and the target value is determined. The difference is subsequently made zero by etching the insulating film to adjust the frequency.

[0008] The conventional algorithm is to adjust the thickness of the insulating film based on the difference between the measured frequency and the target value, but this approach cannot ensure the product yield and electrical stability.

[0009] It should be noted that the information disclosed in this BACKGROUND section is only intended to increase an understanding of the general context of the present application and should not be taken as an acknowledgement that this information constitutes prior art that is already known in the art. SUMMARY

[0010] The present application provides a filter chip, which comprises a piezoelectric substrate, IDT electrodes and a frequency-tuning dielectric layer.

[0011] The IDT electrodes are arranged on the piezoelectric substrate at intervals. The frequency-tuning dielectric layer covers the piezoelectric substrate and the IDT electrodes. The final thickness of the frequency-tuning dielectric layer is determined according to the thickness of the piezoelectric substrate, the interval of the IDT electrodes and the deposition thickness of the frequency-tuning dielectric layer. S +△F IDT )] / A. H1 is the final thickness of the frequency-tuning dielectric layer, F1 is the target frequency of the frequency-tuning dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrodes are deposited, △F S is the electrical frequency affected by the piezoelectric substrate,

[0012] △F IDT is the frequency compensation value of the IDT electrode process, and A is a sensitive coefficient.

[0013] The present application also provides a filter chip, which comprises a piezoelectric substrate, IDT electrodes and a frequency-tuning dielectric layer. The IDT electrodes are arranged on the piezoelectric substrate at intervals. The frequency-tuning dielectric layer covers the piezoelectric substrate and the IDT electrodes. The final thickness of the frequency-tuning dielectric layer is determined according to the thickness of the piezoelectric substrate, the interval of the IDT electrodes and the deposition thickness of the frequency-tuning dielectric layer.

[0014] The present application also provides a preparation method of a filter chip, which comprises the following steps: forming IDT electrodes arranged at intervals on a piezoelectric substrate; depositing a frequency-tuning dielectric layer on the piezoelectric substrate and the IDT electrodes; and adjusting the frequency-tuning dielectric layer according to the thickness of the piezoelectric substrate, the interval of the IDT electrodes and the deposition thickness of the frequency-tuning dielectric layer to obtain the final thickness of the frequency-tuning dielectric layer.

[0015] An embodiment of the present application provides a filter chip and a preparation method thereof. The final thickness of the frequency-tuning dielectric layer is determined according to the thickness of the piezoelectric substrate, the interval of the IDT electrodes and the deposition thickness of the frequency-tuning dielectric layer, so that the final thickness of the frequency-tuning dielectric layer can be adjusted more accurately, the filter chip can reach the required target frequency more accurately, the product demand can be met, the electrical stability of the filter chip is improved, the product yield is ensured, and the problem of low product yield caused by deviation of the traditional algorithm is solved.

[0016] Other features and advantages of the present application will be illustrated in the following description, and some technical features and advantages can be obtained from the description or by implementing the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, part of the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0018] Figure 1a is a partial cross-sectional view of a filter chip provided by an embodiment of the present application;

[0019] Figure 1b is a partial top view of a filter chip provided by an embodiment of the present application;

[0020] Figures 2 to 5 is a structural schematic diagram of the filter chip shown in Fig. 1 at various stages in the manufacturing process;

[0021] Figure 6 is a flowchart of a filter chip manufacturing method provided by an embodiment of the present application;

[0022] Figure 7 is a frequency distribution diagram of a filter wafer implemented according to the present application;

[0023] Figure 8 is a frequency distribution diagram of a conventional filter wafer;

[0024] Figure 9 is a cross-sectional view of a filter device implemented according to the present application.

[0025] Reference signs:

[0026] 1 - filter chip; 10 - support substrate; 12 - piezoelectric substrate; 14 - IDT electrode; 14a - IDT; 14b - reflector; 16 - tuning dielectric layer; 22 - wiring substrate; 24 - bump; 26 - sealing portion; L1 - pitch of IDT electrode; H2 - thickness of piezoelectric substrate. DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. The technical features designed in different embodiments of the present application can be combined with each other as long as they do not conflict with each other. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0028] In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the terms "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or component indicated thereby must have a particular orientation or be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated thereby. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, the term "comprising" and any variation thereof means "at least including".

[0029] The filter chip disclosed in the following embodiments can be, for example, a substrate formed of a piezoelectric single crystal such as lithium tantalate, lithium niobate or quartz. The filter chip can also be, for example, a substrate formed of a piezoelectric ceramic. The filter chip can also be, for example, a substrate formed by joining a piezoelectric substrate to a support substrate. The support substrate is, for example, a substrate formed of sapphire, silicon, alumina, spinel, quartz or glass. The filter chip is a substrate provided with functional components, for example, a receive filter and a transmit filter provided on a main surface of the filter chip.

[0030] The following embodiments will be described in detail taking the joining of a piezoelectric substrate to a support substrate as an example.

[0031] Referring to Figure 1a , Figure 1a is a partial cross-sectional schematic view of a filter chip according to an embodiment of the present application. In order to achieve at least one of the advantages described above or other advantages, an embodiment of the present application provides a filter chip. As shown in the figure, the filter chip includes a piezoelectric substrate 12, an IDT electrode 14 and a tuning dielectric layer 16.

[0032] In a preferred embodiment, the piezoelectric substrate 12 can be disposed on a support substrate 10, which includes the support substrate 10 made of a high acoustic velocity material. Specifically, the support substrate 10 is made of a high acoustic velocity material, which functions as a support and as a high acoustic velocity medium for signal transmission. The support substrate 10 can be a substrate formed of a material selected from a group consisting of silicon carbide, alumina, aluminum nitride, sapphire, silicon nitride, silicon, spinel, and magnesium oxide. In a preferred embodiment, the support substrate 10 is made of a polycrystalline material, which is advantageous in suppressing spurious signals. The piezoelectric substrate 12 has a piezoelectric effect, i.e., generates an electric charge distribution and thus an electric voltage when subjected to an external force. The material of the piezoelectric substrate 12 can be lithium tantalate (LT) or lithium niobate (LN), but the present application is not limited thereto, and the material of the piezoelectric substrate 12 can be another material having a stable crystal structure, such as quartz. In some embodiments, the thickness H2 of the piezoelectric substrate 12 is in a range of 0.5 to 5 μm. In a preferred embodiment, the thickness of the piezoelectric substrate is preferably in a range of 1.05 to 1.5 μm.

[0033] In some embodiments, a dielectric layer can be formed between the piezoelectric substrate 12 and the support substrate 10, which can include a high acoustic velocity layer, a low acoustic velocity layer, or a combination of both. The high acoustic velocity layer can be made of any one of aluminum nitride, alumina, silicon carbide, silicon nitride, silicon oxynitride, DLC film or diamond, a material having any one of the above materials as a main component, or a material having a mixture of the above materials as a main component. The low acoustic velocity layer can be made of any one of silicon oxide, glass, silicon oxynitride, tantalum oxide, or a compound obtained by adding fluorine or carbon or boron to silicon oxide, or a material having any one of the above materials as a main component.

[0034] As Figure 1bAs shown, the main surface of the piezoelectric substrate 12 is provided with an IDT (Interdigital Transducer) 14a and a pair of reflectors 14b. The IDT 14a and the reflectors 14b are provided for exciting a surface acoustic wave. For example, the IDT 14a and the reflectors 14b are made of an alloy of aluminum and copper. For example, the IDT 14a and the reflectors 14b are made of an appropriate metal such as titanium, palladium, silver, or an alloy thereof. For example, the IDT 14a and the reflectors 14b can be a laminated metal film formed by laminating a plurality of metal layers. The thickness of the IDT 14a and the reflectors 14b is, for example, 150 nm to 400 nm. The IDT 14a has a pair of comb electrodes 14c. The comb electrodes 14c face each other. Each of the comb electrodes 14c has a plurality of electrode fingers 14d and a bus bar 14e. The electrode fingers 14d extend in the longitudinal direction. The bus bar 14e connects the electrode fingers 14d. One of the reflectors 14b is adjacent to one side of the IDT 14a, and the other reflector 14b is adjacent to the other side of the IDT 14a, that is, the two reflectors 14b are located on opposite sides of the IDT 14a, respectively, and in the illustrated embodiment, on the left and right sides of the IDT 14a.

[0035] The IDT electrodes 14 are provided on the piezoelectric substrate 12 at intervals. IDT (Inter Digital Transducer) is a transducer with interdigital electrodes. By applying a high-frequency electric signal to both ends of the IDT electrodes 14, mechanical vibration occurs on the surface of the piezoelectric substrate 12, and at the same time, a surface acoustic wave having the same frequency as the applied electric signal is excited, and this surface acoustic wave propagates along the surface of the piezoelectric substrate 12. If a pair of IDT electrodes 14 is provided on the propagation path of the SAW (Surface Acoustic Wave), the SAW can be detected and converted into an electric signal. The IDT electrodes 14 can be formed on the piezoelectric substrate 12 by semiconductor planar processing technology.

[0036] The frequency tuning dielectric layer 16 covers the piezoelectric substrate 12 and the IDT electrode 14. By adjusting the covering thickness of the frequency tuning dielectric layer 16, the frequency of the filter chip can be changed so that the filter chip reaches the required target frequency and meets the product requirements. Traditionally, the thickness of the frequency tuning dielectric layer 16 is confirmed mainly by adjusting the thickness of the frequency tuning dielectric layer 16 based on the difference between the measured frequency and the target value. However, such a method cannot ensure product yield and electrical stability. The inventors have found in experiments that the deviation of the traditional method is too large, mainly due to the following two aspects: 1. When the pitch L1 of the IDT electrode 14 is too large or too small, the use of the traditional algorithm will produce obvious deviation, resulting in reduced product yield; 2. When the thickness H2 uniformity of the piezoelectric substrate 12 is poor, the filter is greatly affected by the thickness uniformity of the piezoelectric substrate 12, resulting in that the traditional algorithm cannot ensure the electrical stability of the product. Therefore, the inventors propose to determine the final thickness of the frequency tuning dielectric layer 16 according to the thickness H2 of the piezoelectric substrate 12, the pitch L1 of the IDT electrode 14 and the deposition thickness of the frequency tuning dielectric layer 16, so as to realize accurate regulation and control of the frequency tuning dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, meet the product requirements, improve the electrical stability of the filter chip, and ensure the product yield.

[0037] In an embodiment, the final thickness of the frequency tuning dielectric layer 16 on the IDT electrode 14 and the piezoelectric substrate 12 can be determined by formula (1), which is as follows: H1 = [F1 - (F2 + AF S + AF IDT )] / A. Wherein H1 is the final thickness of the frequency tuning dielectric layer 16, and the frequency tuning dielectric layer 16 is etched according to H1, and the remaining thickness of the frequency tuning dielectric layer 16 is the final thickness. F1 is the target frequency of the frequency tuning dielectric layer 16, that is, the target frequency required to be reached by the filter chip. F2 is the electrical frequency measurement value of the piezoelectric substrate 12 after the IDT electrode 14 is deposited (i.e. the electrical frequency measurement value when the frequency tuning dielectric layer 16 is not covered). AF S is the electrical frequency affected by the piezoelectric substrate 12. AF IDT is the frequency compensation value of the IDT electrode 14 process, and A is the sensitivity coefficient. It should be noted that the final thickness of the frequency tuning dielectric layer 16 on the IDT electrode 14 and the final thickness of the frequency tuning dielectric layer 16 on the piezoelectric substrate 12 can be different. The final thickness of the frequency tuning dielectric layer 16 on the IDT electrode 14 and the final thickness of the frequency tuning dielectric layer 16 on the piezoelectric substrate 12 can be accurately determined by the above formula (1) respectively to ensure the quality of the filter chip, and the final thickness of the frequency tuning dielectric layer 16 at different places on the piezoelectric substrate 12 can also be determined according to the surface flatness of the piezoelectric substrate 12 (the surface flatness of the piezoelectric substrate 12 will affect the thickness H2 of the piezoelectric substrate 12).

[0038] Since F=V / λ, the thickness H2 of the piezoelectric substrate 12 affects the propagation speed of the surface acoustic wave. When λ is constant, the thinner the piezoelectric substrate 12, the greater V and F are. According to the change of the substrate thickness and the change of F frequency, the influence coefficient of the IDT electrode 14 pitch L1 on the frequency, λ, can be used to derive the relationship between △V and the substrate thickness, and the relationship between △F S =△V / λ, where △V is the propagation speed of the surface acoustic wave in the piezoelectric substrate 12, and λ is the influence coefficient of the IDT electrode 14 pitch L1 on the frequency.

[0039] △F IDT is a constant value determined according to the IDT electrode 14 that has been formed. Since the photolithography development equipment is stable and unchanging, △F IDT is a constant value. For example, when the IDT electrode 14 is a three-layer Ti / AlCu / Ti structure with thicknesses of 30 nm, 135 nm, and 15 nm for Ti, AlCu, and Ti respectively, and an Al and Cu doping ratio of 98.5:1.5, and the photolithography development equipment IDT angle is controlled within 70°±10°, the value of △F IDT is -2.019. When the IDT electrode 14 is a three-layer Ti / AlCu / Ti structure with thicknesses of 30 nm, 160 nm, and 15 nm for Ti, AlCu, and Ti respectively, and an Al and Cu doping ratio of 98.5:1.5, and the photolithography development equipment IDT angle is controlled within 70°±10°, the value of △F IDT is -1.4186.

[0040] A is a sensitive coefficient of the product, which is a constant term determined according to the chip product and fluctuates within a range of 0.5-0.6.

[0041] In some embodiments, the material of the frequency tuning dielectric layer 16 includes SiO2. Further, when the material of the frequency tuning dielectric layer 16 is SiO2, formula (1) can be transformed into formula (2), which is as follows: H1={F1-[F2+(H2-1.540) / 0.064]-2.019} / A, where H2 is the thickness of the piezoelectric substrate 12, and A=0.535±10% (i.e. 0.4815-0.5885). In this way, the final thickness of the frequency tuning dielectric layer 16 can be accurately controlled, so that the filter chip can more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield.

[0042] Please refer to Figures 2 to 5 , Figures 2 to 5 is a structural schematic diagram of the filter chip shown in FIG. 1 at each stage of the manufacturing process. A method for manufacturing the filter chip shown in FIG. 1 is disclosed below.

[0043] First, as Figure 2As shown, a relatively thick support substrate 10 is provided. The support substrate 10 can be a substrate made of silicon carbide, aluminum oxide, aluminum nitride, sapphire, silicon, spinel, magnesium oxide, etc. Next, a relatively thin piezoelectric substrate 12 is formed on the support substrate 10, and the thickness H2 of the piezoelectric substrate 12 is measured. The thickness H2 of the piezoelectric substrate 12 can be 0.5 to 5 μm.

[0044] Secondly, such as Figure 3 As shown, an IDT electrode 14 is formed on the piezoelectric substrate 12. The IDT electrode 14 is made of a metallic material, such as Ti, Al, Cu, Pt, Au, Ag, or Pd, or an alloy containing at least two of the aforementioned metals. After the IDT electrode 14 is formed, a first electrical data measurement is performed to obtain the initial frequency F2. Furthermore, the spacing L1 of the IDT electrode 14 is measured to confirm the influence coefficient λ of the spacing L1 on the frequency.

[0045] Then, as Figure 4 As shown, a frequency-modulated dielectric layer 16 is formed on the piezoelectric substrate 12 and the IDT electrode 14. The frequency-modulated dielectric layer 16 covers the piezoelectric substrate 12 and the IDT electrode 14. The frequency-modulated dielectric layer 16 can be SiO2.

[0046] Finally, as Figure 5 As shown, the final thickness of the frequency modulation dielectric layer 16 is determined based on the thickness H2 of the piezoelectric substrate 12, the spacing L1 of the IDT electrodes 14, and the deposition thickness of the frequency modulation dielectric layer 16. For example, the final thickness of the frequency modulation dielectric layer 16 in each region can be determined by formula (1). The frequency modulation dielectric layer 16 is then subjected to plasma bombardment etching using gas to obtain the final thickness H1. This allows for precise control of the frequency modulation dielectric layer 16, enabling the filter chip to more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield. The gas used can be an inert gas, such as Ar or He. The parameters can be as follows: gas flow rate of 2–10 sccm; ACC voltage of 300–1000V; beam current of 10–50mA; beam voltage of 1000–2000V; trimming angle of 90–150°C; and RF power of 50–500W.

[0047] The above is only one method for manufacturing the filter chip shown in Figure 1. This case is not limited to this method, but is only used to illustrate one way of manufacturing a filter chip.

[0048] Please combine Figures 2 to 5 See Figure 6 , Figure 6is a flowchart of a filter chip preparation method provided by an embodiment of the present application. An embodiment of the present application further provides a filter chip preparation method, as shown in the figure, which includes the following steps:

[0049] S100: Forming the IDT electrode 14 arranged at intervals on the piezoelectric substrate 12. Then, a first electrical data measurement is performed to obtain F2, and the interval L1 of the IDT electrode 14 is measured to confirm the influence coefficient λ of the interval L1 of the IDT electrode 14 on the frequency. Before this, the thickness H2 of the piezoelectric substrate 12 can be measured first.

[0050] S200: Depositing the frequency-adjusting dielectric layer 16 on the piezoelectric substrate 12 and the IDT electrode 14.

[0051] S300: Adjusting the frequency-adjusting dielectric layer 16 according to the thickness H2 of the piezoelectric substrate 12, the interval L1 of the IDT electrode 14, and the deposition thickness of the frequency-adjusting dielectric layer 16 to obtain the final thickness of the frequency-adjusting dielectric layer 16 in each region. Subsequently, argon is used to perform plasma bombardment etching on the frequency-adjusting dielectric layer 16 to realize accurate regulation of the adjusted frequency-adjusting dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield.

[0052] The final thickness of the frequency-adjusting dielectric layer 16 on the IDT electrode 14 and the piezoelectric substrate 12 can be determined by formula (1), which is as follows: H1 = [F1-(F2+△F S +△F IDT )] / A. Wherein H1 is the final thickness of the frequency-adjusting dielectric layer 16, and the thickness of the frequency-adjusting dielectric layer 16 remaining after etching according to H1 is the final thickness. F1 is the target frequency of the frequency-adjusting dielectric layer 16, that is, the target frequency required to be reached by the filter chip. F2 is the electrical frequency measurement value of the piezoelectric substrate 12 after depositing the IDT electrode 14. △F S is the electrical frequency affected by the piezoelectric substrate 12. △F IDT is the frequency compensation value of the IDT electrode 14 process, and A is the sensitivity coefficient.

[0053] △F S =△V / λ,△V is the propagation speed of the surface acoustic wave in the piezoelectric substrate 12, and λ is the influence coefficient of the interval L1 of the IDT electrode 14 on the frequency. △F IDT is a constant value determined according to the IDT electrode 14 that has been formed. A is the sensitivity coefficient of the product, which is a constant term determined according to the chip product, and the value fluctuates within the range of 0.5-0.6.

[0054] Further, when the material of the frequency tuning dielectric layer 16 is SiO2, the formula (1) can be transformed to formula (2), the formula (2) is as follows: H1={F1-[F2+(H2-1.540) / 0.064]-2.019} / A, H2 is the thickness of the piezoelectric substrate 12, A=0.535±10%, so as to accurately control the final thickness of the frequency tuning dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product demand, improve the electrical stability of the filter chip, and ensure product yield.

[0055] As shown in the following table 1 and table 2, the filter chip prepared by using the method of the present application has a significant improvement in yield and product performance compared with the filter chip prepared by the traditional algorithm. Regarding the influence of electrical measurement key parameters, the overall frequency convergence is about 25%; the product yield is improved by about 4%.

[0056] Table 1

[0057]

[0058] Table 2

[0059]

[0060] As Figure 7 and Figure 8 Compared with the traditional algorithm, the frequency distribution graph of the wafer has a clear ring-shaped distribution, which is strongly related to the thickness of the substrate, which will make the frequency convergence worse, resulting in some point electrical measurement data exceeding the standard, and then affecting the product yield. The wafer graph of the filter chip prepared by using the method of the present application has no obvious distribution characteristics, the in-chip frequency uniformity PPM is about 25% higher than that of the old algorithm, and the yield is improved by about 4.2%.

[0061] An embodiment of the present application provides a filter chip and a preparation method thereof, which determines the final thickness of the frequency tuning dielectric layer 16 based on the thickness H2 of the piezoelectric substrate 12, the pitch L1 of the IDT electrode 14 and the deposition thickness of the frequency tuning dielectric layer 16, can more accurately adjust the final thickness of the frequency tuning dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product demand, improve the electrical stability of the filter chip, ensure product yield, and improve the problem of low product yield caused by the deviation of the traditional algorithm.

[0062] Please refer to Figure 9 , Figure 9 is a cross-sectional view of a filter device according to an embodiment of the present application. As shown in Figure 9 , the filter device includes a wiring substrate 22, a plurality of bumps 24, a filter chip 1 and a sealing portion 26. The bumps 24 are electrically connected to the main surface of the filter chip 1Figure 9 The bump 24 is also electrically connected to the wiring substrate 22. The filter chip 1 is joined to the wiring substrate 22 by the bump 24. The sealing portion 26 is provided on the wiring substrate 22 and covers the filter chip 1.

[0063] The wiring substrate 22 can be a multilayer substrate made of resin, and can also be a Low Temperature Co-fired Ceramics (LTCC) multilayer substrate formed of a plurality of dielectric layers. The bump 24 can be a gold bump, for example, and the height of the bump 24 can be between 20 μm and 50 μm.

[0064] The detailed design of the filter chip 1 can refer to the detailed description of the filter chip in the foregoing embodiments.

[0065] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present application can only be improved in one or several aspects, and it is not necessary to solve all the technical problems listed in the prior art or background art at the same time. Those skilled in the art should understand that what is not mentioned in a claim should not be regarded as a limitation on the claim.

[0066] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A filter chip, characterized by: The filter chip comprises: a piezoelectric substrate; IDT electrodes arranged at intervals on the piezoelectric substrate; a tuning dielectric layer covering the piezoelectric substrate and the IDT electrodes; wherein the final thickness of the tuning dielectric layer on the IDT electrodes and the piezoelectric substrate is determined by formula (1) as follows: H1 = [F1 - (F2 + AF S + AF IDT )] / A (1) H1 is the final thickness of the frequency-modulated dielectric layer, F1 is the target frequency of the frequency-modulated dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrode is deposited, and △F S is the electrical frequency affected by the piezoelectric substrate, △F IDT is the frequency compensation value of the IDT electrode process, and A is a sensitivity coefficient. wherein, ΔF S = ΔV / λ, ΔV is the propagation speed of the surface acoustic wave in the piezoelectric substrate, and λ is the influence coefficient of the pitch of the IDT electrode on the frequency.

2. The filter chip of claim 1, wherein: A has a value range of 0.5-0.

6.

3. The filter chip of claim 1, wherein: The material of the piezoelectric substrate comprises lithium tantalate or lithium niobate.

4. The filter chip of claim 1, wherein: The material of the tuning dielectric layer comprises SiO2.

5. The filter chip of claim 4, wherein: When the material of the tuning dielectric layer is SiO2, formula (1) is deformed to formula (2) as follows: H1={F1-[F2+(H2-1.540) / 0.064]-2.019} / A, H2 is the thickness of the piezoelectric substrate, and A=0.535±10%.

6. A filter chip, characterized by: The filter chip comprises: a piezoelectric substrate; IDT electrodes arranged at intervals on the piezoelectric substrate; a tuning dielectric layer covering the piezoelectric substrate and the IDT electrodes; wherein the final thickness of the tuning dielectric layer is determined according to the thickness of the piezoelectric substrate, the interval of the IDT electrodes and the deposition thickness of the tuning dielectric layer; The final thickness of the tuning dielectric layer is determined by formula (1) as follows: H1 = [F1 - (F2 + AF S + AF IDT )] / A (1) H1 is the final thickness of the frequency-modulated dielectric layer, F1 is the target frequency of the frequency-modulated dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrode is deposited, and △F S is the electrical frequency affected by the piezoelectric substrate, △F IDT is the frequency compensation value of the IDT electrode process, and A is a sensitivity coefficient. △F S =△V / λ,△V is the propagation speed of the surface acoustic wave in the piezoelectric substrate, and λ is the influence coefficient of the pitch of the IDT electrode on the frequency.

7. The filter chip of claim 6, wherein: A has a value range of 0.5-0.

6.

8. A method of making a filter chip, characterized by: The preparation method of the filter chip comprises the following steps: forming IDT electrodes arranged at intervals on a piezoelectric substrate; depositing a tuning dielectric layer on the piezoelectric substrate and the IDT electrodes; adjusting the tuning dielectric layer according to the thickness of the piezoelectric substrate, the interval of the IDT electrodes and the deposition thickness of the tuning dielectric layer to obtain the final thickness of the tuning dielectric layer; The final thickness of the tuning dielectric layer is determined by formula (1) as follows: H1 = [F1 - (F2 + AF S + AF IDT )] / A (1) H1 is the final thickness of the frequency-modulated dielectric layer, F1 is the target frequency of the frequency-modulated dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrode is deposited, and △F S is the electrical frequency affected by the piezoelectric substrate, △F IDT is the frequency compensation value of the IDT electrode process, and A is a sensitivity coefficient. △F S =△V / λ,△V is the propagation speed of the surface acoustic wave in the piezoelectric substrate, and λ is the pitch-to-frequency influence coefficient of the IDT electrode.

9. The method of claim 8, wherein: A has a value range of 0.5-0.

6.

10. The method of claim 8, wherein: The material of the piezoelectric substrate comprises lithium tantalate or lithium niobate.

11. The method of claim 8, wherein: The material of the tuning dielectric layer comprises SiO2.

12. A filter device, characterized by: The filter device comprises the filter chip according to any one of claims 1-10, and the filter chip is an elastic wave chip.

13. The filter device of claim 12, wherein: The filter device further comprises a wiring substrate and a sealing part, the filter chip is arranged on the wiring substrate, and the sealing part seals the filter chip.

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