High-voltage level shift circuit, gate driving chip, intelligent power module and equipment

Abstract

The invention provides a high-voltage level shift circuit, a gate driving chip, an intelligent power module and equipment, and the high-voltage level shift circuit comprises a double-pulse shaping circuit which is used for carrying out the shaping and phase inversion of a received first pulse signal and a received second pulse signal, obtaining a first inverted pulse signal and a second inverted pulse signal; the common-mode noise filtering circuit is electrically connected with the double-pulse shaping circuit and is used for filtering noise signals in the first reversed-phase pulse signal and the second reversed-phase pulse signal to respectively obtain and output a reset signal and a setting signal; the common-mode noise filtering circuit comprises a first switch tube, a second switch tube, a first current limiting circuit and a second current limiting circuit. According to the scheme, dV / dt noise can be eliminated, and interference to a post-stage circuit is avoided.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a high-voltage level shift circuit, a gate drive chip, an intelligent power module and a device. Background Art

[0002] Intelligent Power Module (IPM) integrates high-side gate drive chips, over-temperature, over-current and under-voltage protection circuits, fault handling circuits and driven power devices. Thanks to its advantages such as high switching frequency, low switching loss and strong anti-noise ability, it has great application potential in the current power electronics field and has a wide range of application scenarios, especially suitable for variable frequency motors and inverter power supplies.

[0003] Traditional high-side gate driver chips are mainly based on high-voltage double-pulse trigger level shift circuit (LEVEL_SHIFTER), pulse filter (NOISE CANCELLER), RS latch (RS LATCH), gate drive circuit (DRIVER), etc. When they are integrated into intelligent power modules (IPM), they are applied to high-voltage and high-speed environments. Due to their weak ability to resist dV / dt noise, high dV / dt noise may cause the power tube to be turned on incorrectly, resulting in direct connection of the upper and lower bridge power tubes, thereby seriously damaging the system. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] On one hand, the present application provides a high-voltage level shift circuit, the high-voltage level shift circuit comprising:

[0006] A double pulse shaping circuit, used for shaping and inverting the received first pulse signal and the second pulse signal respectively, to obtain a first inverted pulse signal and a second inverted pulse signal;

[0007] A common mode noise filtering circuit is electrically connected to the dual pulse shaping circuit and is used to filter out noise signals in the first inverted phase pulse signal and the second inverted phase pulse signal to obtain and output a reset signal and a set signal respectively;

[0008] Among them, the common mode noise filtering circuit includes:

[0009] A first switch tube, the gate of which is connected to the double pulse shaping circuit and the floating power supply, and is used to receive the second inverted pulse signal and control the on or off of the first switch tube through the second inverted pulse signal;

[0010] a second switch tube, the gate of which is connected to the double pulse shaping circuit and the floating power supply, and is used to receive the first inverted pulse signal, and control the conduction or cutoff of the second switch tube by the first inverted pulse signal, wherein the input end of the first switch tube is connected to the gate of the second switch tube, and the input end of the second switch tube is connected to the gate of the first switch tube;

[0011] A first current limiting circuit, one end of which is connected to the output end of the first switch tube, and the other end of which is connected to the floating ground end, and the output end of the first switch tube is used to output a reset signal;

[0012] The second current limiting circuit has one end connected to the output end of the second switch tube and the other end connected to the floating ground end. The output end of the first switch tube is used to output a setting signal.

[0013] In one embodiment, the double pulse shaping circuit comprises:

[0014] The first pulse shaping circuit is used to shape and invert the received first pulse signal and output a first inverted pulse signal, wherein the first pulse shaping circuit includes:

[0015] A first input switch tube, the gate of which is used to receive a first pulse signal;

[0016] A first current limiting resistor, one end of which is connected to the input end of the first input switch tube, and the other end of which is connected to the gate of the second switch tube, for outputting a first inverted pulse signal to the second switch tube;

[0017] The first current mirror circuit is coupled between the output terminal and the gate of the first input switch tube.

[0018] Since the dual pulse shaping circuit includes a current mirror circuit, the circuit's ability to resist noise interference can be improved, and a negative feedback loop can be provided. When the first pulse signal is a valid signal, the pulse signal is instantaneously set to a low level, and a narrow pulse is used to drive the first input switch tube to be turned on and off, thereby reducing power consumption.

[0019] In one embodiment, the first current mirror circuit includes:

[0020] A first NPN transistor, wherein the collector of the first NPN transistor is connected to the gate of the first input switch tube, and the emitter of the first NPN transistor is connected to the ground terminal;

[0021] A second NPN transistor, the collector of the second NPN transistor is connected to the output end of the first input switch tube, the emitter of the second NPN transistor is connected to the ground end, the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the base of the second NPN transistor is also electrically connected to the output end of the first input switch tube.

[0022] The current mirror circuit is formed by two NPN transistors, which enhances the circuit's ability to resist noise signal interference, and the structure is simple and low in cost.

[0023] In one embodiment, the double pulse shaping circuit comprises:

[0024] The second pulse shaping circuit is used to shape the received second pulse signal and output the shaped second inverted pulse signal, wherein the second pulse shaping circuit includes:

[0025] A second input switch tube, the gate of the second input switch tube is used to receive a second pulse signal;

[0026] A second current limiting resistor, one end of which is connected to the input end of the second input switch tube, and the other end of which is connected to the gate of the first switch tube, for outputting a second inverted pulse signal to the first switch tube;

[0027] The second current mirror circuit is coupled between the output terminal and the gate of the second input switch tube.

[0028] By setting up the current mirror circuit, the circuit's ability to resist noise interference can be improved, and a negative feedback loop can be provided. When the second pulse signal is a valid signal, the pulse signal is instantaneously set to a low level, and a narrow pulse is used to drive the second input switch tube to be turned on and off, thereby reducing power consumption.

[0029] In one embodiment, the second current mirror circuit comprises:

[0030] a third NPN transistor, wherein the collector of the third NPN transistor is connected to the gate of the second input switch tube, and the emitter of the third NPN transistor is connected to the ground terminal;

[0031] A fourth NPN transistor, the collector of the fourth NPN transistor is connected to the output end of the second input switch tube, the emitter of the fourth NPN transistor is connected to the ground end, the base of the fourth NPN transistor is electrically connected to the base of the third NPN transistor, and the base of the fourth NPN transistor is also electrically connected to the output end of the second input switch tube.

[0032] The current mirror circuit is formed by two NPN transistors, which enhances the circuit's ability to resist noise signal interference, and the structure is simple and low in cost.

[0033] In one embodiment, it further includes:

[0034] a first input resistor, one end of the first input resistor is connected to a floating power supply, and the other end of the first input resistor is connected to a first current limiting resistor; and

[0035] A second input resistor, one end of the second input resistor is connected to a floating power supply, and the other end is connected to a second current limiting resistor.

[0036] The first input resistor and the second input resistor can play the role of current limiting protection and voltage division, thereby ensuring the normal output of the reset signal and the set signal generated by the circuit.

[0037] In one embodiment, it further includes: a voltage stabilizing circuit, the first input resistor and the second input resistor are respectively connected in parallel with a voltage stabilizing circuit, wherein each voltage stabilizing circuit includes at least two diodes connected in series, and a cathode of a diode is electrically connected to a floating power supply.

[0038] Among them, by connecting at least two diodes in series, the voltage stabilization value of the voltage stabilization circuit can be improved, and a reverse current limiting protection function can also be achieved.

[0039] Another aspect of the present application provides a gate driver chip, comprising:

[0040] A pulse generating circuit, used for encoding the rising edge and the falling edge in the received PWM pulse width modulation signal into a first pulse signal and a second pulse signal respectively;

[0041] The high-voltage level shift circuit mentioned above is electrically connected to the pulse generating circuit and is used to receive the first pulse signal and the second pulse signal.

[0042] In one embodiment, it further includes:

[0043] The noise elimination circuit is electrically connected to the high-voltage level shift circuit and is used for receiving and filtering out differential mode noise in the set signal and the reset signal.

[0044] The noise elimination circuit can filter out differential mode noise in the signal, thereby improving the problem of false triggering caused by the differential mode noise interfering with the subsequent circuit.

[0045] In one embodiment, it further includes:

[0046] A trigger circuit, the trigger circuit is electrically connected to the noise elimination circuit, and is used to receive a signal output by the noise elimination circuit, and process the signal output by the noise elimination circuit to obtain a target drive signal, and when a noise signal appears in the signal output by the noise elimination circuit, the target drive signal is output as a latch signal;

[0047] A latch, the latch is electrically connected to the trigger circuit, and is used to receive a target drive signal and process it to obtain a switch signal to drive the device to be driven to turn on or off;

[0048] A driving circuit is connected to the gate of the target switch tube and is used to drive the target switch tube to be turned on or off, wherein the driving circuit includes a device to be driven, and the output end of the latch is connected to the gate of the device to be driven.

[0049] Among them, through the trigger circuit of the present application, the false triggering of the device to be driven caused by the noise signal caused by the negative voltage of VS and the narrow pulse width of the input signal can be improved, and a clean driving signal can be output, thereby solving the problem of the latch effect of the drive caused by the false triggering of the device, which may cause serious damage to the system.

[0050] In one embodiment, the pulse generating circuit comprises:

[0051] The filtering and shaping circuit receives the PWM pulse width modulation signal and performs filtering and shaping on it;

[0052] A low voltage level shift circuit is used for processing a PWM pulse width modulation signal to obtain a level shift signal;

[0053] The narrow pulse generating circuit is used for encoding the rising edge and the falling edge in the low voltage level shift signal into the first pulse signal and the second pulse signal respectively.

[0054] Among them, the signal is filtered and shaped by the filtering and shaping circuit to obtain a clean signal, the signal is transferred from the low-voltage area to the working voltage area by the low-voltage level shifting circuit, and the triggering time of the signal can be accurately controlled by the narrow pulse generating circuit to achieve high-precision timing control.

[0055] On the other hand, the present application also provides an intelligent power module, including the aforementioned gate drive chip.

[0056] In yet another aspect of the present application, a device includes the aforementioned high-voltage level shift circuit, or includes the aforementioned gate drive chip, or includes the aforementioned intelligent power module.

[0057] Through the high-voltage level shift circuit, gate drive chip, intelligent power module and device of the present application, when dV / dt noise is applied to the floating power supply voltage, the first switch tube and the second switch tube are both in the cut-off state, and the common-mode noise filtering circuit keeps outputting low-level reset signals and set signals. Therefore, the dV / dt noise can be eliminated and will not cause interference to the subsequent circuits, thereby effectively improving the problem that the power tube is mistakenly turned on due to dV / dt noise, resulting in the upper and lower bridge power tubes being directly connected and causing serious damage to the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0059] Figure 1 A circuit diagram of a high-side gate driver chip in the related art is shown;

[0060] Figure 2 A schematic diagram of the structure of an intelligent power module (IPM) is shown;

[0061] Figure 3 A schematic diagram of the circuit structure of a high-voltage double-pulse triggered level shift circuit in the related art is shown;

[0062] Figure 4 Shows Figure 3 Timing diagram of medium and high voltage double pulse triggered level shift circuit;

[0063] Figure 5 A schematic diagram of the circuit structure of a high-voltage level shift circuit in one embodiment of the present application is shown;

[0064] Figure 6 Shows Figure 5 Timing diagram of medium and high voltage level shift circuit;

[0065] Figure 7 Shows Figure 2 Schematic diagram of false triggering caused by the negative overshoot of VS and the overlap of RESET signal in the middle structure;

[0066] Figure 8 It shows that when the first pulse signal SET = 0 and the second pulse signal RESET = 1 Figure 5 A schematic diagram of the working state of the medium and high voltage level shift circuit;

[0067] Fig.9A The timing diagram when the VS negative overshoot overlaps with the RESET signal is shown;

[0068] Fig. 9B The timing diagram when the VS negative overshoot does not overlap with the RESET signal is shown;

[0069] Fig.10 A schematic diagram showing the structure of a trigger circuit in one embodiment of the present application is shown;

[0070] Fig.11 A schematic diagram of the structure of a pulse modulator in one embodiment of the present application is shown;

[0071] Fig.12 A timing diagram of an edge trigger circuit for receiving a reset signal in a trigger circuit in an embodiment of the present application is shown;

[0072] Fig.13 A schematic structural diagram of a high-voltage gate driver chip in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0073] In order to make the purpose, technical solutions and advantages of the present application more obvious, the example embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0074] High-voltage gate driver chips are mainly divided into low-side, high-side, single-channel, dual-channel, isolated, half-bridge, full-bridge and other power driver chips. It integrates low-voltage signal transmission logic control circuits to process front-end input signals more accurately. At the same time, in order to drive high-power devices at the back end, it is also equipped with a high-voltage output driver circuit. The core function of this circuit product is to convert the front-end microprocessor (MCU) signal into a switch tube drive control signal. In normal operation, the high-voltage gate driver chip not only processes the input signal to drive the power switch tube, but also transmits various operating status signals to the external microprocessor (MCU) to monitor the circuit working condition. The intelligent power module (IPM) integrates high-voltage gate driver chips, over-temperature, over-current and under-voltage protection circuits, fault handling circuits and driven power devices. Thanks to its high switching frequency, low switching loss, strong anti-noise ability and other advantages, it has strong application potential in the current power electronics field and has a wide range of application scenarios, especially suitable for variable frequency motors and inverter power supply fields. Such as Figure 1 As shown in the figure, the traditional high-side gate driver chip is mainly based on the high-voltage double-pulse trigger level shift circuit (LEVEL_SHIFTER), pulse filter (NOISE CANCELLER), RS latch (RS LATCH), gate driver circuit (DRIVER), etc. When it is integrated into the intelligent power module (IPM), it is applied to the high-voltage and high-speed environment, and often has problems such as false shutdown and false start. For example, the high-side gate driver chip has weak dV / dt noise resistance. The high dV / dt noise may cause the power tube to turn on by mistake, resulting in the upper and lower bridge power tubes being directly connected, thereby seriously damaging the system.

[0075] Next, we will combine Figures 2 to 4 , explain the causes of dV / dt noise, such as Figure 2 As shown, the intelligent power module includes a high-side gate driver chip HVIC and a low-side gate driver chip LVIC. They receive control signals from a microcontroller (MCU) or other control unit, amplify the signal and perform logic processing through internal circuits, and finally output sufficient voltage and current to drive the gate of the power device to turn it on and off. Among them, the high-side gate driver chip HVIC outputs a high-voltage drive output HO to control the high-side power tube IGBT1. The low-side gate driver chip LVIC outputs a low-voltage drive output LO to control the low-side power tube IGBT2.

[0076] Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power tube IGBT1 and the low-side power tube IGBT2 is the high-side floating ground VS terminal Vs. Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are alternately turned on. When the high-side power tube IGBT1 is turned on and the low-side power tube IGBT2 is turned off, the high-side floating ground VS terminal Vs is approximately equal to the bus voltage VH, that is, Vs is at a high potential. When the high-side power tube IGBT1 is turned off and the low-side power tube IGBT2 is turned on, the high-side floating ground VS terminal Vs is approximately equal to the ground voltage GND. Optionally, a load (not shown in the accompanying drawings) is connected between the voltage Vs of the high-side floating ground VS terminal and the ground voltage. Optionally, the high-side floating power supply voltage VB (also called the operating voltage VB) is bootstrapped and connected to the power supply voltage VCC through a bootstrap diode D1". Optionally, the high-side floating power supply voltage VB is bootstrapped and connected to the high-side floating ground Vs terminal through a bootstrap capacitor C1.

[0077] There are two main reasons for the generation of dV / dt noise: the first is that when the high-side power tube IGBT1 is turned on and the low-side power tube IGBT2 is turned off, the VS potential will rise, thereby generating dVS / dt noise. The noise generated in this case is mainly related to the switching speed of the power tube and the DC VH voltage. Among them, the faster the turn-off speed of the low-side power tube IGBT2, the larger the dVS / dt noise signal. The second is that when driving an inductive load, the IGBT2 turns off too fast and the energy on the load inductor L_load is not completely exhausted. At this time, the load inductor L_load will form a freewheeling loop with the body diode D3 of IGBT1. Since the diode turns on very quickly and the voltage at the VS end changes suddenly, the dV / dt noise generated in this case is large. Since the VB end and the VS end are connected through the bootstrap capacitor C1, the dV / dt noise is coupled to the high-voltage side floating power supply inside the chip through the bootstrap capacitor, thereby generating the same dV / dt noise in VB, such as Figure 3As shown, the power supply of the high-voltage level shift circuit integrated in the chip is the floating voltage. This high-voltage level shift circuit is mainly composed of HVNLDMOS and resistors in series. Due to process reasons, HVNLDMOS has parasitic capacitors C1 and C2 at the drain-source end, which will cause dV / dt noise to generate large displacement currents IC1 and IC2 through the parasitic capacitance of the HVNLDMOS drain end. This displacement current passes through the drain-end resistors R4 and R5 of the high-voltage level shift circuit, thereby generating voltage drops VR4 and VR5 on the drain-end resistors. Because VSD=VB-VR4, VRD=VB-VR5, generally R4=R5, so VSD=VRD, the larger the dV / dt noise, the smaller the VSD or VRD. The circuit working timing is as follows Figure 4 As shown, if the voltage drop value is greater than the logic input threshold of the subsequent module, the RS trigger will output an abnormal drive signal, causing the high-side power tube IGBT1 to be turned on or off incorrectly, affecting the normal logic function of the chip. Therefore, as the bridge between the high-side floating power supply and the low-side low-voltage circuit, the high-voltage level shift circuit's ability to resist dV / dt noise determines the reliability of the chip. In addition, since dV / dt noise and VS negative voltage overshoot will also interfere with the low-side GND and VCC through circuit structures such as parasitic capacitance, parasitic diodes and parasitic transistors inside the chip, affecting the SET and RESET signals, when the interfering signal meets the opening condition of HVNLDMOS (the first input switch tube and the second input switch tube), that is, VSET-VGND>Vth or VRESET-GND>Vth, a false trigger signal will be introduced, causing the upper bridge IGBT1 to be turned on or off incorrectly.

[0078] In order to solve the aforementioned technical problems, the present application provides a high-voltage level shift circuit, which includes: a dual pulse shaping circuit, used to shape and invert the received first pulse signal and the second pulse signal, respectively, to obtain a first inverted pulse signal and a second inverted pulse signal; a common-mode noise filtering circuit, electrically connected to the dual pulse shaping circuit, used to filter out the noise signals in the first inverted pulse signal and the second inverted pulse signal, and respectively obtain and output a reset signal and a set signal. Among them, the common-mode noise filtering circuit includes: a first switch tube, the gate of the first switch tube is connected to the dual pulse shaping circuit and the floating power supply, used to receive the second inverted pulse signal, and control the conduction or cutoff of the first switch tube through the second inverted pulse signal; a second switch tube, the gate of the second switch tube is connected to the dual pulse shaping circuit and the floating power supply, used to receive the first inverted pulse signal, and control the conduction or cutoff of the second switch tube through the first inverted pulse signal, wherein the input end of the first switch tube is connected to the gate of the second switch tube, and the input end of the second switch tube is connected to the gate of the first switch tube; a first current limiting circuit, one end of which is connected to the output end of the first switch tube, and the other end is connected to the floating ground end, and the output end of the first switch tube is used to output a reset signal; a second current limiting circuit, one end of which is connected to the output end of the second switch tube, and the other end is connected to the floating ground end, and the output end of the first switch tube is used to output a set signal.

[0079] Through the high-voltage level shift circuit of the present application, when dV / dt noise is applied to the floating power supply voltage, the first switch tube and the second switch tube are both in the cut-off state, and the common-mode noise filtering circuit keeps outputting a low-level reset signal and a set signal. Therefore, the dV / dt noise can be eliminated and will not cause interference to the subsequent circuit, thereby effectively improving the problem that the power tube is mistakenly turned on due to dV / dt noise, resulting in the upper and lower bridge power tubes being directly connected and causing serious damage to the system.

[0080] Next, we will refer to Figure 5 and Figure 6 , the structure of the high-voltage level shift circuit of the present application is described. It is worth mentioning that the technical features of each embodiment of the present application can be combined with each other without conflict.

[0081] First, if Figure 5 As shown, the high-voltage level shift circuit of the present application includes: a dual pulse shaping circuit 510, which is used to shape and invert the received first pulse signal SET and second pulse signal RESET respectively to obtain a first inverted pulse signal SET' and a second inverted pulse signal RESET'.

[0082] Optionally, the double pulse shaping circuit 510 is electrically connected to the pulse generating circuit of the previous stage, and the pulse generating circuit is used to encode the rising edge and the falling edge of the received PWM pulse width modulation signal into the first pulse signal SET and the second pulse signal RESET respectively. Optionally, the first pulse signal and the second pulse signal are both square wave signals. Optionally, the high level parts of the first pulse signal SET and the second pulse signal RESET do not overlap in timing to prevent the RS latch from having an unknown state.

[0083] The dual pulse shaping circuit 510 includes a first pulse shaping circuit and a second pulse shaping circuit. The structures of the two pulse shaping circuits are basically the same. They are respectively used to receive the first pulse signal SET and the second pulse signal RESET and shape them.

[0084] In one example, the first pulse shaping circuit is used to shape and invert the received first pulse signal, and output a first inverted pulse signal SET', wherein the first pulse shaping circuit includes a first input switch tube NM1, and the gate of the first input switch tube NM1 is used to receive the first pulse signal SET, and control the on or off of the first input switch tube NM1 based on the first pulse signal SET. Optionally, the first input switch tube NM1 can be any suitable switch tube such as NMOS or PMOS. Exemplarily, the first input switch tube NM1 is a high-voltage N-type LDMOS device.

[0085] In one example, the first pulse shaping circuit also includes a first current limiting resistor R2, one end of the first current limiting resistor R2 is connected to the input end of the first input switch tube NM1 (for example, the first input switch tube is a high-voltage N-type LDMOS device, then the input end can refer to the drain end of the LDMOS device), and the other end is connected to the gate of the second switch tube PM2, which is used to output the first inverted pulse signal SET' to the second switch tube. Optionally, the number of the first current limiting resistors R2 can be one or more, which is not specifically limited here. The first current limiting resistor R2 can limit the current size of the branch to prevent excessive current from burning out devices such as the switch tube, and the first current limiting resistor R2 can also be limited to a predetermined safety range, and the first current limiting resistor R2 can also be used as a voltage divider resistor.

[0086] In one example, the first pulse shaping circuit also includes a first current mirror circuit 511, which is coupled between the output terminal and the gate of the first input switch tube NM1, that is, one end of the first current mirror is connected to the source terminal of the first input switch tube NM1, and the other end is connected to the gate to receive the first pulse signal SET. By setting the current mirror circuit, the circuit's ability to resist noise interference can be improved, and by utilizing the characteristics of the current mirror, a negative feedback loop can be provided to facilitate monitoring the on or off state of NM1. When the first pulse signal SET is a valid signal, the pulse signal is instantaneously set to a low level, and the first input switch tube NM1 is driven on and off with a narrow pulse, thereby reducing power consumption.

[0087] In one example, a diode (such as a reverse Zener diode or a forward diode, not shown) can also be connected in series between the source of the first input switch tube NM1 and the base of the first NPN transistor to increase the NPN threshold voltage so that it is turned on when the first pulse signal SET is a valid high-level signal, and turned off when there is a noise signal to filter out interference signals.

[0088] In one example, the first current mirror circuit 511 can be any suitable circuit structure, for example, the first current mirror circuit 511 includes a first NPN transistor Q1 and a second NPN transistor Q2, the collector of the first NPN transistor Q1 is connected to the gate of the first input switch tube NM1, and the emitter of the first NPN transistor Q1 is connected to the ground terminal; the collector of the second NPN transistor Q2 is connected to the output terminal (for example, the source terminal) of the first input switch tube NM1, the emitter of the second NPN transistor Q2 is connected to the ground terminal, the base of the second NPN transistor Q2 is electrically connected to the base of the first NPN transistor Q1, and the base of the second NPN transistor Q2 is also electrically connected to the output terminal (for example, the source terminal) of the first input switch tube NM1. The current mirror circuit is formed by two NPN transistors, which enhances the circuit's ability to resist signal interference, and the structure is simple and low in cost.

[0089] In one example, the second pulse shaping circuit is used to shape the received second pulse signal RESET and output the shaped second inverted pulse signal RESET', wherein the second pulse shaping circuit includes: a second input switch tube NM2, a second current limiting resistor R3 and a second current mirror circuit 512, the gate of the second input switch tube NM2 is used to receive the second pulse signal RESET; one end of the second current limiting resistor R3 is connected to the input end of the second input switch tube, and the other end is connected to the gate of the first switch tube PM1, which is used to output the second inverted pulse signal RESET' to the first switch tube PM1 to drive the first switch tube PM1 to turn on and off, and optionally, the number of the second current limiting resistors R3 can be one or more, which is not specifically limited here. The second current limiting resistor R3 can limit the current size of the branch to prevent excessive current from burning out the switch tube and other devices, and the second current limiting resistor R3 can also be limited to a predetermined safety range, and the second current limiting resistor R3 can also be used as a voltage divider resistor.

[0090] Optionally, the second current mirror circuit 512 is coupled between the output terminal and the gate of the second input switch tube NM2. That is, one end of the second current mirror circuit 512 is connected to the source terminal of the second input switch tube NM2, and the other end is connected to the gate to receive the second pulse signal RESET. By setting the current mirror circuit, the circuit's ability to resist noise interference can be improved, and by utilizing the characteristics of the current mirror, a negative feedback loop can be provided to facilitate monitoring the on or off state of NM2. When the second pulse signal RESET is a valid signal, the pulse signal is instantly set low, and the second input switch tube NM2 is driven to be on and off with a narrow pulse, thereby reducing power consumption.

[0091] In one example, a diode (such as a reverse Zener diode or a forward diode, not shown) can also be connected in series between the source of the second input switch tube NM1 and the base of the fourth NPN transistor to increase the NPN threshold voltage so that it is turned on when the effective signal of the second pulse signal RESET is a high level signal, and turned off when a noise signal is generated to facilitate filtering out interference signals.

[0092] In one example, the second current mirror circuit 512 can use any suitable circuit structure, for example, the second current mirror circuit 512 includes: a third NPN transistor Q3 and a fourth NPN transistor Q4, the collector of the third NPN transistor Q3 is connected to the gate of the second input switch tube NM2, the emitter of the third NPN transistor Q3 is connected to the ground terminal, the collector of the fourth NPN transistor Q4 is connected to the output terminal of the second input switch tube NM2, the emitter of the fourth NPN transistor is connected to the ground terminal, the base of the fourth NPN transistor Q4 is electrically connected to the base of the third NPN transistor Q3, and the base of the fourth NPN transistor Q4 is also electrically connected to the output terminal of the second input switch tube NM2. The current mirror circuit is formed by two NPN transistors, which enhances the circuit's ability to resist noise signal interference, and the structure is simple and low in cost.

[0093] Furthermore, in order to improve the circuit's ability to resist noise signal interference, the high-voltage level shift circuit of the present application also includes a common-mode noise filtering circuit, which is electrically connected to the dual pulse shaping circuit 510, and is used to filter out the noise signals in the first inverted pulse signal and the second inverted pulse signal to obtain and output a reset signal and a set signal respectively. Wherein, the common-mode noise filtering circuit includes: a first switch tube PM1, the gate of the first switch tube PM1 is connected to the dual pulse shaping circuit 510 and a floating power supply (i.e., a high-side floating power supply VB terminal), and is used to receive the second inverted pulse signal RESET', and control the conduction or cutoff of the first switch tube PM1 through the second inverted pulse signal RESET', so that the circuit outputs a set signal SD.

[0094] The common-mode noise filtering circuit 520 also includes: a second switch tube PM2, the gate of the second switch tube PM2 is connected to the dual pulse shaping circuit 510 and the floating power supply, and is used to receive the first inverted pulse signal SET', and control the conduction or cutoff (sometimes also referred to as shutdown in this article) of the second switch tube PM2 through the first inverted pulse signal SET', wherein the input end of the first switch tube PM1 (for example, its source end) is connected to the gate of the second switch tube PM2, and the input end of the second switch tube PM2 (for example, its source end) is connected to the gate of the first switch tube PM1.

[0095] The common-mode noise filtering circuit 520 also includes a first current limiting circuit, one end of which is connected to the output end of the first switch tube PM1 (for example, the drain end of the first switch tube PM1), and the other end is connected to the floating ground end (also referred to as the high-side floating ground Vs end in this article). The output end of the first switch tube PM1 is used to output a reset signal RD; the first current limiting circuit can limit the current size of the branch to prevent excessive current from burning out devices such as the switch tube, and the first current limiting circuit can also be used as part of a voltage divider circuit.

[0096] The first current limiting circuit may adopt any suitable circuit structure capable of performing current limiting protection. Optionally, the first current limiting circuit may include at least one first resistor R6. When there are multiple first current limiting resistors, the multiple first resistors R6 are connected in series or in parallel.

[0097] The common mode noise filtering circuit 520 also includes a second current limiting circuit, one end of which is connected to the output end of the second switch tube PM2, and the other end is connected to the floating ground end. The output end of the first switch tube PM1 is used to output a third setting signal. The second current limiting circuit can limit the current size of the branch to prevent the switch tube and other devices from being burned out due to excessive current, and the second current limiting circuit can also be used as a part of the voltage divider circuit.

[0098] The second current limiting circuit may adopt any suitable circuit structure capable of performing current limiting protection. Optionally, the second current limiting circuit may include at least one second resistor R7. When there are multiple second resistors, the multiple second current limiting resistors are connected in series or in parallel.

[0099] When dV / dt noise is applied to the floating power supply VB voltage, the first switch tube PM1 and the second switch tube PM2 are both in the cut-off state, and the common-mode noise filtering circuit 520 keeps outputting the reset signal RD and the set signal SD of a low level, thereby being able to eliminate the dV / dt noise and not causing interference to the subsequent circuits, thereby effectively improving the problem of the upper and lower bridge power tubes being directly connected and causing serious damage to the system due to the dV / dt noise causing the power tube to be turned on incorrectly.

[0100] Optionally, the first switch tube PM1 and the second switch tube PM2 may be switch tubes of the same type, for example, both are NMOS or PMOS. In the embodiments of the present application, the first switch tube PM1 and the second switch tube PM2 are mainly PMOS as an example.

[0101] In one example, the high-voltage level shifting circuit further includes: a first input resistor R4 and a second input resistor R5, wherein one end of the first input resistor R4 is connected to a floating power supply and the other end is connected to a first current limiting resistor R2, and one end of the second input resistor R5 is connected to a floating power supply and the other end is connected to a second current limiting resistor R3.

[0102] Optionally, the first input resistor R4 and the second input resistor R5 may have the same resistance value, which may be realized by one or more resistors. The first input resistor R4 and the second input resistor R5 may be used as voltage-dividing resistors, for example, the first input resistor R4 and the first current-limiting resistor R2 may constitute a voltage-dividing circuit, and the voltage-dividing node may be arranged between the first input resistor R4 and the first current-limiting resistor R2 to output the first inverted pulse signal SET', wherein a high-level signal is output when the branch where the first input resistor R4 and the first current-limiting resistor R2 are located is turned on, and a low-level signal is output when it is turned off. Similarly, the second input resistor R5 and the second current-limiting resistor R3 may constitute a voltage-dividing circuit, and the voltage-dividing node may be arranged between the second input resistor R5 and the second current-limiting resistor R3 to output the second inverted pulse signal RESET', wherein a high-level signal is output when the branch where the second input resistor R5 and the second current-limiting resistor R3 are located is turned on, and a low-level signal is output when it is turned off. Therefore, the first input resistor R4 and the second input resistor R5 can play the role of current limiting protection and voltage division, thereby ensuring the normal output of the reset signal and the set signal generated by the circuit.

[0103] In one example, the high-voltage level shift circuit of the present application also includes a voltage stabilizing circuit, and the first input resistor and the second input resistor are respectively connected in parallel with a voltage stabilizing circuit 531 and 532, wherein each voltage stabilizing circuit includes at least two diodes connected in series, and the negative pole of a diode is electrically connected to a floating power supply. The diode operates under reverse bias conditions. When the reverse voltage is lower than the breakdown voltage of the diode (also called the Zener voltage or the stabilizing value), the voltage stabilizing circuit is almost non-conductive. Once the reverse voltage reaches or exceeds the stabilizing value, the diode will enter the breakdown region. At this time, the current will increase significantly, but the voltage across the diode will remain almost unchanged. This stable voltage value is the stabilizing value of the diode. By connecting at least two diodes in series, the voltage stabilizing value of the voltage stabilizing circuit can be improved, and it can also play a role in reverse current limiting protection.

[0104] For example, Figure 5 As shown, the first voltage stabilizing circuit 531 connected in parallel with the first input resistor R4 includes a first diode D1 and a second diode D2 connected in series, wherein the anode of the first diode D1 is connected to one end where the first input resistor R4 and the first current limiting resistor R2 are connected, the cathode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is electrically connected to the floating power supply. The second voltage stabilizing circuit 52 connected in parallel with the second input resistor R5 includes a third diode D3 and a fourth diode D4 connected in series, wherein the anode of the third diode D3 is connected to one end where the second input resistor R5 and the second current limiting resistor R3 are connected, the cathode of the fourth diode D4 is connected to the anode of the fourth diode D4, and the cathode of the fourth diode D4 is electrically connected to the floating power supply VB.

[0105] The first diode D1 , the second diode D2 , the third diode D3 , and the fourth diode D4 may be Zener diodes or other suitable types of diodes.

[0106] It is worth mentioning that in the present application, the so-called "state where component A is connected to component B" includes not only the case where component A and component B are physically directly connected, but also the case where component A and component B are indirectly connected via other components that do not substantially affect their electrical connection state or do not damage the function or effect achieved by their coupling, such as indirect connection via a resistor or a diode.

[0107] The first input switch tube and the second input switch tube of the present application can be high-voltage components, such as transistors with a DMOS (Double-Diffused MOS) structure, but transistors with other structures can also be used, such as HVMOS (High Voltage MOSFET), LDMOS (Lateral Diffusion MOSFET), IGBT (Insulated Gate Bipolar Transistor), SiC (Silicon Carbide)-JFET, SIC-MOSFET, etc. Regarding other transistors that are not specifically marked as high-voltage components, they can be MOSFETs with normal voltage resistance.

[0108] The following will be combined Figure 6The timing diagram shown describes the working principle of the high-voltage level shift circuit of the present application, wherein, in the absence of dV / dt noise, when the first pulse signal SET is at a high level and the second pulse signal RESET is at a low level, the first input switch tube NM1 is turned on and the second input switch tube NM2 is turned off. Therefore, the generated first inverted pulse signal SET' is at a high level, so that the first switch tube PM1 is turned off, and the generated second inverted pulse signal RESET' is at a low level, so that the second switch tube PM2 is turned on. When the first switch tube PM1 is turned off, the RD signal is set low, and when the second switch tube PM2 is turned on, the SD signal is set high, thereby ensuring the normal output of the signal. When dV / dt noise is applied to VB, the same voltage drop is generated across the first input resistor R4 and the second input resistor R5, that is, the voltage applied to the source terminal and the gate of the first switch tube PM1 are equal, and the voltage applied to the source terminal and the gate of the second switch tube PM2 are equal, then the gate-source voltage VGS of the first switch tube PM1 is equal to zero, and the gate-source voltage VGS of the second switch tube PM2 is also equal to zero, the first switch tube PM1 and the second switch tube PM2 are both in the cut-off region, and the voltage of the first resistor R6 and the second resistor R7 is VS, that is, the reset signal RD and the set signal SD of low level are output, so the dV / dt noise is eliminated and will not cause interference to the subsequent circuit.

[0109] When interference noise is applied to the first pulse signal SET and the second pulse signal RESET, due to the NPN transistors connected in series to the sources of the first input switch tube NM1 and the second input switch tube NM2, the turn-on thresholds of the first input switch tube NM1 and the second input switch tube NM2 are also increased, and the interference signal introduced by the ground voltage GND and the power supply voltage VCC is shielded at the source ends of the first input switch tube NM1 and the second input switch tube NM2. Compared with the traditional structure, as long as the level of the first pulse signal VSET or the level of the second pulse signal RESET is greater than the threshold voltage Vth, the first input switch tube NM1 and the second input switch tube NM2 will be turned on. However, the circuit structure of the present invention requires that the narrow pulse meets the predetermined pulse width and amplitude in order to turn on the first input switch tube NM1 and the second input switch tube NM2. Since the pulse width and amplitude of the noise signal are usually lower than those of the normal signal in the pulse signal, the noise signal cannot drive the first input switch tube NM1 and the second input switch tube NM2 to turn on, thereby filtering out the interference signal.

[0110] Although the high-voltage level shift circuit in the above embodiment can improve the noise problem in the pulse signal, since the high-voltage gate driver chip drives inductive loads in many application fields, an important characteristic of inductive loads is that the current cannot change suddenly. The IPM module generally uses 2, 4 or 6 power tubes to form a half-bridge, full-bridge, or three-phase circuit drive structure to meet the driving requirements of various motors. Taking the half-bridge circuit structure as an example, Figure 7 As shown, under the rapid turn-off change of the power tube IGBT1, the current on the load inductor L_load cannot change suddenly, forcing the parasitic inductors L3, L4 and the reverse recovery diode D2 of the power tube IGBT2 to form a current freewheeling loop. The high-side floating ground VS end of the HVIC driver chip will generate a considerable negative overshoot voltage. The high-side floating power supply VB end is connected to the high-side floating ground VS end through an external bootstrap capacitor, so the voltage of the VB end will follow the voltage change of VS and decrease with the VS voltage. This situation will cause strong interference to the high-voltage level shift circuit and subsequent logic module circuit of the HVIC, resulting in false start and false shutdown. When the negative overshoot voltage of the VS voltage reaches 15V, this causes the HVIC power supply voltage VB to reach below 0V. When the VB voltage is less than the reference ground GND, the parasitic diode between the high-voltage well and the substrate is forced to turn on, that is, the parasitic diode from GND to VB, so that the current flows through the substrate. The substrate current may cause the high-end drive circuit to latch, resulting in a direct short circuit between the upper and lower bridges IGBT1 and IGBT2, resulting in excessive power consumption and burning of the device. When the reset signal RD and the set signal SD output by the high-voltage level shift circuit pass through the noise elimination circuit to eliminate the DV / DT common mode noise and differential mode noise, the RD' and SD' signals are obtained. However, as the input pulse width becomes smaller and smaller, the IGBT1 turns off faster, and the VS negative overshoot overlaps with the set signal RESET, which still causes the set signal SD to be mistakenly triggered as a valid high-level signal, causing the latch RS_LATCH to latch incorrectly, resulting in false triggering. When the VS negative overshoot phenomenon occurs, VB will change with VS. If VB<0, the parasitic diode of GND to VB will be forward turned on to charge the external capacitor at the VB end; if VB>0, the parasitic diode of GND to VB will be closed. According to the diode characteristics, reverse recovery current will be generated. Figure 8 It shows the working state of the high voltage level shift circuit when the first pulse signal SET = 0 and the second pulse signal RESET = 1. The reverse recovery currents IRS and IRR flow to the parasitic diodes D11 and D22 respectively. When there is no edge trigger circuit, the circuit timing diagram is as follows Fig.9AAs shown in the figure, when the second pulse signal RESET is active high and overlaps with the negative voltage of VS, IRS > IRR and VR4 > VR5. Since VSET’ = VB - VR4 and VRESET’ = VB - VR5, then VSET’ < VRESET’, which causes PM1 to turn off and PM2 to turn on. As a result, the reset signal RD output by the high-voltage level shift circuit is set to a low level, and the set signal SD is set to a high level. Then, the set signal (RS_LATCH SET) input to the latch RS_LATCH is also at a high level, while the reset signal (RS_LATCH RESET) input to the latch RS_LATCH is at a low level. Consequently, the RS_LATCH latches an incorrect signal (for example, outputs a high-level signal, while actually according to the initial first and second pulse signals, at this time period, the RS_LATCH latch should output a low level and not trigger the IGBT1 to turn on), leading to an incorrect turn-on trigger.

[0111] To solve the above technical problems, the present application provides a trigger circuit that can receive the set signal and reset signal output by the high-voltage level shift circuit, or receive the filtered set signal and reset signal output by the noise cancellation circuit, as Fig. 9B can be seen from the circuit timing diagram shown. By setting this trigger circuit, when RESET is active high (i.e., a valid high level) and does not overlap with the negative voltage of VS, IRS ≈ IRR, VR4 ≈ VR5, VSET’ ≈ VRESET’, which causes PM1 to turn off and PM2 to turn off, sets RD to low, and sets SD to low, thereby enabling the latch RS_LATCH to maintain the latch and avoiding incorrect triggering.

[0112] Specifically, the trigger circuit of the present application will be described below with reference to Figures 10 to 12 the following.

[0113] As an example, as Fig.10As shown, the trigger circuit of the present application includes two edge trigger circuits for processing the reset signal RD and the set signal SD respectively, wherein each edge trigger circuit includes: a first pulse modulator 1010, the input end of the first pulse modulator 1010 is used to receive the first drive signal, and delay and filter the first drive signal to obtain the second drive signal RDB, wherein the first drive signal is the reset signal RD or the set signal SD; a rising edge trigger DFF1, whose input end is used to receive the first drive signal, and process the first drive signal to obtain the first output signal Q1, wherein the rising edge in the first drive signal triggers the rising edge trigger to make the first output signal Q1 a high level; a falling edge trigger DFF 2, whose input end is connected to the first pulse modulator 1010, for receiving the second drive signal and processing to obtain the second output signal, wherein the falling edge in the second drive signal RDB triggers the falling edge trigger DFF2 to make the second output signal Q2 high level; the logic operation circuit 1030, which is electrically connected to the rising edge trigger DFF1 and the falling edge trigger DFF2, is used to operate the received first output signal Q1 and the second output signal Q2 to obtain the target drive signal RD' and send it to the latch, so that the latch outputs a switch signal to drive the device to be driven to turn on or off, wherein when a noise signal appears in the first output signal Q1, the target drive signal RD' is output as a latch signal to the latch, so that the latch latches and maintains. Through the trigger circuit of the present application, the false triggering of the device to be driven caused by the noise signal caused by the negative voltage of VS and the narrow pulse width of the input signal can be improved, and a clean drive signal can be output, which solves the problem of the latch effect of the drive caused by the false triggering of the device, which may cause serious damage to the system.

[0114] Since the edge trigger circuit structure used for processing the set signal and the reset signal in the trigger circuit is the same, the following mainly uses the edge trigger circuit used for processing the reset signal as an example for explanation and description.

[0115] The first pulse modulator 1010 may be any suitable modulator that can filter out signals with a certain noise width and play a role in pulse modulation.

[0116] In one example, the first pulse modulator 1010 can be implemented as follows Fig.11In the structure shown, the first pulse modulator 1010 includes a signal shaping circuit 1011, which is used to receive a first drive signal (that is, the input terminal VIN receives, for example, a reset signal RD or a set signal SD), and shapes the first drive signal to obtain a square wave signal; for example, the signal shaping circuit 1011 is connected in series with at least two inverters INV, and the first drive signal obtains a square wave signal after passing through the inverter INV, that is, a relatively ideal square wave signal. By utilizing the oscillation characteristics of the inverter INV, the output signal of the inverter is continuously switched between high and low levels, thereby generating a relatively ideal square wave signal. Optionally, the inverter can be a CMOS inverter or a TTL inverter, or other suitable inverters.

[0117] In one example, if Fig.11 As shown, the first pulse modulator also includes a filtering circuit 1012 and a Schmitt trigger SMIT. The filtering circuit 1012 is connected to the signal shaping circuit 1011 and is used to filter the square wave signal to obtain a filtered signal. The Schmitt trigger SMIT is connected to the filtering circuit 1012 and is used to filter out the noise signal in the filtered signal and output a second driving signal.

[0118] For example, the filter circuit 1012 can be an RC filter circuit or other suitable types of circuits. The filter circuit 1012 can be used to make the rising edge of the square wave signal output by the signal shaping circuit slow, so that it can be beneficial to output a stable input signal to the subsequent Schmitt trigger, reduce the false triggering of the Schmitt trigger SMIT due to the rapid change of the signal, and, because the pulse width of the noise signal and the normal pulse signal are different, they will have different performances when passing through, for example, the RC filter circuit, and the noise signal is often narrower, so the voltage accumulated on the capacitor of the RC filter circuit may not be enough to trigger the subsequent circuit (such as the Schmitt trigger). The normal pulse signal can accumulate enough voltage on the capacitor to trigger the subsequent circuit due to its large width. In this way, the RC charging circuit plays the role of filtering and shaping, removes the noise signal, and retains the normal pulse signal.

[0119] In a specific example, the filtering circuit 1012 includes: a charging resistor R1, a capacitor C1 and a switch module, the charging resistor R1 is connected to one end of the capacitor C1, and the square wave signal output by the signal shaping circuit 1011 is used to control the conduction or shutdown of the switch module so that the power supply voltage VCC charges the capacitor C1 through the charging resistor R1 or the capacitor C1 discharges through the switch module. For example, the switch module includes a first switch tube P1 and a second switch tube N1, wherein the gate of the first switch tube P1 is connected to a signal shaping circuit 1011 for receiving a first drive signal, and the gate of the second switch tube N1 is connected to a signal shaping circuit 1011 for receiving a first drive signal, wherein the first switch tube P1 and the second switch tube N1 are connected in series between a power supply voltage VCC and a ground terminal GND, one end of the first switch tube P1 is connected to a power supply, and one end of the second switch tube N1 is connected to a ground terminal; the first switch tube P1 and the second switch tube N1 are connected via a charging resistor R1, wherein the first switch tube P1 and the second switch tube N1 are different types of switch tubes, and the two are not turned on at the same time, for example, the first switch tube is a PMOS, and the second switch tube is an NMOS. Specifically, the source terminal of the first switch tube P1 is connected to the power supply voltage VCC, the drain terminal of the first switch tube P1 is connected to the drain terminal of the second switch tube N1 via the charging resistor R1, and the source terminal of the second switch tube N1 is connected to the ground terminal GND. The capacitor C1 is connected in parallel with the second switch tube N1, and the capacitor C1 is also connected to a Schmitt trigger SMIT, wherein the square wave signal output by the signal shaping circuit 1011 controls the first switch tube P1 to be turned on, and when the second switch tube N1 is turned off, the power supply voltage VCC charges the capacitor C1 through the charging resistor R1, and when the voltage of the capacitor C1 is higher than the first flip level of the Schmitt trigger SMIT, the Schmitt trigger SMIT outputs a high level signal, and when the voltage of the capacitor C1 is lower than the second flip level, the Schmitt trigger outputs a low level signal, wherein the first flip level is higher than the second flip level.

[0120] Specifically, firstly, the structure of the charging circuit in the RC filter circuit is used, that is, when the first switch tube P1 is turned on, for example, when the signal shaping circuit 1011 outputs a low-level signal, the first switch tube P1 is turned on, and the voltage of the power supply VCC charges the capacitor C1 through the charging resistor R1, thereby changing the rising slope of the pulse signal, and changing the original fast-changing pulse signal into a slowly rising signal. If the normal input signal is mixed with a noise signal, but because the width of the noise signal is different from the normal short pulse signal width, the maximum voltage reached by the capacitor C1 is different. When the input pulse signal arrives, the capacitor C1 is charged through the charging resistor R1. If the voltage charged on the capacitor C1 can reach the first flip level of the post-stage Schmitt trigger, this signal is a normal pulse signal and will be received by the post-stage circuit. At this time, the RC circuit plays a shaping role. If the voltage on the capacitor C1 still does not reach the first flip level of the post-stage Schmitt trigger at this time, this signal is a noise signal, which will not be received by the post-stage circuit, and the circuit state will not change. Therefore, this circuit can filter out noise signals with a certain noise width and achieve the purpose of pulse modulation.

[0121] The Schmitt trigger SMIT can be composed of multiple electronic components, including but not limited to CMOS inverters, resistors, diodes and transistors. For example, two CMOS inverters can be connected in series, and the voltage at the output end can be fed back to the input end through a voltage divider resistor, thereby forming a circuit with Schmitt trigger characteristics. Specifically, the present application does not limit the structure of the Schmitt trigger.

[0122] The Schmitt trigger SMIT has two different threshold voltage levels (i.e., the first flip level and the second flip level mentioned above), i.e., the first flip level is a rising threshold (positive threshold) and the second flip level is a falling threshold (negative threshold). When the input signal exceeds the rising threshold, the output changes from a low level to a high level; when the input signal is lower than the falling threshold, the output changes from a high level to a low level. This dual threshold structure makes the Schmitt trigger more sensitive to changes in the input signal and can resist noise interference to a certain extent.

[0123] In one example, the first pulse modulator 1010 may also include an output inverter INV, which is connected to a Schmitt trigger SMIT and is used to invert the signal output by the Schmitt trigger SMIT, thereby outputting a signal having the same phase as the signal input into the first pulse modulator. However, due to the processing by the inverter and the RC filtering circuit, the signal output from the first pulse modulator has a certain delay compared to the signal input into the first pulse modulator.

[0124] Further, the rising edge trigger DFF1 of the present application has an input end for receiving a first drive signal such as a reset signal RD, and processes the first drive signal to obtain a first output signal Q1, wherein the rising edge in the first drive signal triggers the rising edge trigger to make the first output signal Q1 high level, and the rising edge trigger DFF1 can ensure that the input signal is read at the beginning of each clock cycle, thereby achieving accurate timing control, that is, the rising edge of the first drive signal (that is, the moment from low level to high level) triggers. Optionally, the rising edge trigger DFF1 can be any suitable trigger, for example, it can be a D trigger, and the D trigger can include a clock input end (CLK) for receiving a clock signal and controlling the trigger timing of the trigger. When the rising edge (or falling edge, depending on the type of trigger) of the clock signal arrives, the trigger will update its output according to the data state of the D end, and the D trigger also includes a data input (D) end for receiving data to be stored. When the trigger edge of the clock signal arrives, the data at the D end will be transmitted to the output end of the trigger. It also includes an output (Q) end: for outputting the current state of the trigger. The state of the trigger (0 or 1) will be updated according to the data at the D end when the trigger edge of the clock signal arrives, and maintained at the Q end output. It can also have a reset (R) port to force the output of the trigger to 0.

[0125] The rising edge trigger DFF1 may include a plurality of NAND gates or other logic gate circuits for realizing the logic function of the trigger, which is not specifically limited here.

[0126] Furthermore, the falling edge trigger DFF2 of the present application has its input end connected to the first pulse modulator 1010, and is used to receive the second drive signal output by the first pulse modulator 1010 and process it to obtain the second output signal Q2, wherein the falling edge in the second drive signal triggers the falling edge trigger DFF1 to make the second output signal Q2 high level; before the falling edge of the clock signal arrives, the falling edge trigger is in a waiting state. However, when the falling edge of the clock signal arrives, the falling edge trigger updates the output state according to the current input signal (or internal state), and then keeps the state unchanged until the falling edge of the next clock signal arrives.

[0127] The falling edge trigger DFF1 can have better anti-interference ability because the falling edge is usually steeper than the rising edge, so it is easier to be identified and processed, thereby reducing the possibility of false triggering.

[0128] The falling edge trigger DFF1 can also be implemented based on a D trigger, which can also specifically have a D terminal, a Q terminal, a CLK terminal and an R terminal.

[0129] Furthermore, the trigger circuit of the present application also includes a logic operation circuit 1030, which is electrically connected to the rising edge trigger DFF1 and the falling edge trigger DFF2, and is used to operate the received first output signal Q1 and the second output signal Q2 to obtain a target drive signal and send it to the latch, so that the latch outputs a switching signal to drive the device to be driven to turn on or off, wherein when a noise signal appears in the first output signal, the target drive signal is output as a latch signal to the latch, so that the latch is latched and maintained.

[0130] Optionally, the logic operation circuit 1030 may be an AND gate or other suitable circuits, and the first output signal output by the rising edge trigger and the second output signal output by the falling edge trigger may be comprehensively processed by the logic operation circuit 1030, thereby generating a more stable and reliable target drive signal. For example, when there is high-level noise in the first input signal, and the second input signal is low-level at this time, the AND gate is used to output a low-level signal, so that the noise signal will not be output to the next stage circuit.

[0131] The circuit of the AND gate can be implemented in many ways, such as using CMOS logic, NMOS logic, PMOS logic, and diodes. Taking CMOS logic as an example, the AND gate is usually composed of a combination of PMOS transistors and NMOS transistors, and the "AND" operation is realized by controlling the conduction and cutoff of the transistors, and no specific limitation is made here.

[0132] In one example, each edge trigger circuit further includes: a second pulse modulator 1020, the second pulse modulator 1020 is connected to the reset signal input terminal R of the rising edge trigger DFF1 and the reset signal input terminal R of the falling edge trigger DFF2, and is used to process the target drive signal into a trigger reset signal to reset the rising edge trigger DFF1 and the falling edge trigger DFF2, so that the rising edge trigger DFF1 and the falling edge trigger DFF2 output a low level signal. The reset operation of the trigger can be implemented through the second pulse modulator 1020, thereby ensuring that the circuit finally outputs the target drive signal corresponding to the input signal.

[0133] The second pulse modulator 1020 may have the same structure as or a different structure from the first pulse modulator 1010 , and no specific limitation is given here.

[0134] Specifically, it will be combined Fig.12The circuit timing of the edge-triggered circuit is described, wherein, when a signal pulse of the reset signal RD comes, the rising edge of the pulse triggers the rising edge trigger, so that the output end of the rising edge trigger outputs the first output signal Q1. At this time, Q1=D=VCC, and the storage state of the rising edge trigger is a high level; the reset signal RD is delayed and filtered by the first pulse modulator PULSE MOD to obtain the second output signal RDB signal, and the falling edge of the pulse triggers the falling edge trigger DFF2, so that Q2=D=VCC, and the storage state of the falling edge trigger DFF2 is a high level. Since they are both high levels, they are still high levels after passing through a logic operation circuit such as an AND gate, so the RD' signal output by the edge trigger is a high level. After passing through the second pulse modulator, a trigger reset signal R is obtained, so that the rising edge trigger DFF1 and the falling edge trigger DFF2 enter the reset state and output a low level. After passing through a logic operation circuit such as an AND gate, the RD' signal is set to a low level. The pulse width of the signal output by the pulse modulator (for example, the first pulse modulator and the second pulse modulator) can be adjusted by adjusting the charging resistor R1 or the capacitor C1. When the pulse width is less than a certain value, it can be determined as a noise (NOISE) signal, so that the second output signal RDB does not respond to the noise signal, and thus the noise signal cannot be read in, thereby avoiding false triggering.

[0135] In summary, the trigger circuit of the present application can improve the anti-noise capability and avoid false triggering.

[0136] Further, if Fig.13 As shown, the present application also provides a gate drive chip, which includes a high-side gate drive chip HVIC. The gate drive chip can be a PWM drive chip or an ordinary drive chip, wherein the PWM drive chip is a drive chip that can transmit three-phase pulse signals of U phase, V phase and W phase, and the ordinary drive chip usually only transmits one pulse signal. Compared with the ordinary drive chip, the number of signal input ports of the PWM drive chip itself (hereinafter referred to as IO port) is two more than the signal input ports of the ordinary chip.

[0137] The gate drive chip includes a pulse generating circuit 1310, which is used to encode the rising edge and the falling edge of the received PWM pulse width modulation signal into a first pulse signal SET and a second pulse signal RESET respectively. The pulse generating circuit 1310 may include a filtering and shaping circuit, a low-voltage level shifting circuit and a narrow pulse generating circuit. The filtering and shaping circuit receives the PWM pulse width modulation signal and filters and shapes it; the low-voltage level shifting circuit is used to process the PWM pulse width modulation signal to obtain a level shifting signal; the narrow pulse generating circuit is used to encode the rising edge and the falling edge in the level shifting signal into a first pulse signal and a second pulse signal respectively. The narrow pulse generating circuit can accurately control the triggering time of the signal and realize high-precision timing control.

[0138] Optionally, the filtering and shaping circuit may include a Schmitt trigger SMIT and an input signal filter INPUTFILTER.

[0139] Specifically, Fig.13 The circuit structure of the high-voltage gate driver chip shown in the figure has three voltage domains, which are divided into a low-voltage area, an operating voltage area, and a high-voltage area. The power supply VDD in the low-voltage area is provided by the operating voltage VCC through the linear load regulator REG, mainly for compatibility with the upper-level driving capability. The power supply in the high-voltage area is provided by the operating voltage VCC through a bootstrap boost circuit, mainly for compatibility with driving the lower-level load. The output control signal directly drives the gate of the power tube. In order to ensure the normal operation of the circuit function, both the high-voltage area and the operating voltage area require undervoltage protection circuits, which are HSUVLO and LSUVLO respectively. Except for the device type, the circuit structure and parameters of the two circuits are the same. The devices in the high-voltage area must be replaced with isolation devices because they are integrated in the high-voltage isolation island.

[0140] HIN receives a PWM pulse width modulation signal from a controller such as an MCU. The input signal is a 3.3V CMOS level or a 5V TTL level. After the signal is filtered and shaped by a Schmitt trigger SMIT and an input signal filter INPUT FILTER, a clean signal HIN_PWM is obtained. After the signal passes through a level shift circuit (LS_L2H), it is transferred from a low voltage area to a working voltage area, and an LS_PWM signal (also known as a level shift signal) is output. The narrow pulse generating circuit (PULSE GEN) encodes the rising edge and falling edge of the high side signal of the LS_PWM signal into two narrow pulse signals, namely, a first pulse signal PWM1 and a second pulse signal PWM2.

[0141] Further, if Fig.13As shown, the high-voltage gate driver chip of the present application also includes a high-voltage level shift circuit 1320, which can be implemented as the high-voltage level shift circuit in the aforementioned embodiment, thereby having the function of the aforementioned high-voltage level shift circuit to resist noise signal interference.

[0142] The narrow pulse signal is used as the gate input of two high-voltage LDMOS (such as the first input switch tube and the second input switch tube mentioned above) of the high-voltage level shift circuit (LEVEL_SHIFTER), and two inverse phase narrow pulse signals are generated at the drain end of the high-voltage LDMOS, and then after passing through the common mode noise filtering circuit, a reset signal RD and a set signal SD are generated. The signal is shifted from the working voltage area to the high voltage area through the high-voltage level shift circuit 1320.

[0143] In one example, a noise cancelling circuit 1330 is further included, one end of which is connected to the high-voltage level shifting circuit 1320, and the other end is connected to the trigger circuit, for filtering the reset signal RD and the set signal SD for noise removal and then outputting them to the trigger circuit 1340. After the reset signal RD and the set signal SD pass through the noise cancelling circuit (NOISE CANCELLER), the differential mode noise in the signal is filtered out to obtain RD' and SD' signals.

[0144] In one example, the trigger circuit (EDGE TRIGGER) in the aforementioned embodiment is also included, and the RD' and SD' signals pass through the edge trigger circuit (EDGE TRIGGER) to prevent false triggering caused by the negative voltage of VS and the narrow pulse width of HIN, thereby obtaining a clean signal.

[0145] In one example, a latch 1350 and a drive circuit 1360 are also included. The latch 1350 is electrically connected to the trigger circuit 1340, and is used to process the signal output by the trigger circuit 1340 to obtain a switch signal to drive the device to be driven to turn on or off. The drive circuit 1360 is connected to the gate of the target switch tube (for example, the high-side power tube IGBT1) to drive the target switch tube to turn on or off. The drive circuit (DRIVER) 1360 includes the device to be driven, and the output end of the latch 1350 is connected to the gate of the device to be driven. The device to be driven is a switch tube. The switch tube is controlled to be turned on or off by the signal output by the latch 1350, thereby controlling the drive circuit 1360 to be turned on or off. In a specific example, the latch 1350 restores the signal output by the trigger circuit 1340 to a normal floating voltage switch signal and outputs it to the drive circuit to control the drive circuit to be turned on or off, thereby obtaining a HO signal. The HO signal is output to the high-side power tube IGBT1 through the driving circuit 1360 to realize the on / off of the high-side power tube IGBT1.

[0146] Optionally, the latch 1350 may be an RS latch, which may be a low-level effective trigger, which may include a first trigger terminal S, a second trigger terminal R, and a trigger output terminal Q. Optionally, the first trigger terminal S receives the above-mentioned SD' signal and changes its level state. The second trigger terminal R receives the above-mentioned RD' signal and changes its level state. The trigger output terminal Q outputs a control signal (i.e., a switch signal) of the driving circuit according to the level state of the first trigger terminal S and the level state of the second trigger terminal R.

[0147] Specifically, the structure of the driving circuit 1360 can adopt any suitable circuit, which is not specifically limited here.

[0148] Since the gate driving chip of the present application has the aforementioned high-voltage level shift circuit and / or the aforementioned edge trigger circuit, it has the same advantages as the aforementioned high-voltage level shift circuit and / or the aforementioned edge trigger circuit.

[0149] The present application also provides an intelligent power module, comprising the aforementioned gate drive chip.

[0150] The gate driver chip of the present application is a high-voltage gate driver chip, which belongs to a high-side gate driver chip and is used in an intelligent power module (IPM). Optionally, three single-channel high-side gate driver chips, one three-channel low-side gate driver chip and six power tubes can be sealed together in the IPM for driving a three-phase motor. It can be used in electric vehicles, household appliances and industrial equipment, for example.

[0151] by Figure 2 Taking the intelligent power module with a half-bridge circuit structure in as an example, it includes a high-side gate driver chip HVIC and a low-side gate driver chip LVIC. Among them, the high-side gate driver chip HVIC outputs a high-voltage drive output HO signal to control the high-side power tube IGBT1. The low-side gate driver chip LVIC outputs a low-voltage drive output LO signal to control the low-side power tube IGBT2.

[0152] Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are connected in series between the DC voltage VH and the ground voltage. The voltage at the connection point between the high-side power tube IGBT1 and the low-side power tube IGBT2 is the high-side floating ground VS terminal Vs. Optionally, the high-side power tube IGBT1 and the low-side power tube IGBT2 are turned on alternately.

[0153] Since the IPM of the present application has the aforementioned gate driving chip, it also has the advantages of the aforementioned gate driving chip.

[0154] Furthermore, the present application also provides a device, which may include the aforementioned trigger circuit, or, include the aforementioned gate drive chip, or, include the aforementioned intelligent power module.

[0155] The device can be any electronic product or device such as household appliances (such as variable frequency air conditioners), televisions, mobile phones, tablet computers, laptop computers, netbooks, game consoles, televisions, VCDs, DVDs, navigators, cameras, video cameras, voice recorders, MP3s, MP4s, PSPs, etc., or the device can also be transportation equipment such as vehicles.

[0156] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented with the aid of hardware including several different elements and with the aid of appropriately programmed computers. In a unit claim listing several on-board systems, several of these on-board systems may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0157] The above is only a specific implementation method or description of a specific implementation method of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A high voltage level shift circuit, characterized in that: The high voltage level shift circuit comprises: A double pulse shaping circuit, used for shaping and inverting the received first pulse signal and the second pulse signal respectively, to obtain a first inverted pulse signal and a second inverted pulse signal; A common mode noise filtering circuit, electrically connected to the dual pulse shaping circuit, for filtering noise signals in the first inverted pulse signal and the second inverted pulse signal to obtain and output a reset signal and a set signal respectively; Wherein, the common mode noise filtering circuit comprises: a first switch tube, wherein the gate of the first switch tube is connected to the double pulse shaping circuit and the floating power supply, and is used to receive the second inverted pulse signal, and control the on or off of the first switch tube through the second inverted pulse signal; a second switch tube, the gate of which is connected to the double pulse shaping circuit and the floating power supply, and is used to receive the first inverted pulse signal, and control the conduction or cutoff of the second switch tube by the first inverted pulse signal, wherein the input end of the first switch tube is connected to the gate of the second switch tube, and the input end of the second switch tube is connected to the gate of the first switch tube; A first current limiting circuit, one end of which is connected to the output end of the first switch tube, and the other end of which is connected to a floating ground end, wherein the output end of the first switch tube is used to output the reset signal; The second current limiting circuit has one end connected to the output end of the second switch tube and the other end connected to the floating ground end. The output end of the first switch tube is used to output the setting signal.

2. The high voltage level shift circuit according to claim 1, wherein: The double pulse shaping circuit comprises: A first pulse shaping circuit, wherein the first pulse shaping circuit is used to shape and invert the received first pulse signal and output a first inverted pulse signal, wherein the first pulse shaping circuit comprises: A first input switch tube, wherein the gate of the first input switch tube is used to receive the first pulse signal; a first current limiting resistor, one end of which is connected to the input end of the first input switch tube, and the other end of which is connected to the gate of the second switch tube, and is used to output the first inverted pulse signal to the second switch tube; A first current mirror circuit is coupled between the output terminal and the gate of the first input switch tube.

3. The high voltage level shift circuit according to claim 2, characterized in that: The first current mirror circuit comprises: A first NPN transistor, wherein the collector of the first NPN transistor is connected to the gate of the first input switch tube, and the emitter of the first NPN transistor is connected to the ground terminal; A second NPN transistor, wherein the collector of the second NPN transistor is connected to the output end of the first input switch tube, the emitter of the second NPN transistor is connected to the ground end, the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the base of the second NPN transistor is also electrically connected to the output end of the first input switch tube.

4. The high voltage level shift circuit according to claim 2, wherein: The double pulse shaping circuit comprises: A second pulse shaping circuit, wherein the second pulse shaping circuit is used to shape the received second pulse signal and output the shaped second inverted pulse signal, wherein the second pulse shaping circuit comprises: A second input switch tube, wherein the gate of the second input switch tube is used to receive the second pulse signal; a second current limiting resistor, one end of which is connected to the input end of the second input switch tube, and the other end of which is connected to the gate of the first switch tube, for outputting the second inverted pulse signal to the first switch tube; A second current mirror circuit is coupled between the output terminal and the gate of the second input switch tube.

5. The high voltage level shift circuit according to claim 4, characterized in that: The second current mirror circuit comprises: a third NPN transistor, wherein the collector of the third NPN transistor is connected to the gate of the second input switch tube, and the emitter of the third NPN transistor is connected to the ground terminal; A fourth NPN transistor, wherein the collector of the fourth NPN transistor is connected to the output end of the second input switch tube, the emitter of the fourth NPN transistor is connected to the ground end, the base of the fourth NPN transistor is electrically connected to the base of the third NPN transistor, and the base of the fourth NPN transistor is also electrically connected to the output end of the second input switch tube.

6. The high voltage level shift circuit according to claim 4, characterized in that: Also includes: a first input resistor, one end of the first input resistor being connected to the floating power supply, and the other end of the first input resistor being connected to the first current limiting resistor; as well as A second input resistor, one end of the second input resistor is connected to the floating power supply, and the other end is connected to the second current limiting resistor.

7. The high voltage level shift circuit according to claim 6, characterized in that: Also includes: A voltage stabilizing circuit, wherein the first input resistor and the second input resistor are respectively connected in parallel with one of the voltage stabilizing circuits, wherein each of the voltage stabilizing circuits comprises at least two diodes connected in series, and a cathode of one of the diodes is electrically connected to the floating power supply.

8. A gate driver chip, characterized in that: include: A pulse generating circuit, used for encoding the rising edge and the falling edge in the received PWM pulse width modulation signal into a first pulse signal and a second pulse signal respectively; The high-voltage level shift circuit according to any one of claims 1 to 7, wherein the high-voltage level shift circuit is electrically connected to the pulse generating circuit for receiving the first pulse signal and the second pulse signal.

9. The gate driving chip according to claim 8, characterized in that: Also includes: The noise elimination circuit is electrically connected to the high-voltage level shift circuit and is used for receiving and filtering out differential mode noise in the set signal and the reset signal.

10. The gate driving chip according to claim 9, characterized in that: Also includes: a trigger circuit, the trigger circuit being electrically connected to the noise elimination circuit, and being used for receiving a signal output by the noise elimination circuit, and processing the signal output by the noise elimination circuit to obtain a target drive signal, and when a noise signal appears in the signal output by the noise elimination circuit, the target drive signal is output as a latch signal; A latch, the latch being electrically connected to the trigger circuit, and configured to receive the target drive signal and process the target drive signal to obtain a switch signal to drive the device to be driven to be turned on or off; A driving circuit, wherein the driving circuit is connected to the gate of the target switch tube and is used to drive the target switch tube to be turned on or off, wherein the driving circuit includes the device to be driven, and the output end of the latch is connected to the gate of the device to be driven.

11. The gate driving chip according to claim 8, characterized in that: The pulse generating circuit comprises: A filtering and shaping circuit, wherein the filtering and shaping circuit receives the PWM pulse width modulation signal and performs filtering and shaping on the PWM signal; A level shift circuit, used for processing the PWM pulse width modulation signal to obtain a level shift signal; The narrow pulse generating circuit is used for encoding the rising edge and the falling edge in the level shift signal into the first pulse signal and the second pulse signal respectively.

12. An intelligent power module, characterized in that: Comprising the gate driving chip as claimed in any one of claims 8 to 11.

13. A device, characterized in that: It comprises the trigger circuit as claimed in any one of claims 1 to 7, or comprises the gate drive chip as claimed in any one of claims 8 to 11, or comprises the intelligent power module as claimed in claim 12.

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