Method and device for determining phase difference value
By randomly selecting the output clock signal in PPADPLL and determining the ideal delay time according to the value of the decimal part, adjusting the phase of the output clock signal, the problem of spur in the phase noise curve when the FCW is decimal is solved, and the lock frequency of the phase lock loop is improved. Phase locking accuracy.
Patent Information
- Application Number
- CN202411245164.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2024-12-31
AI Technical Summary
In PPADPLL, when FCW is a decimal, spur appears in the phase noise curve, causing the phase of the CNC oscillator output clock signal to be unable to align with the reference clock signal, and the frequency cannot be aligned, which in turn leads to inaccurate phase locking and phase locking.
By obtaining the first signal and the second signal corresponding to the output clock signal of the CNC oscillator, randomly select one of them, and determine the ideal delay time according to the value of the fractional part of the frequency control word corresponding to the current period of the phase-locked loop, and adjust the output The phase of the clock signal is to make the phase calculation error random and reduce spur in the phase noise curve.
It effectively reduces the spur height in the phase noise curve of PPADPLL, and aligns the phase and frequency of the output clock signal of the CNC oscillator with the reference clock signal, thereby improving the accuracy of phase locking loop frequency locking and phase locking.
Smart Images
Figure CN119232143A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to technical fields such as electronic engineering, and in particular to a method and device for determining a phase difference value. Background Art
[0002] With the rapid development of modern communication technology and electronic systems, Phase Preditc All-Digital Phase-Locked Loop (PPADPLL) is an important frequency synthesis and signal synchronization tool, widely used in wireless communication, clock generation, data recovery and other fields.
[0003] PPADPLL includes a phase detector and a digitally controlled oscillator (DCO). The DCO aligns the phase and frequency of the output clock signal of the DCO and the reference clock signal of the phase detector according to the phase difference between the clock signal of the DCO and the reference clock signal after the delay time. PPADPLL delays the reference clock signal according to the frequency control word (FCW) and the delay time.
[0004] When FCW is a decimal, spurious signals (spur) will appear in the phase noise curve of the PPADPLL, which will make it impossible to align the phase and frequency of the output clock signal of the numerically controlled oscillator with the reference clock signal, resulting in inaccurate frequency and phase locking of the PPADPLL. Summary of the invention
[0005] The present application provides a method and device for determining a phase difference value, which is used to solve the problem that when FCW is a decimal, spur will appear in the phase noise curve of the PPADPLL, which will make the phase and frequency of the output clock signal of the digital controlled oscillator and the reference clock signal unable to be aligned, thereby causing the phase locking and phase locking of the phase-locked loop to be inaccurate.
[0006] In a first aspect, an embodiment of the present application provides a method for determining a phase difference value, which is applied to a phase-locked loop, wherein the phase-locked loop includes a digitally controlled oscillator, including:
[0007] Acquire a first signal and a second signal corresponding to an output clock signal of the digitally controlled oscillator, wherein the first signal and the second signal have different phases;
[0008] randomly selecting the first signal or the second signal;
[0009] Determine an ideal delay duration according to the value of the decimal part of the frequency control word corresponding to the current cycle of the phase-locked loop and the first signal or the second signal randomly selected;
[0010] Determining a target phase of the output clock signal according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration;
[0011] A phase difference between the target phase and the actual phase of the output clock signal is determined, and the phase difference is used to adjust the phase of the output clock signal.
[0012] In one implementation, determining the ideal delay duration according to the value of the decimal part and the randomly selected first signal or second signal includes:
[0013] In the case where the first signal is randomly selected, determining the ideal delay duration according to a first preset value and a value of the decimal part;
[0014] In the case where the second signal is randomly selected, the ideal delay duration is determined according to the value of the decimal part, the first preset value and the second preset value.
[0015] In one implementation, determining the delay duration according to the first preset value and the value of the decimal part includes:
[0016] The difference between the first preset value and the numerical value of the decimal part is determined as the ideal delay duration.
[0017] In one implementation, determining the ideal delay duration according to the value of the decimal part, the first preset value, and the second preset value includes:
[0018] When the value of the decimal part is less than or equal to the second preset value, determining the ideal delay duration according to the second preset value and the value of the decimal part;
[0019] When the value of the decimal part is greater than the second preset value, the ideal delay duration is determined according to the first preset value, the second preset value and the value of the decimal part.
[0020] In one implementation, determining the ideal delay duration according to the second preset value and the frequency control word includes:
[0021] The difference between the second preset value and the numerical value of the decimal part is determined as the ideal delay duration.
[0022] In one implementation, determining the ideal delay duration according to the first preset value, the second preset value, and the value of the decimal part includes:
[0023] Determine a difference between the first preset value and the numerical value of the decimal part;
[0024] The sum of the difference and the second preset value is determined as the ideal delay duration.
[0025] In one implementation, determining the target phase of the output clock signal according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration includes:
[0026] The phase of the reference clock signal after the phase of the reference clock signal at the ideal delay time is determined as the target phase of the output clock signal.
[0027] In a second aspect, an embodiment of the present application provides a phase difference acquisition device, which is applied to a phase-locked loop, wherein the phase-locked loop includes a digitally controlled oscillator, including:
[0028] A first acquisition module, used to acquire a first signal and a second signal corresponding to an output clock signal of the digitally controlled oscillator, wherein the first signal and the second signal have different phases;
[0029] A random selection module, used for randomly selecting the first signal or the second signal;
[0030] A first determination module, configured to determine an ideal delay duration according to a value of a decimal part of a frequency control word corresponding to a current cycle of the phase-locked loop and the first signal or the second signal randomly selected;
[0031] A second determination module, configured to determine a target phase of the output clock signal according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration;
[0032] The third determination module is used to determine a phase difference between the target phase and the actual phase of the output clock signal, and the phase difference is used to adjust the phase of the output clock signal.
[0033] In one implementation, the first determining module is specifically configured to:
[0034] In the case where the first signal is randomly selected, determining the ideal delay duration according to a first preset value and a value of the decimal part;
[0035] In the case where the second signal is randomly selected, the ideal delay duration is determined according to the value of the decimal part, the first preset value and the second preset value.
[0036] In one implementation, the first determining module is specifically configured to:
[0037] The difference between the first preset value and the numerical value of the decimal part is determined as the ideal delay duration.
[0038] In one implementation, the first determining module is specifically configured to:
[0039] When the value of the decimal part is less than or equal to the second preset value, determining the ideal delay duration according to the second preset value and the value of the decimal part;
[0040] When the value of the decimal part is greater than the second preset value, the ideal delay duration is determined according to the first preset value, the second preset value and the value of the decimal part.
[0041] In one implementation, the first determining module is specifically configured to:
[0042] The difference between the second preset value and the numerical value of the decimal part is determined as the ideal delay duration.
[0043] In one implementation, the first determining module is specifically configured to:
[0044] Determine a difference between the first preset value and the numerical value of the decimal part;
[0045] The sum of the difference and the second preset value is determined as the ideal delay duration.
[0046] In one implementation, the second determining module is specifically configured to:
[0047] The phase of the reference clock signal after the phase of the reference clock signal at the ideal delay time is determined as the target phase of the output clock signal.
[0048] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement any of the methods described in the first aspect.
[0049] In a fourth aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements any method described in the first aspect when executed by a computer.
[0050] In a fifth aspect, an embodiment of the present application provides a chip having a computer program stored thereon, and when the computer program is executed by the chip, any one of the methods provided in the first aspect is implemented.
[0051] In a sixth aspect, an embodiment of the present application provides a chip module, on which a computer program is stored. When the computer program is executed by the chip module, any method provided in the first aspect is implemented.
[0052] The embodiment of the present application provides a method and device for determining a phase difference value, in which the first signal and the second signal corresponding to the output clock signal of the numerically controlled oscillator are obtained, and the first signal or the second signal is randomly selected; the ideal delay duration is determined according to the value of the decimal part of the frequency control word corresponding to the current cycle of the phase-locked loop, and the first signal or the second signal randomly selected, so that the ideal delay duration has randomness. Further, the target phase of the output clock signal is determined according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration; the phase difference between the target phase and the actual phase of the output clock signal is determined, and the phase difference is used to adjust the phase of the output clock signal, so that the phase calculation error △PHE also has randomness, rather than a periodic change pattern, so that the spur in the phase noise curve of the phase-locked loop can be reduced, so that the output clock signal of the numerically controlled oscillator is aligned in phase and frequency with the reference clock signal, thereby improving the accuracy of the frequency locking and phase locking of the phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS
[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0054] Figure 1 The working principle diagram of PPADPLL under ideal conditions provided for this application;
[0055] Figure 2 The working principle diagram of PPADPLL under non-ideal conditions provided for this application;
[0056] Figure 3 Schematic diagram of the delay duration and phase error of the PPADPLL provided in this application under ideal and non-ideal conditions;
[0057] Figure 4 This is one of the schematic diagrams of the method for determining the phase difference value provided in this application;
[0058] Figure 5 The second schematic diagram of the method for determining the phase difference value provided in this application;
[0059] Figure 6 A schematic diagram of a phase error of a phase-locked loop provided in an embodiment of the present application;
[0060] Figure 7 The phase noise curve of the phase-locked loop provided by this application;
[0061] Figure 8 This is a schematic diagram of the structure of the phase difference determination device provided in this application.
[0062] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0063] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0064] In this application, the term "include" and its variations may refer to non-restrictive inclusion; the term "or" and its variations may refer to "and / or". "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.
[0065] In the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In the present application, the term "at least one" refers to one or more, and "plurality" refers to two or more. In the present application, the term "at least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, c can be single or multiple.
[0066] In this application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the words "exemplary" or "for example" is intended to present the related concepts in a concrete way.
[0067] First, the relevant technical terms involved in this application are explained.
[0068] Spurs are pulse bumps on the phase noise curve.
[0069] Alignment means the same. For example, phase alignment means the phases are the same. For example, frequency alignment means the frequencies are the same.
[0070] The All-Digital Phase-Locked Loop (ADPLL) adjusts the frequency and phase of the output clock signal of the digitally controlled oscillator through FCW, so that the phase and frequency of the output clock signal of the digitally controlled oscillator and the reference clock signal of the ADPLL are aligned, so that the ADPLL can achieve the purpose of frequency locking and phase locking.
[0071] The principle of ADPLL frequency locking and phase locking is:
[0072] Obtain the first target phase PHR1 of the output clock signal of the digitally controlled oscillator in the Nth cycle, wherein the first target phase PHR1 of the output clock signal is the phase of the reference clock signal in the Nth cycle, and the first target phase PHR1 can be expressed as FCW n Indicates the frequency control word of the nth cycle;
[0073] Obtain the real phase PHV of the output clock signal of the digital controlled oscillator in the Nth cycle;
[0074] Among them, the FCW of each cycle n The value of is the same, that is, FCW n The value of is fixed. For example, FCW n is 2.1, when N=1, The first target phase PHR1 of the first cycle is 2.1; when N=2, The first target phase PHR1 of the second cycle is 4.2; when N=3, The first target phase PHR1 of the third cycle is 6.3; when N=4, The first target phase PHR1 of the fourth cycle is 8.4.
[0075] In ADPLL, accurate measurement of the fractional phase of PHR1 requires high power consumption.
[0076] In view of the above problems, a PPADPLL is proposed. The principle of PPADPLL frequency locking and phase locking is:
[0077] Obtaining a second target phase PHR2 of the output clock signal of the digitally controlled oscillator in the Nth cycle, where the target phase PHR2 is the phase of the reference clock signal in the Nth cycle (eg, PHR1) after an ideal delay time length;
[0078] Obtaining a real phase PHV of the output clock signal of the digital controlled oscillator in the Nth cycle, where the real phase PHV is the phase of the reference clock signal in the Nth cycle (for example, PHR1) after a real delay time;
[0079] determining a second phase difference PHE2 between a second target phase PHR2 and a real phase PHV;
[0080] According to the second phase difference PHE2, the phase of the output clock signal of the digitally controlled oscillator and the frequency of the output clock signal of the digitally controlled oscillator are adjusted to align the phase and frequency of the output clock signal with the reference clock signal.
[0081] In an ideal case, the ideal delay time is the same as the actual delay time, so that the second target phase PHR2 can be aligned with the actual phase PHV. Figure 1 Introduce the working principle of PPADPLL under ideal conditions.
[0082] Figure 1 The working principle diagram of PPADPLL under ideal conditions provided for this application. Figure 1 As shown, FCW n Take 2.1 as an example.
[0083] When N=1, The first target phase PHR1 of the first cycle is 2.1, and the second target phase PHR2 of the first cycle and the actual phase PHV are both 3.
[0084] When N=2, The first target phase PHR1 of the second cycle is 4.2, and the second target phase PHR2 and the actual phase PHV of the second cycle are both 5.
[0085] When N=3, The first target phase PHR1 of the third cycle is 6.3, and the second target phase PHR2 and the actual phase PHV of the third cycle are both 7.
[0086] When N=4, The first target phase PHR1 of the fourth cycle is 8.4, and the second target phase PHR2 and the actual phase PHV of the fourth cycle are both 9.
[0087] Depend on Figure 1 It can be seen that, in an ideal case, the delay time can make the second target phase PHR2 aligned with the real phase PHV.
[0088] In a non-ideal situation, the ideal delay time and the actual delay time are different, making it difficult to align the second target phase PHR2 with the actual phase PHV. Figure 2 Describes the working principle of PPADPLL under non-ideal conditions.
[0089] Figure 2 The working principle diagram of PPADPLL under non-ideal conditions provided for this application. Figure 2 As shown, FCW n Take 2.1 as an example.
[0090] When N=1, In the first cycle, the first target phase PHR1 is 2.1, the second phase PHR2 is 2.8, and the actual phase PHV is 3.
[0091] When N=2, In the second cycle, the first target phase PHR1 is 4.2, the second phase PHR2 is 4.9, and the actual phase PHV is 5.
[0092] When N=3, In the third cycle, the first target phase PHR1 is 6.3, the second phase PHR2 is 6.8, and the actual phase PHV is 7.
[0093] When N=4, In the fourth cycle, the first target phase PHR1 is 8.4, the second phase PHR2 is 8.9, and the actual phase PHV is 9.
[0094] Depend on Figure 2 It can be seen that, under non-ideal conditions, the delay time makes it difficult for the second phase PHR2 to be aligned with the real phase PHV.
[0095] For example, in an ideal case, the delay time length is expressed as an ideal delay time length d1, and the second phase difference PHE2 can be expressed as: PHE2 = PHR1 + d1 - PHV.
[0096] For example, in a non-ideal case, the delay time length is represented by the actual delay time length d2, and the second phase difference PHE2 can be expressed as: PHE2 = PHR1 + d2 - PHV.
[0097] The difference between the second phase difference PHE2 in a non-ideal situation and the second phase difference PHE2 in an ideal situation (which may be referred to as a phase calculation error ΔPHE) may be expressed as: ΔPHE=d2−d1.
[0098] In FCW n When is a decimal, △PHE shows a periodic change pattern. Figure 3 This is explained.
[0099] Figure 3The delay time and phase error diagram of the PPADPLL provided in this application under ideal and non-ideal conditions. Figure 3 As shown, including: the changing relationship between the ideal delay time d1 and the actual delay time d2, and the changing law of △PHE.
[0100] In FCW n When it is a decimal, according to the changing relationship between the ideal delay time d1 and the actual delay time d2, it can be known that the ideal delay time d1 and the actual delay time d2 are different.
[0101] In FCW n When ΔPHE is a decimal, it can be seen from the variation law of ΔPHE that ΔPHE presents a periodic variation law. Since ΔPHE presents a periodic variation law, the spur energy in the phase noise curve of PPADPLL is relatively high.
[0102] In FCW n When it is a decimal, spurs will appear in the phase noise curve of the PPADPLL, which will make it impossible to align the phase and frequency of the output clock signal of the numerically controlled oscillator with the reference clock signal, resulting in inaccurate frequency and phase locking of the PPADPLL.
[0103] In view of this, the present application provides a method for determining a phase difference value, which is used to reduce the spur height in the phase noise curve of the PPADPLL, so that the output clock signal of the digitally controlled oscillator is phase-aligned and frequency-aligned with the reference clock signal, thereby improving the accuracy of PPADPLL frequency locking and phase locking.
[0104] Next, combine Figure 4 The method for determining the phase difference value provided in the present application is exemplarily described.
[0105] Figure 4 This is one of the schematic diagrams of the method for determining the phase difference value provided in this application. Figure 4 As shown, the method includes:
[0106] S401 , obtaining a first signal and a second signal corresponding to an output clock signal of a digitally controlled oscillator, wherein the first signal and the second signal have different phases.
[0107] Optionally, the execution subject of the embodiment of the present application is a phase-locked loop, or a phase difference acquisition device in the phase-locked loop. The phase-locked loop includes a digitally controlled oscillator. The phase difference acquisition device can be implemented by a combination of software and / or hardware.
[0108] Optionally, the first signal may be an output clock signal, or the first signal may be a clock signal after the output clock signal has been delayed by a preset time. The present application does not limit the specific value of the preset delay.
[0109] Optionally, the second signal is a clock signal having a preset phase difference with the first signal. Exemplarily, the preset phase difference may be 180 degrees or the like.
[0110] Exemplarily, the phase of the first signal is 0 degrees, the preset phase difference is 180 degrees, and the second signal is a clock signal having a phase difference of 180 degrees with the first signal, that is, the second signal is a clock signal with a phase of 180 degrees.
[0111] S402: Randomly select the first signal or the second signal.
[0112] Optionally, the first signal or the second signal may be randomly selected according to a switching signal in a phase-locked loop.
[0113] S403: Determine an ideal delay time according to the value of the decimal part of the frequency control word corresponding to the current cycle of the phase-locked loop and the randomly selected first signal or second signal.
[0114] The frequency control word corresponding to the current cycle is the sum of the frequency control word of the current cycle and the frequency control words of all cycles before the current cycle.
[0115] Exemplarily, the current cycle is the Nth cycle, and the frequency control word corresponding to the current cycle is FCW per cycle n The values can be the same, that is, FCW1 = FCW2 = ... = FCW n .
[0116] Optionally, the frequency control word corresponding to the current cycle (ie ) may or may not include a decimal part.
[0117] When the decimal part is not included, for example,
[0118] When including a decimal part, illustratively,
[0119] For example, The value of the decimal part is 0.5; The value of the decimal part is 0.2.
[0120] The ideal delay time is the ideal delay time, that is, the expected ideal delay time.
[0121] S404: Determine a target phase of an output clock signal according to a phase of a reference clock signal of a phase-locked loop and an ideal delay duration.
[0122] The phase of the reference clock signal is the phase of the rising edge of the reference clock signal.
[0123] Exemplarily, when the delay time is 0.8, the time between the target phase of the output clock signal and the phase of the rising edge of the reference clock signal is 0.8.
[0124] S405: Determine a phase difference between the target phase and the actual phase of the output clock signal, where the phase difference is used to adjust the phase of the output clock signal.
[0125] The actual phase of the output clock signal is the actual phase of the output clock signal in the current cycle.
[0126] In an embodiment of the present application, the first signal or the second signal is randomly selected; the ideal delay duration is determined according to the value of the decimal part of the frequency control word corresponding to the current cycle of the phase-locked loop, and the randomly selected first signal or the second signal, so that the ideal delay duration is random. Further, the target phase of the output clock signal is determined according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration; the phase difference between the target phase and the actual phase of the output clock signal is determined, and the phase difference is used to adjust the phase of the output clock signal, so that the phase calculation error △PHE is also random, rather than showing a periodic change pattern, so that the spur height in the phase noise curve of the phase-locked loop can be reduced, so that the output clock signal of the numerically controlled oscillator is aligned in phase and frequency with the reference clock signal, thereby improving the accuracy of the frequency locking and phase locking of the phase-locked loop.
[0127] Figure 5 The second schematic diagram of the method for determining the phase difference value provided in this application. For example, Figure 5 As shown, the method includes:
[0128] S501 , obtaining a first signal and a second signal corresponding to an output clock signal of a digitally controlled oscillator, wherein the first signal and the second signal have different phases.
[0129] S502: Randomly select the first signal or the second signal.
[0130] Specifically, the execution method of S501 and S502 is the same as the execution method of S401 and S402, and the execution process of S501 and S502 is not repeated here.
[0131] S503: When the first signal is randomly selected, determine an ideal delay time according to the first preset value and the value of the decimal part of the frequency control word corresponding to the current cycle of the phase-locked loop.
[0132] In a possible implementation manner, the difference between the first preset value and the numerical value of the decimal part is determined as the ideal delay duration.
[0133] Exemplarily, the first preset value is 1.
[0134] Exemplarily, the frequency control word corresponding to the current cycle is The value of the decimal part is 0.2. When the first preset value is 1, the ideal delay time is 0.8.
[0135] S504: When the second signal is randomly selected, determine an ideal delay time according to the value of the decimal part, the first preset value, and the second preset value.
[0136] Exemplarily, the second preset value is 0.5.
[0137] In a possible implementation manner, determining the ideal delay duration according to the value of the decimal part, the first preset value, and the second preset value includes:
[0138] When the value of the decimal part is less than the second preset value, determining the ideal delay time according to the second preset value and the value of the decimal part;
[0139] When the value of the decimal part is greater than or equal to the second preset value, the ideal delay duration is determined according to the first preset value, the second preset value and the value of the decimal part.
[0140] In a possible implementation manner, determining the ideal delay duration according to the second preset value and the frequency control word includes: determining the difference between the second preset value and the numerical value of the decimal part as the ideal delay duration.
[0141] Exemplarily, the second preset value is 0.5, The value of the decimal part of is 0.2. Since the value of the decimal part 0.2 is less than the first preset value 0.5, the difference between 0.5 and 0.2, 0.3, is determined as the delay duration.
[0142] In a possible implementation manner, the ideal delay duration is determined based on the first preset value, the second preset value and the numerical value of the decimal part, including: determining the difference between the first preset value and the numerical value of the decimal part; and determining the sum of the difference and the second preset value as the ideal delay duration.
[0143] Exemplarily, the second preset value is 0.5, the first preset value is 1, The value of the decimal part is 0.6, so the value of the decimal part 0.6 is greater than the first preset value 0.5. Therefore, the difference between the first preset value 1 and the value of the decimal part 0.6 is determined to be 0.4, and the sum of the difference 0.4 and the first preset value 0.5 is 0.9, which is determined to be the ideal delay duration.
[0144] S505 : Determine the phase of the reference clock signal after the phase at the ideal delay time as the target phase of the output clock signal.
[0145] S506: Determine a phase difference between the target phase and the actual phase of the output clock signal, where the phase difference is used to adjust the phase of the output clock signal.
[0146] Specifically, the execution method of S505 and S506 is the same as the execution method of S404 and S405, and the execution process of S505 and S506 is not repeated here.
[0147] In an embodiment of the present application, when the first signal is randomly selected, the ideal delay time is determined according to the first preset value and the value of the decimal part in the frequency control word corresponding to the current cycle of the phase-locked loop. When the second signal is randomly selected, the ideal delay time is determined according to the value of the decimal part, the first preset value and the second preset value, so that the ideal delay time is random, thereby ensuring that the phase calculation error △PHE is random rather than showing a periodic change pattern. Therefore, the spur height in the phase noise curve of the phase-locked loop can be reduced, so that the output clock signal of the numerically controlled oscillator is aligned in phase and frequency with the reference clock signal, thereby improving the accuracy of frequency locking and phase locking of the phase-locked loop.
[0148] Exemplarily, according to the method for determining the ideal delay duration in the embodiment of the present application, the ideal delay duration shown in the following Table 1 can be obtained. It should be noted that Table 1 is illustrated by taking the first signal as the output clock signal and the second signal as the clock signal having a phase difference of 180 degrees with the first signal as an example.
[0149] Table 1
[0150]
[0151] Figure 6 Schematic diagram of phase error of a phase-locked loop provided in an embodiment of the present application. Figure 6 As shown, including: the changing relationship between the ideal delay time d1 and the actual delay time d2, and the changing law of △PHE.
[0152] It can be seen from the changing relationship between the ideal delay time length d1 and the actual delay time length d2 that, for example, when the ideal delay time length d1 is equal to 0.9, the actual delay time length d2 is less than 0.9.
[0153] Therefore, according to the value of the ideal delay time in the representation, and the changing relationship between the ideal delay time d1 and the actual delay time d2, we can get Figure 6 The changing pattern of △PHE is shown.
[0154] For example, when the ideal delay time d1 is equal to 0.9 and the actual delay time d2 is less than 0.9, the difference △PHE between the ideal delay time d1 and the actual delay time d2 is less than 0. Therefore, in the variation law of △PHE, the △PHE corresponding to the ideal delay time d1 equal to 0.9 is less than 0.
[0155] For example, when the ideal delay time d1 is equal to 0.3 and the actual delay time d2 is greater than 0.3, the difference △PHE between the ideal delay time d1 and the actual delay time d2 is greater than 0. Therefore, in the variation law of △PHE, the △PHE corresponding to the ideal delay time d1 equal to 0.3 is greater than 0.
[0156] from Figure 6 It can be seen from the variation law of △PHE shown that △PHE does not show a periodic variation law. Since △PHE does not show a periodic variation law, the spur in the phase noise curve of the phase-locked loop can be reduced, so that the output clock signal of the numerically controlled oscillator is aligned in phase with the reference clock signal of the phase detector, and the frequency is aligned, which improves the accuracy of the frequency and phase locking of the phase-locked loop.
[0157] Next, combine Figure 7 The spur of a phase-locked loop in the prior art and the spur of a phase-locked loop provided by the present application are introduced.
[0158] Figure 7 This is the phase noise curve of the phase-locked loop provided in this application. Figure 7 As shown, including: when the output clock frequency is 6.240052 Gigahertz (GHz), the phase noise curve of the prior art phase-locked loop and the phase noise curve of the phase-locked loop provided by the present application.
[0159] From the phase noise curve of the prior art phase-locked loop, it can be seen that:
[0160] When the offset frequency is 5.058e+04 (ie, 5.058×104) Hertz (Hz), the phase noise is -28.69 decibels relative to carrier per Hertz (dBc / Hz), and the height of the spur is -28.69 dBc / Hz.
[0161] When the offset frequency is 1.041e+05 (ie, 1.041×105) Hz, the phase noise is -48.47 dBc / Hz and the spur height is -48.47 dBc / Hz.
[0162] When the offset frequency is 1.547e+05 (ie, 1.547×105) Hz, the phase noise is -50.92 dBc / Hz and the spur height is -50.92 dBc / Hz.
[0163] It can be seen from the phase noise curve of the prior art phase-locked loop that the maximum value of the spur height is -28.69 dBc / Hz.
[0164] From the phase noise curve of the phase-locked loop provided in this application, it can be seen that:
[0165] When the offset frequency is 1.041e+05 (ie, 1.041×105) Hz, the phase noise is -41.11 dBc / Hz and the spur height is -41.11 dBc / Hz.
[0166] When the offset frequency is 2.053e+05 (ie, 2.053×105) Hz, the phase noise is -46.34 dBc / Hz and the spur height is -46.34 dBc / Hz.
[0167] When the offset frequency is 3.095e+05 (ie, 3.095×105) Hz, the phase noise is -50.7 dBc / Hz and the spur height is -50.7 dBc / Hz.
[0168] It can be seen from the phase noise curve of the phase-locked loop provided in the present application that the maximum value of the spur height is -41.11 dBc / Hz. Compared with the phase-locked loop in the prior art, the maximum value of the spur height is smaller.
[0169] Therefore, the phase-locked loop provided in the present application can reduce the height of the spur in the phase noise curve of the phase-locked loop, thereby reducing the spur in the phase noise curve of the phase-locked loop, so that the output clock signal of the numerically controlled oscillator is phase-aligned and frequency-aligned with the reference clock signal of the phase detector, thereby improving the accuracy of frequency locking and phase locking of the phase-locked loop.
[0170] Figure 8 This is a schematic diagram of the structure of the phase difference determination device provided in the present application, which is applied to a phase-locked loop, which includes a digitally controlled oscillator. Figure 8 As shown, the phase difference determination device 80 may include:
[0171] A first acquisition module 801 is used to acquire a frequency control word corresponding to a current cycle of a phase-locked loop, where the frequency control word includes a decimal part;
[0172] A first determination module 802 is used to determine the delay time of the reference clock signal of the phase-locked loop according to the value of the decimal part;
[0173] A second determination module 803 is used to determine a target phase of an output clock signal of a digitally controlled oscillator according to the frequency control word and the delay time;
[0174] A second acquisition module 804 is used to acquire a random signal corresponding to the output clock signal;
[0175] The third determination module 805 is used to determine the real phase of the output clock signal according to the target phase and the random signal; determine the phase difference between the target phase and the real phase, and the phase difference is used to adjust the phase of the output clock signal.
[0176] The phase difference determination device 80 provided in this embodiment is used to execute the method provided in the above-mentioned embodiment. Its implementation principle and technical effect are similar and will not be described in detail.
[0177] In one implementation, the first determining module 802 is specifically configured to:
[0178] In the case of randomly selecting the first signal, determining an ideal delay time according to the first preset value and the value of the decimal part;
[0179] When the second signal is randomly selected, the ideal delay time is determined according to the value of the decimal part, the first preset value and the second preset value.
[0180] In one implementation, the first determining module 802 is specifically configured to:
[0181] The difference between the first preset value and the numerical value of the decimal part is determined as the ideal delay duration.
[0182] In one implementation, the first determining module 802 is specifically configured to:
[0183] When the value of the decimal part is less than or equal to the second preset value, determining the ideal delay duration according to the second preset value and the value of the decimal part;
[0184] When the value of the decimal part is greater than the second preset value, the ideal delay duration is determined according to the first preset value, the second preset value and the value of the decimal part.
[0185] In one implementation, the first determining module 802 is specifically configured to:
[0186] The difference between the second preset value and the numerical value of the decimal part is determined as the ideal delay duration.
[0187] In one implementation, the first determining module 802 is specifically configured to:
[0188] Determine the difference between the first preset value and the numerical value of the decimal part;
[0189] The sum of the difference and the second preset value is determined as the ideal delay duration.
[0190] In one implementation, the second determining module 803 is specifically configured to:
[0191] The phase of the reference clock signal after the phase of the reference clock signal at the ideal delay time is determined as the target phase of the output clock signal.
[0192] The phase difference determination device 80 provided in this embodiment is used to execute the method provided in the above-mentioned embodiment. Its implementation principle and technical effect are similar and will not be described in detail.
[0193] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method in the above embodiment.
[0194] An embodiment of the present application provides a computer program product, including a computer program, which implements the method in the above embodiment when executed by a computer.
[0195] An embodiment of the present application provides a chip having a computer program stored thereon. When the computer program is executed by the chip, the method in the above embodiment is implemented.
[0196] An embodiment of the present application provides a chip module, on which a computer program is stored. When the computer program is executed by the chip module, the method in the above embodiment is implemented.
[0197] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0198] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0199] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for determining a phase difference value, applied to a phase-locked loop, wherein the phase-locked loop includes a digitally controlled oscillator, characterized in that: include: Acquire a first signal and a second signal corresponding to an output clock signal of the digitally controlled oscillator, wherein the first signal and the second signal have different phases; randomly selecting the first signal or the second signal; Determine an ideal delay duration according to the value of the decimal part of the frequency control word corresponding to the current cycle of the phase-locked loop and the first signal or the second signal randomly selected; Determining a target phase of the output clock signal according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration; A phase difference between the target phase and the actual phase of the output clock signal is determined, and the phase difference is used to adjust the phase of the output clock signal.
2. The method according to claim 1, characterized in that Determining the ideal delay duration according to the value of the decimal part and the randomly selected first signal or second signal includes: In the case where the first signal is randomly selected, determining the ideal delay duration according to a first preset value and a value of the decimal part; In the case where the second signal is randomly selected, the ideal delay duration is determined according to the value of the decimal part, the first preset value and the second preset value.
3. The method according to claim 2, characterized in that The step of determining the delay duration according to the first preset value and the value of the decimal part includes: The difference between the first preset value and the numerical value of the decimal part is determined as the ideal delay duration.
4. The method according to claim 2, characterized in that: The step of determining the ideal delay duration according to the value of the decimal part, the first preset value, and the second preset value includes: When the value of the decimal part is less than the second preset value, determining the ideal delay duration according to the second preset value and the value of the decimal part; When the value of the decimal part is greater than or equal to the second preset value, the ideal delay duration is determined according to the first preset value, the second preset value and the value of the decimal part.
5. The method according to claim 4, characterized in that The step of determining the ideal delay duration according to the second preset value and the frequency control word includes: The difference between the second preset value and the numerical value of the decimal part is determined as the ideal delay duration.
6. The method according to claim 4, characterized in that The step of determining the ideal delay duration according to the first preset value, the second preset value, and the value of the decimal part includes: Determine a difference between the first preset value and the numerical value of the decimal part; The sum of the difference and the second preset value is determined as the ideal delay duration.
7. The method according to any one of claims 1 to 6, characterized in that: The step of determining the target phase of the output clock signal according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration comprises: The phase of the reference clock signal after the phase of the reference clock signal at the ideal delay time is determined as the target phase of the output clock signal.
8. A phase difference acquisition device, applied to a phase-locked loop, wherein the phase-locked loop includes a digitally controlled oscillator, characterized in that: include: A first acquisition module, used to acquire a first signal and a second signal corresponding to an output clock signal of the digitally controlled oscillator, wherein the first signal and the second signal have different phases; A random selection module, used for randomly selecting the first signal or the second signal; A first determination module, configured to determine an ideal delay duration according to a value of a decimal part of a frequency control word corresponding to a current cycle of the phase-locked loop and the first signal or the second signal randomly selected; A second determination module, configured to determine a target phase of the output clock signal according to the phase of the reference clock signal of the phase-locked loop and the ideal delay duration; The third determination module is used to determine a phase difference between the target phase and the actual phase of the output clock signal, and the phase difference is used to adjust the phase of the output clock signal.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.
10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 7 when being executed by a computer.