A method, device, equipment and medium for calibrating synchronous timing of multiple acquisition modules

Abstract

The present application discloses a method, device, equipment and medium for calibrating the synchronous timing of multiple acquisition modules, including: determining multiple synchronous window sets of each acquisition module based on the window information for synchronous sampling provided by each analog-to-digital conversion chip; determining the optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to the multiple synchronous window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronous window position. The present application achieves synchronous timing calibration of multiple acquisition modules by calibrating the acquisition timing between two analog-to-digital conversion chips in each module and keeping the phase relationship between multiple modules consistent under different ambient temperatures.

Description

Technical Field

[0001] The present application relates to the technical field of high-speed signal acquisition modules, and in particular to a method, device, equipment and medium for calibrating synchronous timing of multiple acquisition modules. Background Art

[0002] In the process of multi-channel signal acquisition, it is very important to maintain the stability of the signal acquisition system, which requires good synchronization between chips and modules and between modules. However, factors such as hardware differences in the signal acquisition system and environmental changes during acquisition (such as temperature, humidity and pressure) may lead to the emergence of metastable phenomena, resulting in synchronization failure of the signal acquisition system, that is, the setup time (ts) and hold time (th) between the synchronization signal and the clock are unstable, which may lead to signal acquisition across clock cycles.

[0003] If a signal acquisition system using two interleaved analog-to-digital conversion chips is used, a sawtooth waveform may be generated, which may cause a phase difference of multiples of the clock cycle between different modules in a multi-module synchronous signal acquisition system.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of this application is to provide a method, device, equipment and medium for calibrating the synchronous timing of multiple acquisition modules, aiming to solve the technical problem of failure of timing synchronization of the acquisition system caused by factory differences in hardware in the signal acquisition system and changes in environmental factors during the acquisition process.

[0006] To achieve the above-mentioned purpose, the present application provides a method for calibrating synchronous timing of multiple acquisition modules, which is applied to a measuring device, wherein the measuring device includes multiple acquisition modules, each acquisition module includes multiple analog-to-digital conversion chips, and the method is executed by a synchronous timing calibration device that is communicatively connected to each acquisition device, and the method is executed by a processor, including: determining multiple synchronization window sets of each acquisition module based on window information for synchronous sampling provided by each analog-to-digital conversion chip; determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to the multiple synchronization window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronization window position.

[0007] Optionally, determining multiple synchronization window sets for each acquisition module includes: calculating multiple optional positions contained in window information provided by each analog-to-digital conversion chip for synchronous sampling; and determining multiple synchronization window sets for each acquisition module based on multiple optional positions of each analog-to-digital conversion chip in each acquisition module.

[0008] Optionally, the calculation of multiple optional positions contained in the window information for synchronous sampling provided by each analog-to-digital conversion chip includes: determining at least one optional interval of each analog-to-digital conversion chip based on the window information for synchronous sampling provided by each analog-to-digital conversion chip; and determining multiple optional positions of each analog-to-digital conversion chip based on each optional interval.

[0009] Optionally, determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on multiple synchronization window sets of each acquisition module includes: determining a position combination sequence of each acquisition module based on multiple synchronization window sets of each acquisition module; completing the position combination sequence of each acquisition module based on the difference in the number of data of the position combination sequences of different acquisition modules; and determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the completed position combination sequence of each acquisition module.

[0010] Optionally, determining the position combination sequence of each acquisition module based on multiple synchronization window sets of each acquisition module includes: for any acquisition module, determining the phase difference between multiple analog-to-digital conversion chips under each synchronization window set, and determining multiple position combination values ​​of the acquisition module based on the synchronization window set corresponding to the phase difference less than a preset threshold; and forming the position combination sequence of each acquisition module from the multiple position combination values ​​of each acquisition module.

[0011] Optionally, the method of completing the position combination sequence of each acquisition module based on the difference in the number of data of the position combination sequences of different acquisition modules includes: determining the acquisition module corresponding to the position combination sequence with the largest number of data as the benchmark acquisition module; and completing the position combination sequence of each acquisition module according to the difference in the number of data between the position combination sequences of each acquisition module and the benchmark acquisition module.

[0012] Optionally, the method of determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the completed position combination sequence of each acquisition module includes: calculating the standard deviation of multiple identical position data in the completed position combination sequence of all acquisition modules; and determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the size difference of each standard deviation.

[0013] In addition, to achieve the above-mentioned purpose, the present application also provides a multi-acquisition module synchronization timing calibration device, including: a synchronization window set determination module, used to determine multiple synchronization window sets of each acquisition module, and the synchronization window set is used to characterize the optional position of each analog-to-digital conversion chip in the acquisition module; an optimal sampling position determination module, used to determine the optimal sampling position of each acquisition module according to the multiple synchronization window sets of each acquisition module; a synchronization timing calibration module, used to complete the synchronization timing calibration of multiple acquisition modules based on the optimal sampling position of each acquisition module.

[0014] The present application also provides a multi-acquisition module synchronization timing calibration device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned multi-acquisition module synchronization timing calibration method.

[0015] The present application also provides a computer-readable storage medium, comprising: a computer program stored therein, wherein when the computer program is executed by a processor, the above-mentioned method for calibrating synchronous timing of multiple acquisition modules is implemented.

[0016] The present application proposes a method, device, equipment and medium for calibrating the synchronous timing of multiple acquisition modules. By determining multiple synchronization window sets of each acquisition module and determining the optimal sampling position of each acquisition module according to the multiple synchronization window sets of each acquisition module, the method solves the problem of deviation in the timing synchronization of multiple acquisition modules caused by factory differences in hardware itself and changes in environmental factors during the multi-channel signal acquisition process. The method achieves synchronization of the acquisition timing between the two analog-to-digital conversion chips in each module and consistency of the phase relationship between multiple modules through calibration at different ambient temperatures, thereby achieving synchronous timing calibration of multiple acquisition modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of a method for calibrating synchronous timing of multiple acquisition modules according to an implementation mode of the present application;

[0018] Figure 2 It is a schematic diagram of the metastable phenomenon;

[0019] Figure 3 This is a schematic diagram of the structure of a collection system according to an implementation mode of the present application;

[0020] Figure 4 This is a schematic diagram of sampling positions of two analog-to-digital conversion chips in one embodiment of the present application;

[0021] Figure 5 This is a diagram showing the effect of interleaved sampling when the phase difference between two analog-to-digital conversion chips is 200ps in one embodiment of the present application;

[0022] Figure 6 This is a schematic diagram of the optimal synchronization window position of each analog-to-digital conversion chip in an embodiment of the present application;

[0023] Figure 7 This is a schematic diagram of the optimal synchronization window position of each analog-to-digital conversion chip in another embodiment of the present application;

[0024] Figure 8It is a structural block diagram of a multi-acquisition module synchronization timing calibration device according to an implementation mode of the present application;

[0025] Fig. 9 It is a structural schematic diagram of a multi-acquisition module synchronous timing calibration device according to an implementation mode of the present application.

[0026] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0027] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] In the process of multi-channel signal acquisition, it is very important to maintain the stability of the signal acquisition system, which requires good synchronization between chips and modules and between modules. However, factors such as hardware differences in the signal acquisition system and environmental changes during acquisition (such as temperature, humidity and pressure) may lead to the occurrence of metastable phenomena, such as Figure 2 As shown, Figure 2 The figure is a schematic diagram of the metastable phenomenon when the synchronization signal deviates. In the figure, ts represents the setup time between the synchronization signal and the sampling clock, and th represents the hold time between the synchronization signal and the sampling clock. When the metastable phenomenon occurs, it will cause the synchronization of the signal acquisition system to fail, that is, the setup time and hold time between the synchronization signal and the clock will be unstable, which may cause signal acquisition across clock cycles.

[0029] In order to solve the above problems, the present application provides a method for calibrating synchronous timing of multiple acquisition modules. The present application scheme is introduced in detail below.

[0030] Figure 1 The flowchart of the synchronous timing calibration method of multiple acquisition modules according to an embodiment of the present application is provided. The synchronous timing calibration method of multiple acquisition modules can be applied to measuring equipment, and can be specifically applied to the fields of electronic test and measurement instruments, radar, communication, electronic countermeasures, etc., wherein the measuring equipment may include multiple acquisition modules, each acquisition module includes multiple analog-to-digital conversion chips, and the measuring equipment may also include a synchronous timing calibration device having data processing capabilities and being communicatively connected to each acquisition device. The synchronous timing calibration method of multiple acquisition modules can be executed by the synchronous timing calibration device, and the synchronous timing calibration device can be, for example, a synchronous timing calibration device for multiple acquisition modules. Figure 1 The method for calibrating the synchronous timing of multiple acquisition modules may include the following steps:

[0031] Step S1, determining a plurality of synchronous window sets of each acquisition module based on window information for synchronous sampling provided by each analog-to-digital conversion chip.

[0032] See also Figure 3 , Figure 3 This is a system structure diagram of a signal acquisition system of an exemplary embodiment. The signal acquisition system may include a measuring device, wherein the number of acquisition modules is 4, namely a first acquisition module B1, a second acquisition module B2, a third acquisition module B3 and a fourth acquisition module B4, and each acquisition module includes two analog-to-digital conversion chips Adc1 and Adc2, and the two analog-to-digital conversion chips perform interleaved acquisition.

[0033] It should be noted that the acquisition module can be used to acquire and process various types of signals, and can convert physical quantities in the environment (such as temperature, pressure, light intensity, etc.) into digital signals that can be used for subsequent processing. The analog-to-digital conversion chip (ADC chip) in the acquisition module is a key component in the acquisition module. By sampling and quantizing the input analog signal, it is converted into a corresponding digital value, thereby realizing the discrete representation of the continuous signal. Using two analog-to-digital conversion chips (ADC chips) for interleaved acquisition in one acquisition module can significantly improve the sampling rate and data accuracy of the signal acquisition system. By alternately using two ADC chips, more sampling operations can be completed in a shorter time, thereby achieving higher time resolution, which is especially advantageous in high-frequency signal acquisition or multi-channel signal processing. However, when using two analog-to-digital conversion chips (ADC chips) for interleaved acquisition, the signal acquisition system needs to accurately synchronize the two ADC chips to avoid timing errors or signal deviations that ultimately affect the quality of the final data. Therefore, it is necessary to perform synchronization timing calibration on the acquisition module to ensure the accuracy and reliability of the data.

[0034] In one embodiment, in step S1, determining multiple synchronous window sets of each acquisition module based on window information for synchronous sampling provided by each analog-to-digital conversion chip may specifically include:

[0035] S11, calculating multiple optional positions included in the window information for synchronous sampling provided by each analog-to-digital conversion chip;

[0036] S12. Determine multiple synchronization window sets of each acquisition module based on multiple optional positions of each analog-to-digital conversion chip in each acquisition module.

[0037] In step S11, the synchronous timing calibration device may first determine at least one optional interval of each analog-to-digital conversion chip based on window information for synchronous sampling provided by each analog-to-digital conversion chip, and then determine multiple optional positions of each analog-to-digital conversion chip based on each optional interval.

[0038] In the specific implementation process, the continuous threshold is set to P, the window information for synchronous sampling of each analog-to-digital conversion chip is collected, and the information is traversed from the low bit to the high bit and the number of consecutive 0s is recorded. If the combination of the first bit and the last bit is "10", the recording starts. If the combination of the first bit and the last bit is "00", the number of consecutive 0s continues to be counted. If the combination of the first bit and the last bit is "01", the recording ends. When the number of consecutive 0s is greater than or equal to the continuous threshold P, the interval where 0s appear continuously is recorded as an optional interval.

[0039] Further, multiple optional positions of each analog-to-digital conversion chip are determined based on each optional interval, wherein the optional position is the position average of each optional interval. For example, the optional position can be calculated using the following formula (1): :

[0040]

[0041] in, Indicates the end position of each optional interval. Indicates the starting position of each optional position.

[0042] In an exemplary embodiment, the window information for synchronous sampling of the first analog-to-digital conversion chip B1.Adc1 and the second analog-to-digital conversion chip B1.Adc2 in the first acquisition module, the first analog-to-digital conversion chip B2.Adc1 and the second analog-to-digital conversion chip B2.Adc2 in the second acquisition module, the first analog-to-digital conversion chip B3.Adc1 and the second analog-to-digital conversion chip B3.Adc2 in the third acquisition module, and the first analog-to-digital conversion chip B4.Adc1 and the second analog-to-digital conversion chip B4.Adc2 in the fourth acquisition module can be expressed as follows: B1.Adc1=>1001_1000_0001_1000_0000_1101

[0043] B1.Adc2=>1110_0000_0011_0000_0001_1001

[0044] B2.Adc1=>1001_1000_0001_1000_0001_1001

[0045] B2.Adc2=>1100_0000_0110_0000_0011_0001

[0046] B3.Adc1=>1000_1100_0000_0110_0000_0111

[0047] B3.Adc2=>1000_1100_0000_1100_0000_0111

[0048] B4.Adc1=>1000_1100_0000_0110_0000_0011

[0049] B4.Adc2=>1000_0110_0000_0110_0000_0011

[0050] Among them, each analog-to-digital conversion chip has a total of 24 bits from low to high, 1 represents a foul, and each optional position can select bit 0 to bit 15. It should be noted that the middle position of the continuous 0 interval is a more ideal sampling position. The higher the sampling clock frequency, the shorter the number of consecutive 0 bits. This exemplary embodiment takes a 5GHz clock as an example.

[0051] Specifically, taking the first analog-to-digital conversion chip B1.Adc1 in the first acquisition module as an example, the continuous threshold P is 3, and two optional intervals can be obtained by traversing from the low position to the high position. Then, based on the two optional intervals, the two optional positions are calculated using formula (1) to be the 7th and 15th positions.

[0052] Taking the second analog-to-digital conversion chip B1.Adc2 in the first acquisition module as an example, the optional position of B1.Adc2 is the 8th bit.

[0053] See also Figure 4 , Figure 4 Schematic diagram of optional positions of the first analog-to-digital conversion chip B1.Adc1 in the first acquisition module and the second analog-to-digital conversion chip B1.Adc2 in the first acquisition module in this exemplary embodiment.

[0054] Furthermore, determining multiple synchronization window sets of each acquisition module based on multiple optional positions of each analog-to-digital conversion chip in each acquisition module in step S12 may specifically include: combining multiple optional positions of different analog-to-digital conversion chips in each acquisition module to obtain multiple synchronization window sets.

[0055] Specifically, taking the optional positions of the first analog-to-digital conversion chip B1.Adc1 in the first acquisition module as the 7th and 15th bits, and the optional position of the second analog-to-digital conversion chip B1.Adc2 in the first acquisition module as the 8th bit as an example, the synchronization window set of the first acquisition module B1 is {7,8} and {15,8}.

[0056] Step S2, determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to multiple synchronization window sets of each acquisition module, wherein the processor of each analog-to-digital conversion chip performs data sampling according to the optimal synchronization window position.

[0057] It should be noted that the analog-to-digital conversion chip usually provides window information for synchronous sampling, and can calculate the appropriate sampling position through window information analysis and set it to the register to maintain stable sampling. However, for this embodiment, the two analog-to-digital conversion chips in the acquisition module perform interleaved acquisition, and thus this embodiment also needs to ensure the phase requirements for the interleaving of the two analog-to-digital conversion chips. Taking a 5GHz clock as an example, that is, one clock cycle is 200ps, please refer to Figure 5 , Figure 5 This is the effect diagram of interleaved sampling when the phase difference between the two analog-to-digital conversion chips is 200ps, that is, the effect diagram of sampling across clock cycles of the two analog-to-digital conversion chips. Figure 5 TI-ADC represents the TI model analog-to-digital converter, so Figure 5 It can be seen that when the phase difference between the two analog-to-digital conversion chips is too large, it will cause distortion of the signal waveform, thereby causing instability in the entire signal sampling system. Therefore, after calculating and obtaining several synchronization window sets, this embodiment needs to further select the synchronization window sets based on the phase difference requirements of the two analog-to-digital conversion chips, so as to ensure that the obtained synchronization window sets can ensure stable sampling of the signal acquisition system.

[0058] In one embodiment, in step S2, determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to multiple synchronization window sets of each acquisition module may specifically include:

[0059] S21, determining a position combination sequence of each acquisition module according to a plurality of synchronization window sets of each acquisition module;

[0060] S22, completing the position combination sequence of each acquisition module based on the difference in the number of data in the position combination sequences of different acquisition modules;

[0061] S23, determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the completed position combination sequence of each acquisition module.

[0062] Among them, in step S21, for any acquisition module, the synchronous timing calibration device can first determine the phase difference between multiple analog-to-digital conversion chips under each synchronization window set, determine multiple position combination values ​​of the acquisition module based on the synchronization window set corresponding to the phase difference less than the preset threshold, and then use the multiple position combination values ​​of the acquisition module to form a position combination sequence of the acquisition module.

[0063] In a specific implementation process, any currently available phase difference calculation algorithm can be used to determine the phase difference between multiple analog-to-digital conversion chips under each synchronization window set, such as a sinusoidal three-parameter error algorithm and FFT.

[0064] In an exemplary embodiment, for any acquisition module, the signals collected by the two analog-to-digital conversion chips under each synchronization window set can first be subjected to a fast Fourier transform, i.e., FFT, and then the phase value of the specified frequency point can be calculated, and the two phase values ​​can be subtracted to obtain the phase difference between the two analog-to-digital conversion chips under each synchronization window set.

[0065] Specifically, the signal source outputs a 1GHz sinusoidal signal to the signal acquisition system, and the amplitude of the signal is adjusted to within ±3div of the full scale of the analog-to-digital conversion chip. The two analog-to-digital conversion chips first collect the signal based on the optional position corresponding to any synchronization window set, and perform FFT calculation on the collected signals respectively. In this embodiment, the sampling frequency of the analog-to-digital conversion chip is set to is 10Gsa / s, and based on the sampling frequency Calculate the frequency point index of 1 GHz, and then index the imaginary part I and the real part R corresponding to the frequency 1GHz from the FFT calculation result of the signal through the frequency point index of 1 GHz, and then calculate the phase angle of the waveform of the first analog-to-digital conversion chip and the phase angle of the waveform of the second analog-to-digital conversion chip based on the imaginary part I and the real part R through the inverse tangent function, so that the difference between the two phase angles is the phase difference between the first analog-to-digital conversion chip and the second analog-to-digital conversion chip under the synchronization window set.

[0066] Furthermore, a set of synchronization windows corresponding to all phase differences less than a preset threshold is obtained, and the mean of two data in each synchronization window set is calculated to obtain each position combination value. For example, the position combination value can be calculated using the following formula (2): , where the preset threshold can be a clock cycle of 200ps:

[0067]

[0068] in, Indicates the optional position of the first bit of data in each synchronization window set, i.e., the first analog-to-digital conversion chip, Indicates the last bit of data in each synchronization window set, namely, the optional position of the second analog-to-digital conversion chip.

[0069] Specifically, taking the synchronization window set of the first acquisition module B1 as {7, 8} and {15, 8} as an example, the synchronization window set that meets the conditions of the first acquisition module B1 is {7, 8}, and the average of 7 and 8 is obtained to obtain the position combination value of 7.5 of the first acquisition module B1.

[0070] Furthermore, a plurality of position combination values ​​of each acquisition module constitute a position combination sequence of each acquisition module.

[0071] Specifically, taking the position combination values ​​5.5 and 14 of the second acquisition module B2 as an example, the position combination sequence of the second acquisition module B2 is {5.5, 14}.

[0072] In one embodiment, in step S22, completing the position combination sequence of each acquisition module based on the difference in the number of data in the position combination sequences of different acquisition modules may specifically include:

[0073] S221, determining the acquisition module corresponding to the position combination sequence with the largest number of data as the reference acquisition module;

[0074] S222. Completing the position combination sequences of each acquisition module according to the difference in the number of data between the position combination sequences of each acquisition module and the reference acquisition module.

[0075] It should be noted that since the number of data in the position combination sequences obtained for each acquisition module is different, it is necessary to first use the position combination sequence containing the largest number of data as a benchmark to fill in the number of data in other position combination sequences so that the number of data in the position combination sequences of each acquisition module is the same.

[0076] In the specific implementation process, the acquisition module corresponding to the position combination sequence with the largest number of data is determined as the reference acquisition module, and the data in the position combination sequences of other acquisition modules are supplemented until the number of data is equal to the number of data in the position combination sequence of the reference acquisition module. It should be noted that if the number of position combination sequences with the largest number of data is greater than 1, the acquisition module corresponding to any position combination sequence with the largest number of data is selected as the reference acquisition module.

[0077] Furthermore, the absolute value of the difference between the first data in the position combination sequence of each other acquisition module and the first data in the position combination sequence of the reference acquisition module is calculated, and the absolute value of the difference between the last data in the position combination sequence of each other acquisition module and the last data in the position combination sequence of the reference acquisition module is calculated. The two absolute values ​​of the difference are compared. If the absolute value of the difference between the first data is large, M data with the same value as the first data are added before the first data in the position combination sequence of each other acquisition module. If the absolute value of the difference between the last data is large, M data with the same value as the last data are added after the last data in the position combination sequence of each other acquisition module. Wherein M is the absolute value of the difference in the number of data in the position combination sequence of each other acquisition module and the position combination sequence of the reference acquisition module.

[0078] In an exemplary embodiment, the position combination sequence of the first acquisition module B1 is {5.5, 14}, the position combination sequence of the second acquisition module B2 is {5.5, 14}, the position combination sequence of the third acquisition module B3 is {3.5, 13}, and the position combination sequence of the fourth acquisition module B4 is {3, 12, 15}. Since the position combination sequence of the fourth acquisition module B4 has the largest number of data, the fourth acquisition module B4 is the reference acquisition module. For the first acquisition module B1, the calculated absolute values ​​of the difference between the first bit of data and the absolute values ​​of the difference between the last bit of data are 2.5 and 1, respectively. Since 2.5 is greater than 1, the first bit of data is added forward to fill in the gaps. The position combination sequence of the first acquisition module B1 after filling in is {5.5, 5.5, 14}. Similarly, the position combination sequence of the second acquisition module B2 after filling in is {5.5, 5.5, 14}, and the position combination sequence of the third acquisition module B3 after filling in is {3.5, 13, 13}.

[0079] In one embodiment, in step S23, completing the position combination sequence of each acquisition module based on the difference in the number of data in the position combination sequences of different acquisition modules may specifically include:

[0080] S231, calculating the standard deviation of multiple identical position data in the position combination sequence after all acquisition modules are completed;

[0081] S232. Determine the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the size difference of each standard deviation.

[0082] In the specific implementation process, the standard deviation of the same position data in the position combination sequence after the acquisition modules are filled is calculated respectively, wherein the number of the calculated standard deviations is the number of data in the position combination sequence after the filling. It should be noted that the standard deviation can be used to characterize the degree of dispersion of data.

[0083] In an exemplary embodiment, the position combination sequences after all acquisition modules are padded can first be formed into a matrix, the number of columns of the matrix is ​​the number of data in each padded position combination sequence, and the number of rows of the matrix is ​​the number of acquisition modules. Then, the standard deviation of each column of data in the matrix is ​​calculated respectively, that is, the standard deviation of multiple identical position data in the position combination sequences after all acquisition modules are padded.

[0084] In an exemplary embodiment, the position combination sequence after the first acquisition module B1 is padded is {7.5,7.5}, the position combination sequence after the second acquisition module B2 is padded is {8,8}, the position combination sequence after the third acquisition module B3 is padded is {5.5,14}, and the position combination sequence after the fourth acquisition module B4 is padded is {5,13.5}. The matrix of the four acquisition modules is:

[0085]

[0086] Among them, the standard deviations of the two columns of data in the matrix are calculated respectively and obtained as: 1.27 and 3.01.

[0087] Furthermore, the position combination value of the acquisition module corresponding to the smallest standard deviation is selected to obtain the synchronization window set of each acquisition module corresponding to each position combination value, and the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module is determined based on the synchronization window set of each acquisition module.

[0088] Continuing with the above embodiment as an example, please refer to Figure 6 , Figure 6 It is a schematic diagram of the optimal synchronization window position of each analog-to-digital conversion chip in the above embodiment. Since 1.27 is smaller than 3.01, the position combination value of each acquisition module corresponding to the column where 1.27 is located is first selected. For example, the first acquisition module B1 selects 7.5, and then based on the position combination value 7.5, it is determined that the optimal synchronization window position of the first analog-to-digital conversion chip and the optimal synchronization window position of the second analog-to-digital conversion chip in the first acquisition module B1 are the 7th and 8th bits respectively. Figure 7 FIG. 1 is a schematic diagram of another embodiment of the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module. Figure 7 In the window information shown, the standard deviations obtained based on the above method are 0.83 and 1.14. Taking 0.83, the optimal synchronization window position of the analog-to-digital conversion chip in each acquisition module shown in the figure is obtained.

[0089] It should be noted that the optimal synchronization window position of the analog-to-digital conversion chip in each acquisition module obtained in this embodiment can meet the phase requirement of interleaving two analog-to-digital conversion chips in the same acquisition module, and at the same time can ensure that the phase difference of multiple acquisition modules remains consistent under different environments, such as at different temperatures. Therefore, it is possible to select the optimal synchronization window position through calibration at different ambient temperatures, synchronize the acquisition timing between the two analog-to-digital conversion chips in each module, and keep the phase relationship between multiple modules consistent, thereby achieving synchronization timing calibration of multiple acquisition modules.

[0090] Based on the above embodiments, Figure 8 FIG. 1 is a structural block diagram of a synchronous timing calibration device for multiple acquisition modules according to an embodiment of the present application. Figure 8 As shown, the multi-acquisition module synchronization timing calibration device may include: a synchronization window set determination module 210, an optimal synchronization window position determination module 220, wherein:

[0091] The synchronization window set determination module 210 is used to determine multiple synchronization window sets of each acquisition module based on the window information for synchronous sampling provided by each analog-to-digital conversion chip;

[0092] The optimal synchronization window position determination module 220 is used to determine the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to multiple synchronization window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronization window position.

[0093] In an exemplary embodiment, the synchronization window set determination module 210 can also be used to calculate multiple optional positions contained in the window information for synchronous sampling provided by each analog-to-digital conversion chip; and determine multiple synchronization window sets for each acquisition module based on the multiple optional positions of each analog-to-digital conversion chip in each acquisition module.

[0094] In an exemplary embodiment, the synchronization window set determination module 210 can also be used to determine at least one optional interval of each analog-to-digital conversion chip based on window information provided by each analog-to-digital conversion chip for synchronous sampling; and determine multiple optional positions of each analog-to-digital conversion chip based on each optional interval.

[0095] In an exemplary embodiment, the optimal synchronization window position determination module 220 can also be used to determine the position combination sequence of each acquisition module based on multiple synchronization window sets of each acquisition module; to complete the position combination sequence of each acquisition module based on the difference in the number of data in the position combination sequences of different acquisition modules; and to determine the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the completed position combination sequence of each acquisition module.

[0096] In an exemplary embodiment, the optimal synchronization window position determination module 220 can also be used to determine, for any acquisition module, the phase difference between multiple analog-to-digital conversion chips under each synchronization window set, and determine multiple position combination values ​​of the acquisition module based on the synchronization window set corresponding to the phase difference less than a preset threshold; the multiple position combination values ​​of each acquisition module constitute a position combination sequence of each acquisition module.

[0097] In an exemplary embodiment, the optimal synchronization window position determination module 220 can also be used to determine the acquisition module corresponding to the position combination sequence with the largest number of data as the reference acquisition module; and fill in the position combination sequence of each acquisition module based on the difference in the number of data between the position combination sequences of each acquisition module and the reference acquisition module.

[0098] In an exemplary embodiment, the optimal synchronization window position determination module 220 can also be used to calculate the standard deviation of multiple identical position data in the position combination sequence after all acquisition modules are completed; and determine the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the size difference of each standard deviation.

[0099] Those skilled in the art should understand that the division of the various modules in the embodiment is only a division of logical functions, and can be fully or partially integrated into one or more actual carriers in actual application, and these modules can be all implemented in the form of software called by the processing unit, or all implemented in the form of hardware, or implemented in the form of a combination of software and hardware. It should be noted that each module in a multi-acquisition module synchronization timing calibration device in this embodiment corresponds one-to-one to each step in a multi-acquisition module synchronization timing calibration method in the aforementioned embodiment. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned multi-acquisition module synchronization timing calibration method, which will not be repeated here.

[0100] Based on the above embodiments, Fig. 9 FIG. 1 is a structural diagram of a multi-acquisition module synchronization timing calibration device according to an embodiment of the present application. Fig. 9 As shown, the electronic device may include: a processor 310, a communication interface 320, a memory 330 and a communication bus 340, wherein the processor 310, the communication interface 320 and the memory 330 communicate with each other through the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute a method for calibrating the synchronous timing of multiple acquisition modules, the method comprising: determining a plurality of synchronous window sets of each acquisition module based on the window information for synchronous sampling provided by each analog-to-digital conversion chip; determining the optimal synchronous window position of each analog-to-digital conversion chip in each acquisition module according to the plurality of synchronous window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronous window position.

[0101] In addition, the logic instructions in the above-mentioned memory 330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0102] On the basis of the above embodiments, on the other hand, the present invention further provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the multi-acquisition module synchronization timing calibration method provided by the above methods, the method including: determining multiple synchronization window sets of each acquisition module based on window information for synchronous sampling provided by each analog-to-digital conversion chip; determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to the multiple synchronization window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronization window position.

[0103] On the basis of the above embodiments, on another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the multi-acquisition module synchronization timing calibration method provided by the above methods, the method comprising: determining a plurality of synchronization window sets of each acquisition module based on window information for synchronous sampling provided by each analog-to-digital conversion chip; determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to the plurality of synchronization window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronization window position.

[0104] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for calibrating synchronous timing of multiple acquisition modules, characterized in that: Applied to a measuring device, the measuring device includes a plurality of acquisition modules, each acquisition module includes a plurality of analog-to-digital conversion chips, the method is performed by a synchronous timing calibration device connected to each acquisition module in communication, and the method includes: Determine multiple synchronization window sets of each acquisition module based on window information for synchronous sampling provided by each analog-to-digital conversion chip; Determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to multiple synchronization window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronization window position; The step of determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to the multiple synchronization window sets of each acquisition module includes: Determine the position combination sequence of each acquisition module according to multiple synchronization window sets of each acquisition module; Completing the position combination sequence of each acquisition module based on the difference in the number of data of the position combination sequences of different acquisition modules; The optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module is determined based on the completed position combination sequence of each acquisition module.

2. The method for calibrating synchronous timing of multiple acquisition modules according to claim 1, characterized in that: The step of determining a plurality of synchronization window sets of each acquisition module includes: Calculating a plurality of optional positions included in the window information for synchronous sampling provided by each analog-to-digital conversion chip; A plurality of synchronization window sets of each acquisition module are determined based on a plurality of optional positions of each analog-to-digital conversion chip in each acquisition module.

3. The method for calibrating synchronous timing of multiple acquisition modules as claimed in claim 2, characterized in that: The step of calculating a plurality of optional positions included in the window information for synchronous sampling provided by each analog-to-digital conversion chip comprises: Determining at least one optional interval of each analog-to-digital conversion chip based on window information for synchronous sampling provided by each analog-to-digital conversion chip; A plurality of optional positions of each analog-to-digital conversion chip are determined based on each optional interval.

4. The method for calibrating synchronous timing of multiple acquisition modules according to claim 1, characterized in that: The step of determining the position combination sequence of each acquisition module according to the multiple synchronization window sets of each acquisition module includes: For any acquisition module, determine the phase difference between multiple analog-to-digital conversion chips under each synchronization window set, and determine multiple position combination values ​​of the acquisition module based on the synchronization window set corresponding to the phase difference less than a preset threshold; The multiple position combination values ​​of each acquisition module constitute a position combination sequence of each acquisition module.

5. The method for calibrating synchronous timing of multiple acquisition modules according to claim 1, characterized in that: The method of completing the position combination sequence of each acquisition module based on the difference in the number of data of the position combination sequences of different acquisition modules includes: The acquisition module corresponding to the position combination sequence with the largest number of data is determined as the reference acquisition module; According to the difference in the number of data between the position combination sequences of each acquisition module and the reference acquisition module, the position combination sequences of each acquisition module are completed.

6. The method for calibrating synchronous timing of multiple acquisition modules according to claim 1, characterized in that: The method of determining the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module based on the position combination sequence after the acquisition modules are completed includes: Calculate the standard deviation of multiple identical position data in the position combination sequence after all acquisition modules are completed; The optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module is determined based on the size difference of each standard deviation.

7. A synchronous timing calibration device for multiple acquisition modules, characterized in that: include: A synchronization window set determination module, used to determine multiple synchronization window sets of each acquisition module based on the window information for synchronous sampling provided by each analog-to-digital conversion chip; An optimal synchronization window position determination module, used to determine the optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module according to multiple synchronization window sets of each acquisition module, wherein the processor of each acquisition module performs data sampling according to the optimal synchronization window position; The optimal synchronization window position determination module is also used to determine the position combination sequence of each acquisition module according to multiple synchronization window sets of each acquisition module; Completing the position combination sequence of each acquisition module based on the difference in the number of data of the position combination sequences of different acquisition modules; The optimal synchronization window position of each analog-to-digital conversion chip in each acquisition module is determined based on the completed position combination sequence of each acquisition module.

8. A multi-acquisition module synchronous timing calibration device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the multi-acquisition module synchronization timing calibration method as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for calibrating synchronous timing of multiple acquisition modules according to any one of claims 1 to 6 is implemented.

Images