Sigma Delta modulator introducing element mismatch information
By introducing incremental ADC structure and pointer generation network into the Sigma Delta modulator, the component mismatch information of the feedback DAC is calculated and stored, which solves the accuracy loss problem caused by component mismatch in traditional modulators, and achieves a higher level of output accuracy and signal-to-noise ratio.
Patent Information
- Application Number
- CN202411188428.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-28
- Publication Date
- 2024-12-31
AI Technical Summary
The traditional multi-bit quantization Sigma Delta modulator does not consider component mismatch of feedback DACs in the digital output, resulting in system accuracy loss, affecting signal-to-noise ratio and stability.
By introducing an incremental ADC structure, component mismatch information of the feedback DAC is calculated and stored, and it is introduced into the digital output of the Sigma Delta modulator, and the pointer generation network and memory are used for calibration, so as to calculate and calibrate component mismatch.
It effectively improves the output accuracy of the Sigma Delta modulator, improves the signal-to-noise ratio and signal-to-noise harmonic distortion ratio, and reduces the accuracy loss caused by component mismatch.
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Figure CN119232168A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronics and solid-state electronics, and is applied to a Sigma Delta analog-to-digital converter. A novel multi-bit quantized Sigma Delta modulator model is designed. The digital output of the modulator model introduces component mismatch information of a feedback DAC, which can effectively improve the system accuracy. Background Art
[0002] Analog-to-digital converter (ADC) is a circuit system that converts continuously changing analog signals into digital signals. Analog-to-digital converters can be divided into two categories: Nyquist rate analog-to-digital converters and oversampling analog-to-digital converters. The minimum sampling frequency of the Nyquist rate analog-to-digital converter is the frequency required by the Nyquist criterion, that is, twice the input signal bandwidth, but the accuracy that the Nyquist analog-to-digital converter can achieve under the same process is limited. Oversampling analog-to-digital converters can achieve high accuracy at a relatively high conversion speed. Sigma Delta ADC is the most widely used oversampling ADC. Sigma Delta ADC consists of Sigma Delta modulator and digital filter. The Sigma Delta modulator first uses oversampling technology to sample the analog input signal with a sampling frequency much higher than the Nyquist frequency, reducing the quantization noise energy within the signal bandwidth. Then, the quantization noise energy within the signal bandwidth is modulated to a high frequency range outside the signal bandwidth through noise shaping technology, further reducing the quantization noise within the signal bandwidth. Finally, the modulator output digital code is downsampled and out-of-band noise is filtered out through the post-stage digital extraction filter to complete the conversion process.
[0003] The accuracy of Sigma Delta ADC is generally determined by the Sigma Delta modulator. During the design process, it is usually necessary to compromise between the topology, order, oversampling rate, number of quantization bits and noise shaping function (NTF) of the Sigma Delta modulator while ensuring the system accuracy requirements, stability, signal input range and power consumption. This process usually uses the Simulink tool in Matlab to model and simulate the Sigma Delta modulator and determine the above system parameters to provide a reference for subsequent circuit design.
[0004] In order to achieve high precision, the structure of the Sigma Delta modulator usually chooses multi-bit quantization to improve the signal-to-noise ratio and avoid using too high an oversampling rate and order. At the same time, it can improve system stability compared to single-bit quantization. Multi-bit quantization has the problem of nonlinearity of the feedback DAC, which will cause large harmonics in the circuit and reduce system accuracy. Dynamic element matching (DEM) is usually used to reduce the impact of DAC nonlinearity on system accuracy. Digital weighted average (DWA) is a relatively mature DEM algorithm. Its core idea is to control the circular shift through the pointer so that each element is selected the same number of times, thereby averaging the nonlinear impact caused by mismatch. In addition, the DWA algorithm also has the ability to shape the first-order noise for the element mismatch of the feedback DAC.
[0005] The DWA algorithm can greatly improve the accuracy of multi-bit quantized Sigma Delta modulators. Figure 1 The digital output of the traditional multi-bit quantized Sigma Delta modulator shown does not take into account the component mismatch generated at each feedback, which will cause a certain loss of accuracy of the Sigma Delta modulator. Therefore, a Sigma Delta modulator structure that introduces feedback component mismatch information in the digital output is of great significance to improving the performance of the Sigma Delta modulator. Summary of the invention
[0006] The present invention proposes a new structure for introducing feedback element mismatch information into the digital output of a Sigma Delta modulator under multi-bit quantization. The structure rearranges the traditional Sigma Delta modulator structure, realizes the introduction of feedback element mismatch information into the digital output of the Sigma Delta modulator, reduces the accuracy loss of the digital output of the existing multi-bit quantized Sigma Delta modulator due to not considering the feedback element mismatch, and can effectively improve the output accuracy of the Sigma Delta modulator.
[0007] The technical solution of the present invention is: a Sigma Delta modulator that introduces component mismatch information. The modulator first connects one end of switch SW2-1, one end of switch SW1-1, one end of switch SW2-2, and the positive input end of a first adder together, the other end of switch SW2-1 is connected to a current source Vac, the other end of switch SW1-1 is connected to a voltage source Vdc, and the other end of switch SW2-2 is input to a three-input adder; the output end of the first adder is divided into three paths after passing through an integral coefficient module a1 and a first-stage discrete time integrator in sequence, the first path is input to the three-input adder after passing through a switch SW2-3 and a feedforward coefficient module f1 in sequence, the second path is input to the positive input end of the second adder after passing through an integral coefficient module a2 and a second-stage discrete time integrator in sequence, and the third path is input to the positive input end of the second adder after passing through a feedforward coefficient module f2; the output end of the second adder is divided into two paths, one path is input to the three-input adder after passing through a switch SW2-4, an integral coefficient module a3, and a third discrete time integrator in sequence Adder, the other path is sequentially switched SW1-2, a one-bit quantizer, a first digital integrator, a second digital integrator, and a counter and then input to the memory RAM, and at the same time, the output of the one-bit quantizer is also input to the negative input terminal of the first adder through the switch SW1-3; the output of the three-input adder is divided into four paths after passing through the three-bit quantizer, the first path is input to the memory RAM after passing through the pointer generation network; the second path is used as the 1 terminal of the switching end of the switch SWA after passing through the dynamic element matching DAC; the third path is directly used as the 2 terminal of the switching end of the switch SWA, the switch SWA switches between the 1 terminal and the 2 terminal, and the non-switching end of the switch SWA is input to the negative input terminal of the first adder through the switch SW2-5; the fourth path is used as the 2 terminal of the switching end of the switch SWB, the output of the memory RAM is used as the 1 terminal of the switching end of the switch SWB, the switch SWB switches between the 1 terminal and the 2 terminal, and the non-switching end of the switch SWB is used as the output of the modulator;
[0008] The on and off states of switch SW2-1, switch SW2-2, switch SW2-3, switch SW2-4, and switch SW2-5 are the same, and the corresponding switch timing is SW2-*;
[0009] The on and off states of switch SW1-1, switch SW1-2, and switch SW1-3 are the same, and the corresponding switch timing is SW1-*;
[0010] Furthermore, the pointer generation network is input to the positive input terminal of the third adder and then divided into two paths, one path is input to the multiplexer MUX, and the other path passes through the delay unit Z -1 , cycle function Function_Cyclic; the output of the cycle function Function_Cyclic is divided into two paths, one path is input to the positive input terminal of the third adder, and the other path is input to the multiplexer MUX. The output of the multiplexer MUX is the output of the pointer generation network.
[0011] The present invention rearranges the traditional Sigma Delta modulator, adds a two-stage digital integrator, a one-bit quantizer, and a counter, reuses the first two stages of the integrator of the main Sigma Delta modulator to realize an incremental ADC, and introduces a RAM and a pointer generation network. The above structure completes the calculation and storage of feedback DAC component mismatch, and introduces the component mismatch information into the digital output of the Sigma Delta modulator. This process is called calibration through an incremental ADC with pointer and memory (Incremental ADC that with Pointer and Memory to Calibrate, IPMC). This structure reduces the accuracy loss of the output of the existing multi-bit quantized Sigma Delta modulator due to not considering the feedback DAC mismatch, and can effectively improve the output accuracy of the Sigma Delta modulator. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 It is a traditional third-order, multi-bit quantized Sigma Delta modulator structure.
[0013] Figure 2 IPMC is used to add component mismatch to the Sigma Delta modulator of the present invention.
[0014] Figure 3 The addition of component mismatch to the Sigma Delta modulator of the present invention does not employ IPMC.
[0015] Figure 4 The Sigma Delta modulator of the present invention is in an ideal situation.
[0016] Figure 5 for Figure 2 The simulation results are shown in Figure 2.
[0017] Figure 6 for Figure 3 The simulation results are shown in Figure 2.
[0018] Figure 7 for Figure 4 The simulation results are shown in Figure 2. DETAILED DESCRIPTION
[0019] The new structure of the present invention after rearrangement of the conventional Sigma Delta modulator structure mainly includes a three-stage discrete time integrator, a three-bit quantizer, a DWA and a feedback DAC, a two-stage digital integrator, a one-bit quantizer, a counter, a pointer generation algorithm (Pointer Generation) and a memory.
[0020] In the first stage, the incremental ADC is operated to calculate and store the mismatch of the feedback DAC. The present invention re-arranges the conventional SigmaDelta modulator structure, and realizes an incremental ADC for calculating the component mismatch by adding a two-stage digital integrator, a one-bit quantizer, and a counter, and reusing the first two stages of the main three-order, three-bit quantized Sigma Delta modulator structure. The digital output of the incremental ADC reflects the component mismatch of the feedback DAC, that is, the analog quantity of the component mismatch is converted into a digital quantity by the incremental ADC and the digital output D is converted into a digital quantity by the incremental ADC. out Stored in memory.
[0021] In the second stage, the Sigma Delta modulator conversion is run, and the output of the Sigma Delta modulator is calibrated using the component mismatch stored in the memory in the previous stage. After the component mismatch calculation, quantization, and storage are completed, the main third-order, three-bit quantized Sigma Delta modulator conversion is started. In this stage, the output Out_Q of the three-bit quantizer is input into the pointer generation algorithm module to control the generation of a two-bit pointer, which is input into the memory storing the component mismatch information, and the calibrated Sigma Delta digital output is obtained from the memory. The incremental ADC calculates and quantizes the component mismatch, the memory stores the component mismatch, and the three-bit quantizer controls the generation of the pointer and outputs the corresponding value from the memory to complete the calibration of the Sigma Delta modulator output, that is, calibration is performed through the incremental ADC with pointer and memory (IPMC), which introduces the feedback DAC component mismatch information into the digital output of the Sigma Delta modulator.
[0022] The present invention is characterized in that the Sigma Delta modulator digital output introduces feedback DAC element mismatch information, which can improve conversion accuracy and achieve a high signal-to-noise ratio. The specific working principle is as follows:
[0023] The Sigma Delta modulator structure of the present invention is as follows Figure 2 As shown in FIG. 1 , the Sigma Delta modulator re-arranges the main third-order, three-bit quantized Sigma Delta modulator structure, and realizes the incremental ADC by reusing the structure of the main Sigma Delta modulator and adding an additional one-bit quantizer, two digital integrators and a counter. The main purpose of the incremental ADC is to calculate and quantify the mismatch of the feedback DAC element. In addition, in order to achieve the purpose of storing the calculation results, a memory is also required to store the digital value D of the incremental ADC quantization element mismatch. out .
[0024] In terms of timing, the incremental ADC works before the Sigma Delta modulator conversion. The Sigma Delta modulator with a third-order, three-bit quantization structure of the main body works after the incremental ADC completes calculation, quantization, and storage. That is, the mismatch calculation, quantization, and storage functions are performed in the SW1-* phase, and the conversion of the Sigma Delta modulator of the main body is performed in the SW2-* phase. The incremental ADC multiplexes the components of the Sigma Delta modulator. On this basis, a comparator, two digital integrators, and a counter are added to obtain the structure of the incremental ADC. The input is V dc and the output is D out The relationship is as follows:
[0025]
[0026] where M represents the maximum counting value of the counter; m is the lower limit variable of the first summation symbol and the upper limit variable of the second summation symbol, and the range of m is: 1 < m < M - 1; d[k] represents the output of a one-bit quantizer; V ref represents the reference voltage of the one-bit quantizer; the first term on the right side of the equation can be considered as an approximation of V dc , e is the error generated by this approximation; the double summation of d[k] is D out , and two-stage digital integrators are used in the incremental ADC to implement this function. Therefore, for a fixed input V dc , due to component mismatches, each different component will generate a different digital output D out , and the ratio between them remains unchanged. This process is called the incremental ADC to implement component mismatch calculation and quantization, and then the component mismatch quantization result is input into the memory.
[0027] During the SW2-* phase, the third-order, three-bit quantization Sigma Delta modulator of the main body starts to convert. The main body structure re-plans the traditional feedforward branch, introduces one branch to sum before the third-stage integrator, and the obtained noise transfer function is:
[0028]
[0029] where NTF represents the noise transfer function, z represents the complex variable after z-transform, a1, a2, and a3 respectively represent the integration coefficients of each stage of the discrete-time integrator, and f1, f2 represent the feedforward coefficients;
[0030] During the conversion of the main Sigma Delta modulator, the output Out_Q of the three-bit quantizer controls the pointer generation algorithm to generate a pointer. The pointer generation algorithm is implemented by the output of the quantizer and the cyclic function Function_Cyclic. The output of the function Function_Cyclic controls the pointer to point to the starting point, and the value obtained by adding the output of Function_Cyclic to the output of the quantizer controls the pointer to point to the end point. The two-bit pointer is input into the memory storing the component mismatch, and the corresponding calibrated digital quantity is read and used as the output of the main Sigma Delta modulator. Therefore, the above process realizes the introduction of component mismatch into the digital output of the Sigma Delta modulator and completes the calibration of the Sigma Delta modulator output by calculating and quantizing the component mismatch through the incremental ADC, storing the calculated component mismatch in the memory, and controlling the generation of the pointer reading by the three-bit quantizer, that is, calibration (IPMC) is performed through the incremental ADC with pointer and memory.
[0031] There are three combinations of switches SWA and SWB, which are used to compare the schemes of the present invention using IPMC and not using IPMC. The three connection methods of SWA and SWB are as follows:
[0032] The present invention (using IPMC): Figure 2 This is a solution proposed by the present invention to introduce component mismatch information into the digital output of the Sigma Delta modulator. At this time, switches SWA and SWB are both connected to position 1, switches SW1-1, SW1-2, and SW1-3 that control the operation of the incremental ADC are first closed and then opened, and switches SW2-1, SW2-2, SW2-3, SW2-4, and SW2-5 that control the operation of the main Sigma Delta modulator are first opened and then closed. After SW1-1, SW1-2, and SW1-3 are opened, SW2-1, SW2-2, SW2-3, SW2-4, and SW2-5 are closed again.
[0033] Without IPMC: Figure 3 In order to use the traditional quantizer output as the digital output of the SigmaDelta modulator in the case of component mismatch, the switch SWA is connected to position 1 and the switch SWB is connected to position 2. The switches SW1-1, SW1-2, and SW1-3 that control the operation of the incremental ADC are disconnected, and the switches SW2-1, SW2-2, SW2-3, SW2-4, and SW2-5 that control the operation of the main Sigma Delta modulator are closed.
[0034] Ideally: Figure 4The Sigma Delta modulator is in an ideal condition. At this time, switches SWA and SWB are both connected to position 2, switches SW1-1, SW1-2, and SW1-3 that control the operation of the incremental ADC are disconnected, and switches SW2-1, SW2-2, SW2-3, SW2-4, and SW2-5 that control the operation of the main Sigma Delta modulator are closed.
[0035] Table 1 compares the performance of the Sigma Delta modulator model of the present invention with three-order, three-bit quantization under the conditions of oversampling rate 64, sampling frequency 1.28MHz, input 859.37Hz sinusoidal signal, input amplitude -4dBFS, and three different connection methods of switches SWA and SWB. In addition, Table 1 also lists the performance of the Sigma Delta modulator model with three-order, three-bit quantization under the conditions of oversampling rate 64, sampling frequency 1.28MHz, input 859.37Hz sinusoidal signal, and input amplitude -4dBFS. In addition, Table 1 also lists the performance of the Sigma Delta modulator model with three-order, three-bit quantization under the conditions of oversampling rate 64 and sampling frequency 1.28MHz, input 859.37Hz sinusoidal signal, and input amplitude -4dBFS.
[0036] It can be seen that under the same conditions and after considering the component mismatch, the new structure of introducing component mismatch into the digital output of the Sigma Delta modulator provided by the present invention has advantages in signal-to-noise ratio, signal-to-noise harmonic distortion ratio and effective number of bits.
[0037] Table 1: Performance comparison of 64-oversampling, third-order, three-bit quantization Sigma Delta modulator model
[0038]
Claims
1. A Sigma Delta modulator that introduces component mismatch information. The modulator first connects one end of switch SW2-1, one end of switch SW1-1, one end of switch SW2-2, and the positive input end of a first adder together, the other end of switch SW2-1 is connected to a current source Vac, the other end of switch SW1-1 is connected to a voltage source Vdc, and the other end of switch SW2-2 is input to a three-input adder; the output end of the first adder is divided into three paths after passing through an integral coefficient module a1 and a first-stage discrete time integrator in sequence, the first path is input to the three-input adder after passing through a switch SW2-3 and a feedforward coefficient module f1 in sequence, and the second path is input to the three-input adder after passing through an integral coefficient module a2 and a second-stage discrete time integrator in sequence. The positive input end of the second adder, the third path is input into the positive input end of the second adder through the feedforward coefficient module f2; the output end of the second adder is divided into two paths, one path is sequentially input to the three-input adder through the switch SW2-4, the integral coefficient module a3, and the third discrete time integrator, and the other path is sequentially input to the memory RAM through the switch SW1-2, the one-bit quantizer, the first digital integrator, the second digital integrator, and the counter, and the output of the one-bit quantizer is also input into the negative input end of the first adder through the switch SW1-3; the output of the three-input adder is divided into four paths after passing through the three-bit quantizer, and the first path is input to the memory RAM after passing through the pointer generation network; The second path is matched to the DAC through a dynamic element and serves as the terminal 1 of the switch SWA switching end; the third path is directly used as the terminal 2 of the switch SWA switching end, the switch SWA switches between the terminal 1 and the terminal 2, and the non-switching end of the switch SWA is input to the negative input end of the first adder through the switch SW2-5; the fourth path is used as the terminal 2 of the switch SWB switching end, the output of the memory RAM is used as the terminal 1 of the switch SWB switching end, the switch SWB switches between the terminal 1 and the terminal 2, and the non-switching end of the switch SWB serves as the output of the modulator; The on and off states of switch SW2-1, switch SW2-2, switch SW2-3, switch SW2-4, and switch SW2-5 are the same, and the corresponding switch timing is SW2-*; The on and off states of the switches SW1 - 1 , SW1 - 2 , and SW1 - 3 are the same, and the corresponding switch timing is SW1 -*.
2. A Sigma Delta modulator for introducing component mismatch information as claimed in claim 1, characterized in that: The pointer generation network is input to the positive input terminal of the third adder and then divided into two paths, one of which is input to the multiplexer MUX and the other is input to the delay unit Z. -1 , cycle function Function_Cyclic; the output of the cycle function Function_Cyclic is divided into two paths, one path is input to the positive input terminal of the third adder, and the other path is input to the multiplexer MUX. The output of the multiplexer MUX is the output of the pointer generation network.