FPGA-based infrared imaging system and electronic equipment

Abstract

The invention discloses an FPGA-based infrared imaging system and electronic equipment, the system comprises an infrared detector, an infrared detector driving circuit, an FPGA processing system, an interface driving circuit and a CRT display, the infrared detector is used for collecting an infrared signal and converting the collected infrared signal into an electric signal; the infrared detector driving circuit is used for converting the electric signal into an original 64-bit parallel binary digital signal; the FPGA processing system is used for processing the original 64-bit parallel binary digital signal in real time and outputting a processed infrared data stream; the interface driving circuit is used for converting the infrared data stream output by the FPGA into a composite synchronous video broadcast signal; and the CRT display is used for displaying the composite synchronous video broadcast signal. The system has the advantages of being good in real-time performance, remarkable in denoising effect and ideal in enhancement effect, the quality of the infrared image can be effectively improved, and better support is provided for subsequent application.

Description

Technical Field

[0001] The present invention relates to the field of infrared imaging technology, and in particular to an infrared imaging system and electronic equipment based on FPGA. Background Art

[0002] Infrared images are widely used in many fields, such as military, security, medical, industrial detection, etc. However, infrared images are often interfered by various noises during acquisition and transmission, which will reduce the quality and readability of the image and affect subsequent analysis and processing. At the same time, due to the characteristics of infrared images themselves, there are problems such as low contrast and unclear details, so enhancement processing is also required to improve the quality of the image.

[0003] Common traditional infrared image denoising methods include mean filtering, median filtering, etc. Although mean filtering is simple, it can easily lead to blurred image edges; median filtering has a good suppression effect on salt and pepper noise, but has limited effect on other types of noise. In addition, there are some denoising methods based on wavelet transform, etc., but these methods often have high computational complexity and poor real-time performance. For infrared image enhancement, commonly used methods include histogram equalization, etc. However, histogram equalization may lead to over-enhancement, causing some unnatural phenomena in the image. At the same time, some existing enhancement methods may not be ideal for enhancing image details and cannot fully mine useful information in infrared images.

[0004] With the development of FPGA technology, it has the advantages of strong parallel processing capability and good reconfigurability, providing a new way for real-time processing of infrared images. However, applying traditional denoising and enhancement algorithms directly to FPGA often faces problems such as high resource consumption, low efficiency, and poor adaptability. Moreover, different application scenarios have different requirements for the quality of infrared images, requiring a denoising and enhancement algorithm that can be flexibly adjusted according to actual needs.

[0005] In practical applications, such as military reconnaissance, the quality of infrared images is directly related to the recognition and monitoring of targets. If the image noise is too large or the contrast is insufficient, it may lead to misjudgment or missed judgment. In the medical field, infrared images are used for disease diagnosis and monitoring, and high-quality images are essential for accurate diagnosis. In industrial inspection, clear infrared images can help detect tiny defects and anomalies.

[0006] There is no effective solution to the problem that the infrared image denoising process in the prior art is not sophisticated enough. Summary of the invention

[0007] The purpose of this application is to provide an infrared imaging system, an electronic device and a readable storage medium based on FPGA. The system has the advantages of good real-time performance, significant denoising effect and ideal enhancement effect, and can effectively improve the quality of infrared images.

[0008] To achieve the above objectives: In a first aspect, an embodiment of the present application provides an infrared imaging system based on FPGA, the system comprising: an infrared detector, an infrared detector driving circuit, an FPGA processing system, an interface driving circuit and a CRT display, the infrared detector being used to collect infrared signals and convert the collected infrared signals into electrical signals; the infrared detector driving circuit being used to convert the electrical signals into original 64-bit parallel digital signals; the FPGA processing system being used to process the original 64-bit parallel digital signals in real time and output the processed infrared data streams; the interface driving circuit being used to convert the infrared data streams output by the FPGA into composite synchronous video broadcast signals; and the CRT display being used to display the composite synchronous video broadcast signals.

[0009] Preferably, the FPGA processing circuit includes: for the original 64-bit parallel digital signal input into the FPGA processing system, the infrared denoising and enhancement algorithm and the AGC algorithm are used to process the signal to obtain a processed infrared data stream.

[0010] Preferably, the infrared denoising and enhancement algorithm includes a first module and a second module, and the first module includes: The original 64-bit parallel binary digital signal is windowed by 3*3 in the FPGA processing system to obtain a matrix X1. , wherein data11-data33 are the original 64-bit parallel binary digital signals; The matrix X1 is multiplied by the boundary coefficient coefxx to obtain the matrix X2, ; Specifically, the matrix X1 is multiplied by the boundary coefficient coefxx to obtain the matrix X1' , when the matrix X1' is at the image boundary, some pixel values ​​in the matrix , , and If the pixel exceeds the boundary range, its boundary coefficient coefxx is set to 0, so that it does not participate in subsequent calculations. The boundary coefficients of the remaining pixel values ​​are taken between 0 and 1, and then the matrix X2 is obtained, where data32_plus=data32*coefxx,data23_plus=data23*coefxx, data21_plus=data21*coefxx,data12_plus=data12*coefxx; Calculate the average value of the matrix X2, and use the average value as the weak filtering value; The output data of the dynamic data exchange mode (DDE_mode) is used as the output data of the first module, wherein the output data of the dynamic data exchange mode is divided into two types, namely, when DDE_mode=0, the output data of the first module is data22, and when DDE_mode=1, the output data of the first module is the weak filtering value.

[0011] Preferably, the second module includes: Window the data output by the first module to obtain a 5*5 pixel matrix X3 , where DATA00-DATA44 are 64-bit parallel binary digital signal after windowing, with a window size of 5*5; The matrix X3 is multiplied by the boundary coefficient coefxx to obtain the matrix X4, ; Specifically, the matrix X3 is multiplied by the boundary coefficient coefxx to obtain the matrix By setting DATAxx_plus=DATAxx*coefxx, the value of xx is: 00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 25, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, the obtained matrix is ​​transformed into the matrix X4; The matrix X4 is multiplied by the threshold coefficient coefxx_2 to obtain the matrix X5, Specifically, the matrix X4 is multiplied by the threshold coefficient coefxx_2 to obtain the matrix By setting DATAxx_plus_x=DATAxx_plus*coefxx_2, the value of xx is: 00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, the obtained matrix is ​​transformed into matrix X5; The matrix X5 is multiplied by twice the threshold value threshold*2 to obtain a matrix X6, where threshold is a preset value, and the matrix X6 is: ; Specifically, the matrix X5 is multiplied by twice the threshold value threshold*2 to obtain the matrix By setting DATAxx_plus_2x=DATAxx_plus_x* threshold*2, the value of xx is 00, 01, 02, 03, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, and the obtained matrix is ​​transformed into the matrix X6; Obtain matrix X8 based on the matrix X5 Based on the matrix X6, the matrix X7 is obtained Calculate the average value S_BF1 of the matrix X7 and the average value S_BF_x1 of the matrix X8, and calculate the parameter S_D1 according to the average values ​​S_BF1 and S_BF_x1, wherein the parameter S_D1 = (S_BF_x1+8192)-S_BF1, and determine the value range of the parameter S_D2 according to the parameter S_D1; Based on the value of the parameter S_D2, the values ​​of the parameters S_RD_SD, S_RD_mean and S_RB_BF are calculated; Determine the size of the sum of the parameter S_RB_BF and the parameter S_RD_SD and the parameter S_RD_mean, and generate data DATA_OUT1 based on the determination result; Calculate the average value of the matrix X4, and use the average value of the matrix X4 as data DATA_OUT2; Calculate the variance of the matrix X4, and determine whether the data output by the second module is DATA_OUT1 or DATA_OUT2 according to the variance.

[0012] Preferably, obtaining a matrix X8 based on the matrix X5 and obtaining a matrix X7 based on the matrix X6 comprises: Taking the central pixel value data22 of the matrix X5 and the matrix X6 as the standard, a threshold threshold is set, wherein the threshold can be 0, 8, 12, 20; the threshold coefficient of the pixel point in the matrix whose pixel value is greater than data22+threshold or less than data22-threshold is set to 0, and the matrix X8 and the matrix X7 are obtained respectively.

[0013] Preferably, judging the range of S_D2 according to the value of S_D1 includes: If S_D1 ≥ 8192: (S_D1<=8192+32) then S_D2<=S_D1; (S_D1<=8192+64) then S_D2<=S_D1[63:1]+4096+16; (S_D1<=8192+128) then S_D2<=S_D1[63:2]+6144+32; (S_D1<=8192+256) then S_D2<=S_D1[63:3]+7168+48; else then S_D2<=S_D1[63:4]+7680+64; If S_D1<8192: (S_D1>=8192-32) then S_D2<=S_D1; (S_D1>=8192-64) then S_D2<=S_D1[63:1]+4096-16; (S_D1>=8192-128) then S_D2<=S_D1[63:2]+6144-32; (S_D1>=8192-256) then S_D2<=S_D1[63:3]+7168-48; else then S_D2<=S_D1[63:4]+7680-64; Among them, S_D1[63:1] represents the value after taking the characters from the 63rd to the 1st bit from the parameter S_D1, S_D1[63:2] represents the value after taking the characters from the 63rd to the 2nd bit from the parameter S_D1, S_D1[63:3] represents the value after taking the characters from the 63rd to the 3rd bit from the parameter S_D1, and S_D1[63:4] represents the value after taking the characters from the 63rd to the 4th bit from the parameter S_D1.

[0014] Preferably, the calculating the values ​​of parameters S_RD_SD, S_RD_mean and S_RB_BF based on the range of S_D2 includes: S_RD_SD= S_D2 * Proportion_in; S_RD_mean= {Proportion_in,7'd0} S_RB_BF=S_BF_x1, Among them, Proportion_in is an image enhancement level parameter, corresponding to different image enhancement levels (DDE_LV); {Proportion_in,7'd0} means adding 7 zeros after the binary value of the image enhancement level parameter Proportion_in. When DDE_LV is level 0, the image enhancement level parameter Proportion_in takes 0; when DDE_LV is level 1, the image enhancement level parameter Proportion_in takes 80; when DDE_LV is level 2, the image enhancement level parameter Proportion_in takes 120; when DDE_LV is level 3, the image enhancement level parameter Proportion_in takes 160; when DDE_LV is level 4, the image enhancement level parameter Proportion_in takes 200; when DDE_LV is level 5, the image enhancement level parameter Proportion_in takes 240; when DDE_LV is level 6, the image enhancement level parameter Proportion_in takes 280.

[0015] Preferably, the sum of the judging parameter S_RB_BF and the parameter S_RD_SD and the parameter S_RD_mean, and generating data DATA_OUT1 based on the judging result, comprises: If S_RB_B+S_RD_SD<S_RD_mean, the generated data DATA_OUT1 takes 0; if S_RB_B+S_RD_SD≥S_RD_mean, the generated data DATA_OUT1 takes S_RB_B+S_RD_SD- S_RD_mean. Preferably, the calculation of the matrix variance variance through the matrix X4 and the determination of whether the data output by the second module is DATA_OUT1 or DATA_OUT2 according to the variance variance include: If variance ≥ 300, it is judged as edge, and the data output by the second module is DATA_OUT1; if variance < 300, it is judged as background, and the data output by the second module is DATA_OUT2.

[0016] In a second aspect, an embodiment of the present application provides an electronic device, comprising the aforementioned infrared imaging processing system.

[0017] The above-mentioned infrared imaging system, electronic device and computer-readable storage medium based on FPGA collect infrared signals through infrared detectors and convert the collected infrared signals into electrical signals; the infrared detector driving circuit converts the electrical signals into original 64-bit parallel digital signals; the FPGA processing system processes the original 64-bit parallel binary digital signals in real time and outputs the processed infrared data stream; the interface driving circuit converts the infrared data stream output by FPGA into a composite synchronous video broadcast signal; and the CRT display displays the composite synchronous video broadcast signal. Among them, the FPGA processing system uses infrared denoising and enhancement algorithms to make the infrared image retain more details, with better denoising effect and higher imaging quality.

[0018] Compared with the prior art, the present invention has the following advantages and beneficial effects: Through the infrared denoising and enhancement algorithm, the infrared image retains more details and the background becomes smoother. The entire FPGA-based infrared imaging system has the advantages of good real-time performance, significant denoising effect, and ideal enhancement effect. It can effectively improve the quality of infrared images and provide better support for subsequent applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The overall flow chart of the infrared detector system based on FPGA design provided by the embodiment of the present invention; Figure 2 It is a schematic diagram of the processing flow of the FPGA processing system; Figure 3 A schematic diagram of the algorithm flow of infrared denoising and enhancement provided in an embodiment of the present application; Figure 4 A diagram of the internal framework of the Ti60F100 chip provided in the embodiment of the present application; Figure 5 This is a diagram showing the effect before and after the infrared denoising and enhancement algorithm provided in the embodiment of the present application is executed; Figure 6 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0021] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0022] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the presence of the described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, “A, B, or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0023] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0024] It should be noted that in this article, step codes such as S1 and S2 are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the order. When implementing the step, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the scope of protection of this application.

[0025] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0027] Figure 1 The overall flow chart of the infrared detector system based on FPGA design is provided; Figure 2 For a schematic diagram of the FPGA processing system processing flow, see Figure 1 The system includes: an infrared detector, an infrared detector driving circuit, an FPGA processing system, an interface driving circuit and a CRT display.

[0028] The infrared detector is used to collect infrared signals and convert the collected infrared signals into electrical signals; Among them, the infrared detector used is Anhui Guangzhi's ceramic package detector, model VL0612VC. This detector is based on ceramic packaging technology, with a pixel of 640x512 and a pixel pitch of 12μm. This solution is also compatible with the application of 640x512 and 384x288 resolution infrared detectors from infrared detector manufacturers such as Arrow Optoelectronics and Hikvision. This product is widely used in industrial temperature measurement, security, vehicle night vision, outdoor search, smart buildings and fire protection.

[0029] The infrared detector driving circuit is used to convert the electrical signal into an original 64-bit parallel digital signal; Specifically, the conversion of electrical signals into digital signals is an important process in modern communication and signal processing. This process involves the following key steps: Sampling: Sampling is the discretization of continuous signals in time, that is, collecting instantaneous values ​​point by point on the original analog signal at specific time intervals. The sampling frequency is the number of samples collected per second. The higher the sampling frequency, the closer the obtained discrete signal is to the original analog signal, but it also requires higher actual circuits, and the calculation and storage costs also increase. If the sampling frequency is too low, it may cause information loss, and in severe cases, the signal will be distorted and unusable. Quantization: Quantization is to quantize the amplitude of the sampled signal into a certain discrete value, that is, to convert the continuous analog signal into a discrete digital signal. The more quantization bits, the smaller the quantization error, and the better the quantization result. Coding: Coding is to convert the quantized signal into binary code, that is, to convert the discrete digital signal into a digital quantity. This process is implemented by a parallel comparison circuit or a successive approximation circuit to convert the quantized discrete signal into the corresponding original 64-bit parallel digital signal.

[0030] The FPGA processing system is used to process the original 64-bit parallel digital signal in real time and output a processed infrared data stream; Specifically, see Figure 4 The FPGA solution used is the Efinix Ti60F100 ultra-small 60K FPGA. Efinix has some unique achievements in low-power, small-size, high-performance FPGAs. Efinix Titanium Series FPGA: The Ti60F100 has 60K logic units, high-speed I / O that can be configured for various protocols, and built-in SPI Flash and Hyper-RAM, all of which are included in a 5.5*5.5mm micro package with only 0.5mm pitch, helping customers solve product size and FPGA performance issues. The chip's built-in framework diagram can be found in Figure 4 .

[0031] The original 64-bit parallel digital signal input into the FPGA processing system is processed by using an infrared denoising and enhancement algorithm and an AGC algorithm to obtain a processed infrared data stream.

[0032] The infrared denoising and enhancement algorithm includes a first module and a second module. Figure 3 , the first module includes: The original 64-bit parallel digital signal is windowed by 3*3 in the FPGA processing system to obtain a matrix X1. , wherein data11-data33 are the original 64-bit parallel digital signals; The matrix X1 is multiplied by the boundary coefficient coefxx to obtain the matrix X2, , Specifically, the matrix X1 is multiplied by the boundary coefficient coefxx to obtain the matrix X1' , when the matrix X1' is at the image boundary, some pixel values ​​in the matrix , , and If the pixel exceeds the boundary range, its boundary coefficient coefxx is set to 0, so that it does not participate in subsequent calculations. The boundary coefficients of the remaining pixel values ​​are set to values ​​between 0 and 1, and then the matrix X2 is obtained, where data32_plus=data32*coefxx, data23_plus= data23*coefxx, data21_plus=data21*coefxx, data12_plus= data12*coefxx; Calculate the average value of the matrix X2, and use the average value as the weak filtering value; The output data of the dynamic data exchange mode (DDE_mode) is used as the output data of the first module, wherein the output data of the dynamic data exchange mode is divided into two types, namely, when DDE_mode=0, the output data of the first module is data22, and when DDE_mode=1, the output data of the first module is the weak filtering value.

[0033] The second module includes: The data output by the first module is windowed to obtain a 5*5 pixel matrix X3. , The pixel matrix X3 is used as an observation window, and the size of the observation window is 5*5 pixels; The matrix X3 is multiplied by the boundary coefficient coefxx to obtain the matrix X4, ; Specifically, the matrix X3 is multiplied by the boundary coefficient coefxx to obtain the matrix By setting DATAxx_plus=DATAxx*coefxx, the value of xx is 00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 25, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, and the obtained matrix is ​​transformed into the matrix X4; The matrix X4 is multiplied by the threshold coefficient coefxx_2 to obtain the matrix X5, Specifically, the matrix X4 is multiplied by the threshold coefficient coefxx_2 to obtain the matrix By setting DATAxx_plus_x=DATAxx_plus*coefxx_2, the value of xx is 00, 01, 02, 03, 04, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, the obtained matrix is ​​transformed into matrix X5; The matrix X5 is multiplied by twice the threshold value threshold*2 to obtain a matrix X6, wherein the threshold value threshold is a preset value. ; Specifically, the matrix X5 is multiplied by twice the threshold value threshold*2 to obtain the matrix By setting DATAxx_plus_2x = DATAxx_plus_x * threshold * 2, the value of xx is 00, 01, 02, 03, 10, 11, 12, 13, 14, 20, 21, 23, 24, 30, 31, 32, 33, 34, 40, 41, 42, 43, 44, transform the obtained matrix into the matrix X6; Obtain matrix X8 based on the matrix X5 ; Based on the matrix X6, the matrix X7 is obtained By obtaining the sum of all elements in the matrix and dividing it by the number of elements, the average value S_BF1 of the matrix X7 and the average value S_BF_x1 of the matrix X8 are obtained, and the parameter S_D1 is calculated, wherein the parameter S_D1 = (S_BF_x1+8192)-S_BF1, and the value of the parameter S_D2 is determined according to the parameter S_D1; Specifically, judging the value of S_D2 according to the value of S_D1 includes: If S_D1 ≥ 8192: (S_D1<=8192+32) then S_D2<=S_D1; (S_D1<=8192+64) then S_D2<=S_D1[63:1]+4096+16; (S_D1<=8192+128) then S_D2<=S_D1[63:2]+6144+32; (S_D1<=8192+256) then S_D2<=S_D1[63:3]+7168+48; else then S_D2<=S_D1[63:4]+7680+64; If S_D1<8192: (S_D1>=8192-32) then S_D2<=S_D1; (S_D1>=8192-64) then S_D2<=S_D1[63:1]+4096-16; (S_D1>=8192-128) then S_D2<=S_D1[63:2]+6144-32; (S_D1>=8192-256) then S_D2<=S_D1[63:3]+7168-48; else then S_D2<=S_D1[63:4]+7680-64; Among them, S_D1[63:1] represents the value after taking the characters from the 63rd to the 1st bit of S_D1, S_D1[63:2] represents the value after taking the characters from the 63rd to the 2nd bit of S_D1, S_D1[63:3] represents the value after taking the characters from the 63rd to the 3rd bit of S_D1, and S_D1[63:4] represents the value after taking the characters from the 63rd to the 4th bit of S_D1.

[0034] The calculating the values ​​of parameters S_RD_SD, S_RD_mean and S_RB_BF based on the S_D2 value includes: S_RD_SD= S_D2 * Proportion_in; S_RD_mean= {Proportion_in,7'd0} S_RB_BF=S_BF_x1, Among them, Proportion_in is an image enhancement level parameter, corresponding to different image enhancement levels (DDE_LV); {Proportion_in,7'd0} means adding 7 zeros after the binary representation value of the image enhancement level parameter Proportion_in. When DDE_LV is level 0, the image enhancement level parameter Proportion_in takes 0; when DDE_LV is level 1, the image enhancement level parameter Proportion_in takes 80; when DDE_LV is level 2, the image enhancement level parameter Proportion_in takes 120; when DDE_LV is level 3, the image enhancement level parameter Proportion_in takes 160; when DDE_LV is level 4, the image enhancement level parameter Proportion_in takes 200; when DDE_LV is level 5, the image enhancement level parameter Proportion_in takes 240; when DDE_LV is level 6, the image enhancement level parameter Proportion_in takes 280. DDE_LV has seven levels from 0 to 6.

[0035] Determine the size of the sum of the parameter S_RB_BF and the parameter S_RD_SD and the parameter S_RD_mean, and generate data DATA_OUT1 based on the determination result; If S_RB_B+S_RD_SD<S_RD_mean, the generated data DATA_OUT1 takes 0; if S_RB_B+S_RD_SD≥S_RD_mean, the generated data DATA_OUT1 takes S_RB_B+S_RD_SD-S_RD_mean.

[0036] Calculate the average value of the matrix X4, and use the average value of the matrix X4 as data DATA_OUT2; Calculate the variance of the matrix X4, and determine whether the data output by the second module is DATA_OUT1 or DATA_OUT2 according to the variance, and finally obtain an image processed by the infrared denoising and enhancement algorithm. Figure 5 ,from Figure 5 It can be seen that the image processed by infrared denoising and enhancement algorithm retains more image details and the background is processed more smoothly.

[0037] Specifically, the obtaining of the matrix X8 based on the matrix X5 and the obtaining of the matrix X7 based on the matrix X6 include: Taking the central pixel value data22 of the matrix X5 and the matrix X6 as the standard, the threshold threshold is set. Currently, the 0-3 levels in the FPGA program correspond to thresholds of 0, 8, 12, and 20 respectively. The threshold coefficient of the pixel points in the matrix whose pixel values ​​are greater than DATA22+threshold or less than DATA22-threshold is set to 0, and the matrix X8 and the matrix X7 are obtained. The selection of the threshold threshold is based on multiple FPGA system processings and is determined by comparing the final processing results, and changes with the increase in the level of the image.

[0038] Specifically, the calculating the matrix variance variance through the matrix X4, and judging whether the data output by the second module is DATA_OUT1 or DATA_OUT2 according to the variance variance, includes: If the matrix variance variance≥300, it is judged as edge, and the data output by the second module is DATA_OUT1; if the matrix variance variance<300, it is judged as background, and the data output by the second module is DATA_OUT2. .

[0039] The interface driving circuit is used to convert the infrared data stream output by the FPGA into a composite synchronous video broadcast signal; Specifically, the composite synchronous video broadcast signal usually includes a video signal, a synchronization signal, a chrominance signal, and a brightness signal. The corresponding signals are generated by designing the FPGA logic according to the format of the composite synchronous video broadcast signal. Including the encoding of video data, the generation of synchronization signals, the modulation of chrominance and brightness signals, etc. Perform timing control: ensure that each signal output by the FPGA is generated at the correct time point to meet the timing requirements of the composite synchronous video broadcast signal. High-precision clocks and counters are required. Perform level conversion: convert the digital signal output by the FPGA into an analog signal that meets the level requirements of the composite synchronous video broadcast signal. This requires the use of DAC (digital-to-analog converter) and other analog circuits. Test and debug: use an oscilloscope and other test equipment to check whether the signal output by the FPGA meets the specifications of the composite synchronous video broadcast signal. Adjust the FPGA logic and circuit parameters as needed until the output signal meets the requirements.

[0040] The CRT display is used to display the composite synchronous video broadcast signal.

[0041] Based on the same inventive concept as the above embodiments, the embodiments of the present invention further provide an electronic device, such as Figure 6 As shown, the device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 6 The processor 310 shown in the figure is not used to indicate that the number of the processor 310 is one, but is only used to indicate the positional relationship of the processor 310 relative to other devices. In actual applications, the number of the processor 310 may be one or more; similarly, Figure 6 The memory 311 shown in the figure has the same meaning, that is, it is only used to refer to the position relationship of the memory 311 relative to other devices. In practical applications, the number of memories 311 can be one or more. When the processor 310 runs the computer program, the fault diagnosis method of the engineering machinery control system is implemented.

[0042] The device may also include: at least one network interface 312. The various components in the device are coupled together via a bus system 313. It is understood that the bus system 313 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 6 Various buses are labeled as bus system 313.

[0043] The memory 311 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).

[0044] The memory 311 described in the embodiment of the present invention is intended to include, but is not limited to, these and any other suitable types of memory. The memory 311 in the embodiment of the present invention is used to store various types of data to support the operation of the device. Examples of these data include: any computer program used to operate on the device, such as an operating system and an application; contact data; phone book data; messages; pictures; videos, etc. Among them, the operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., which are used to implement various basic services and process hardware-based tasks. The application program may include various applications, such as a media player (Media Player), a browser (Browser), etc., which are used to implement various application services. Here, the program that implements the method of the embodiment of the present invention may be included in the application program.

[0045] Based on the same inventive concept as the above-mentioned embodiment, this embodiment further provides a computer-readable storage medium, in which a computer program is stored. The computer-readable storage medium may be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); or it may be various devices including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the computer-readable storage medium is executed by a processor, the above-mentioned fault diagnosis method of the engineering machinery control system is implemented.

[0046] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] In this document, the terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than those listed and may also include additional elements not expressly listed.

[0048] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An infrared imaging system based on FPGA, the system comprising: Infrared detector, infrared detector driving circuit, FPGA processing system, interface driving circuit and CRT display, characterized in that: The infrared detector is used to collect infrared signals and convert the collected infrared signals into electrical signals; The infrared detector driving circuit is used to convert the electrical signal into an original 64-bit parallel binary digital signal; The FPGA processing system is used to process the original 64-bit parallel binary digital signal in real time and output a processed infrared data stream; The interface driving circuit is used to convert the infrared data stream output by the FPGA into a composite synchronous video broadcast signal; The CRT display is used to display the composite synchronous video broadcast signal.

2. The system according to claim 1, characterized in that The FPGA processing system comprises: The original 64-bit parallel binary digital signal input into the FPGA processing system is processed by using an infrared denoising and enhancement algorithm and an AGC algorithm to obtain a processed infrared data stream.

3. The system according to claim 2, characterized in that The infrared denoising and enhancement algorithm includes a first module and a second module, wherein the first module is used to perform dynamic data exchange (DDE) processing on the original 64-bit parallel binary digital signal; the second module is used to determine whether the center value of the matrix is ​​the edge of the image or the background of the image, and output corresponding data based on the determination result.

4. The system according to claim 3, characterized in that The first module includes: The original 64-bit parallel binary digital signal is windowed by 3*3 in the FPGA processing system to obtain a matrix X1. , wherein data11-data33 are the original 64-bit parallel binary digital signals; The matrix X1 is multiplied by the boundary coefficient coefxx to obtain the matrix X2, , wherein the boundary coefficient coefxx is a value between 0 and 1; Calculate the average value of the matrix X2, and use the average value as the weak filtering value; The output data of the dynamic data exchange mode (DDE_mode) is used as the output data of the first module, wherein the output data of the dynamic data exchange mode is divided into two types, namely, when DDE_mode=0, the output data of the first module is the central pixel value data22 of the matrix X1 and the matrix X2, and when the DDE_mode=1, the output data of the first module is the weak filtering value.

5. The system according to claim 3, characterized in that The second module includes: The data output by the first module is windowed to obtain a 5*5 matrix X3. , where DATA00-DATA44 are 64-bit parallel binary digital signal after windowing; The matrix X3 is multiplied by the boundary coefficient coefxx to obtain the matrix X4, ； The matrix X4 is multiplied by the threshold coefficient coefxx_2 to obtain the matrix X5, The matrix X5 is multiplied by twice the threshold value threshold*2 to obtain the matrix X6 Obtain matrix X8 based on the matrix X5 Based on the matrix X6, the matrix X7 is obtained Calculate the average value S_BF1 of the matrix X7 and the average value S_BF_x1 of the matrix X8, and calculate the parameter S_D1 based on the average values ​​S_BF1 and S_BF_x1, wherein the parameter S_D1 = (S_BF_x1+8192)-S_BF1, and determine the range of the value of the random parameter S_D2 according to the value of S_D1; Based on the value of S_D2, the values ​​of parameters S_RD_SD, S_RD_mean and S_RB_BF are calculated; Determine the relative magnitudes of the sum of the parameter S_RB_BF and the parameter S_RD_SD and the parameter S_RD_mean, and generate data DATA_OUT1 based on the determination result; Calculate the average value of the matrix X4, and use the average value of the matrix X4 as data DATA_OUT2; The matrix variance variance is calculated by the matrix X4, and it is determined whether the data output by the second module is DATA_OUT1 or DATA_OUT2 according to the variance variance.

6. The system according to claim 5, characterized in that The obtaining of the matrix X8 based on the matrix X5 and the obtaining of the matrix X7 based on the matrix X6 include: Taking the central pixel value DATA22 of the matrix X5 and the matrix X6 as the standard, a threshold threshold is set, and the threshold coefficient coefxx_2 of the pixel points whose pixel values ​​in the matrix are greater than DATA22+threshold or less than DATA22-threshold is set to 0, and the threshold coefficient coefxx_2 of the remaining pixel points is set to 1, to obtain matrix X8 and matrix X7.

7. The system according to claim 5, characterized in that The step of determining the range of the value of the random parameter S_D2 according to the value of S_D1 includes: If S_D1 ≥ 8192: (S_D1<=8192+32) then S_D2<=S_D1; (S_D1<=8192+64) then S_D2<=S_D1[63:1]+4096+16; (S_D1<=8192+128) then S_D2<=S_D1[63:2]+6144+32; (S_D1<=8192+256) then S_D2<=S_D1[63:3]+7168+48; else then S_D2<=S_D1[63:4]+7680+64; If S_D1<8192: (S_D1>=8192-32) then S_D2<=S_D1; (S_D1>=8192-64) then S_D2<=S_D1[63:1]+4096-16; (S_D1>=8192-128) then S_D2<=S_D1[63:2]+6144-32; (S_D1>=8192-256) then S_D2<=S_D1[63:3]+7168-48; else then S_D2<=S_D1[63:4]+7680-64; Among them, S_D1[63:1] represents the value after taking the characters from the 63rd to the 1st bit from the parameter S_D1, S_D1[63:2] represents the value after taking the characters from the 63rd to the 2nd bit from the output parameter S_D1, S_D1[63:3] represents the value after taking the characters from the 63rd to the 3rd bit from the parameter S_D1, and S_D1[63:4] represents the value after taking the characters from the 63rd to the 4th bit from the parameter S_D1.

8. The system according to claim 4, characterized in that The calculating the values ​​of parameters S_RD_SD, S_RD_mean and S_RB_BF based on the value of S_D2 includes: S_RD_SD = S_D2 * Proportion_in S_RD_mean= {Proportion_in,7'd0} S_RB_BF=S_BF_x1 Among them, Proportion_in is an image enhancement level parameter, corresponding to different image enhancement levels (DDE_LV); {Proportion_in,7'd0} means adding 7 zeros after the binary value of the image enhancement level parameter Proportion_in. When DDE_LV is level 0, the image enhancement level parameter Proportion_in takes 0; when DDE_LV is level 1, the image enhancement level parameter Proportion_in takes 80; when DDE_LV is level 2, the image enhancement level parameter Proportion_in takes 120; when DDE_LV is level 3, the image enhancement level parameter Proportion_in takes 160; when DDE_LV is level 4, the image enhancement level parameter Proportion_in takes 200; when DDE_LV is level 5, the image enhancement level parameter Proportion_in takes 240; when DDE_LV is level 6, the image enhancement level parameter Proportion_in takes 280.

9. The system according to claim 5, characterized in that The sum of the judging parameter S_RB_BF and the parameter S_RD_SD and the parameter S_RD_mean are judged, and data DATA_OUT1 is generated based on the judging result, including: If S_RB_B+S_RD_SD<S_RD_mean, the generated data DATA_OUT1 takes a value of 0; if S_RB_B+S_RD_SD≥S_RD_mean, the generated data DATA_OUT1 takes a value of S_RB_B+S_RD_SD-S_RD_mean.

10. An electronic device, characterized in that: The infrared imaging processing system comprises the infrared imaging processing system as claimed in any one of claims 1 to 9.

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