Pixel array, image sensor and control method

Abstract

The invention provides a pixel array, an image sensor and a control method, the pixel array comprises a plurality of pixel blocks arranged in rows and columns, and each pixel block comprises a photosensitive unit, a floating diffusion active area, a gain control unit, a reset unit and a signal output unit; the photosensitive unit receives the optical signal and generates a charge signal based on the optical signal; the floating diffusion active region receives a charge signal; the gain control unit is coupled to the floating diffusion active region and is matched with the floating diffusion active region to form a modulation storage region, and a voltage signal corresponding to the charge signal is formed based on the modulation storage region; the reset unit is coupled to the floating diffusion active area and resets the floating diffusion active area. The signal output unit is coupled to the floating diffusion active region to output a voltage signal; feedback capacitance configured in the first direction is formed at the gain control unit to balance parasitic capacitance in the second direction caused by adjacent pixel blocks in the row direction. According to the invention, the problem of image color degradation caused by crosstalk due to pixel size miniaturization of an existing image sensor is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a pixel array, an image sensor and a control method. Background Art

[0002] Image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles and other applications. As the number of pixels continues to increase (for example, mobile phones have >64MP, 108MP, 200MP in recent years), the available area of ​​the chip is also constantly shrinking, which leads to the pixel size in image sensors shrinking to below sub-micron.

[0003] At the sub-micron level and above, the electrical interaction between nodes is relatively slight due to the large physical size of the pixels. However, as the pixel size enters the sub-micron level, the physical positions of key nodes are getting closer and closer, and the crosstalk (X-talk) between pixels becomes increasingly complex, resulting in the degradation of the image quality produced by the chip.

[0004] In the prior art, due to the miniaturization of pixel size, the FDs (i.e., floating diffusion active areas) of adjacent rows are getting closer and closer, which leads to the introduction of electrical coupling; in addition, in some other applications, due to the different settings of CFA (color filter), the colors of different pixels will eventually be interfered by other pixels; both of which may lead to image color degradation.

[0005] like Figure 1 As shown, taking the RGGB Bayer array as an example, generally speaking, it is hoped that the photoelectric effects of Gr pixels and Gb pixels are consistent, but in application, there will be deviations due to the influence of R pixels and B pixels; at this time, it is expected that the effects of R pixels and B pixels are the same, but it is difficult to achieve complete symmetry at the actual physical level. For example, the influence of B pixels on Gb pixels (solid line) is not equal to the influence of B pixels on Gr pixels (dotted line), which ultimately leads to color degradation of the image. In addition, some of the FDs of adjacent columns have capacitive parasitic coupling, but the capacitive parasitic coupling of adjacent row FDs is small, which aggravates the color degradation of the image.

[0006] In view of this, how to improve the image color degradation problem of image sensors is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a pixel array, an image sensor and a control method for solving the problem of image color degradation caused by crosstalk introduced by pixel size miniaturization in the prior art image sensors.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides a pixel array, comprising a plurality of pixel blocks arranged in rows and columns, wherein the pixel blocks include a photosensitive unit, a floating diffusion active area, a gain control unit, a reset unit and a signal output unit, wherein:

[0009] The photosensitive unit is used to receive a light signal and generate a charge signal based on the light signal;

[0010] The floating diffusion active area is used to receive the charge signal;

[0011] The gain control unit is coupled to the floating diffusion active area, and the gain control unit cooperates with the floating diffusion active area to form a modulation storage area to form a voltage signal corresponding to the charge signal based on the modulation storage area;

[0012] The reset unit is coupled to the floating diffusion active region and is at least used to reset the floating diffusion active region;

[0013] The signal output unit is coupled to the floating diffusion active region and is used to output the voltage signal;

[0014] A feedback capacitor in a first direction is formed at the gain control unit to balance the parasitic capacitor in a second direction caused by the pixel blocks adjacent to each other in the row, and the second direction has an angle with the first direction.

[0015] Optionally, the gain control unit includes at least one gain control transistor coupled between the reset unit and the floating diffusion active area; when the gain control unit includes two or more gain control transistors, each gain control transistor is coupled in series between the reset unit and the floating diffusion active area.

[0016] Optionally, the gain control unit is provided with a metal routing extending along a first direction, the metal routing includes at least one bending portion along a second direction, and the second direction has an angle with the first direction; wherein, in two adjacent sections of the metal routing in the first direction, each has at least one bending portion that is close to each other and influences each other to form a feedback capacitor.

[0017] Optionally, the photosensitive unit includes a photosensitive element and a corresponding transmission transistor, the gain control unit includes a gain control transistor, the reset unit includes a reset transistor, and the signal output unit includes a source follower transistor and a selection transistor, wherein:

[0018] The transfer transistors in the photosensitive unit are enclosed to form an enclosed area, the source follower transistor is arranged in the enclosed area, the floating diffusion active area is arranged in the enclosed area and is arranged on both sides of the source follower transistor, including a first floating diffusion node and a second floating diffusion node, the gain control transistor is arranged outside the enclosed area and is arranged on one side of the first floating diffusion node or the second floating diffusion node, the reset transistor and the selection transistor are arranged outside the enclosed area and are arranged between adjacent source follower transistors in a column direction;

[0019] The metal routing wire corresponding to the gain control transistor includes at least one bending portion, and in two adjacent sections of the metal routing wire in the first direction, at least one bending portion each is close to each other and affects each other.

[0020] Optionally, among the plurality of pixel blocks arranged in columns, every two adjacent pixel blocks constitute a pixel group, and in the same pixel group, two pixel blocks share the same reset transistor, and two gain control transistors correspond to a section of the metal wiring.

[0021] Optionally, in the same pixel group, the reset transistor is located outside the adjacent source follower transistor, and the metal routing includes: a first bending portion, a second bending portion, a third bending portion, a fourth bending portion, a first column routing, a second column routing, and a third column routing;

[0022] The first bending portion is connected to the first end of the first column-oriented routing and is close to and influences the third bending portion of the previous section of the metal routing. The second bending portion spans the middle end of the first column-oriented routing and the first end of the second column-oriented routing and is close to and influences the fourth bending portion of the previous section of the metal routing. The third bending portion spans the second end of the first column-oriented routing and the middle end of the third column-oriented routing and is close to and influences the first bending portion of the next section of the metal routing. The fourth bending portion is connected to the second end of the third column-oriented routing and is close to and influences the second bending portion of the next section of the metal routing. The second end of the second column-oriented routing and the first end of the third column-oriented routing are free ends. The second column-oriented routing and the third column-oriented routing are respectively coupled to the two gain control transistors of the two pixel blocks in the same pixel group.

[0023] Optionally, in the same pixel group, the reset transistor is located between adjacent source follower transistors, and the metal routing includes: a first bending portion, a second bending portion, a third bending portion, a fourth bending portion, a fifth bending portion, a sixth bending portion, a first column routing, a second column routing, and a third column routing;

[0024] The first bending portion is connected to the first end of the first column-oriented routing and is close to and influences the third bending portion of the previous section of the metal routing. The second bending portion is connected to the first end of the second column-oriented routing and is close to and influences the fourth bending portion of the previous section of the metal routing. The third bending portion is connected to the second end of the first column-oriented routing and is close to and influences the first bending portion of the next section of the metal routing. The fourth bending portion is connected to the second end of the third column-oriented routing and is close to and influences the second bending portion of the next section of the metal routing. The fifth bending portion bridges the middle end of the first column-oriented routing and the middle end of the second column-oriented routing. The sixth bending portion bridges the middle end of the first column-oriented routing and the middle end of the third column-oriented routing. The second end of the second column-oriented routing and the first end of the third column-oriented routing are free ends. The second column-oriented routing and the third column-oriented routing are respectively coupled to the two gain control transistors of the two pixel blocks in the same pixel group.

[0025] Optionally, in the same pixel group, two pixel blocks share the same selection transistor; or, in different pixel groups, two adjacent pixel blocks share the same selection transistor.

[0026] Optionally, the photosensitive unit includes four photosensitive elements and corresponding four transmission transistors, the four photosensitive elements are arranged in an array, the four transmission transistors are in a strip shape, and are arranged at opposite corners of the four photosensitive elements at an inclined angle to form the enclosed area;

[0027] The first floating diffusion node and the second floating diffusion node are respectively arranged in the regions facing each other of the two transfer transistors arranged in a column direction, and the source follower transistor is arranged on the center connection line between the first floating diffusion node and the second floating diffusion node.

[0028] Optionally, the photosensitive unit includes a photosensitive element and a corresponding transmission transistor, the gain control unit includes a gain control transistor, the reset unit includes a reset transistor, and the signal output unit includes a source follower transistor and a selection transistor, wherein:

[0029] The transfer transistors in the photosensitive unit are enclosed to form an enclosed area, the source follower transistor is arranged in the enclosed area, the floating diffusion active area is arranged in the enclosed area and on one side of the source follower transistor, the gain control transistor is arranged outside the enclosed area and on one side of the floating diffusion active area, the reset transistor is arranged on a side of the gain control transistor away from the floating diffusion active area, and the selection transistor is arranged outside the enclosed area and above or below the source follower transistor;

[0030] The metal routing wire corresponding to the gain control transistor includes at least one bending portion, and in two adjacent sections of the metal routing wire in the first direction, at least one bending portion each is close to each other and affects each other.

[0031] Optionally, the metal routing is arranged in an interconnection structure; and / or the photosensitive unit includes two photosensitive elements and corresponding two transmission transistors, the two photosensitive elements share the floating diffusion active area, the signal output unit and the gain control unit, or the photosensitive unit includes one photosensitive element, or the photosensitive unit includes four photosensitive elements and corresponding four transmission transistors, the four photosensitive elements share the floating diffusion active area, the signal output unit and the gain control unit.

[0032] The present invention also provides an image sensor, comprising the pixel array as described in any one of the above items.

[0033] Optionally, the signal output unit in each pixel block includes a source follower transistor and a selection transistor. Among the multiple selection transistors in the column, two adjacent selection transistors are located in the same readout group, and the two selection transistors in the readout group are connected to different column lines.

[0034] Optionally, corresponding selection transistors in different readout groups are connected to the same or different column lines.

[0035] Optionally, the readout group includes a first pixel readout row and a second pixel readout row, the first pixel readout row includes a first filter area and a second filter area arranged alternately, the second pixel readout row includes a third filter area and a fourth filter area arranged alternately, and the adjacent first filter area, the second filter area, the third filter area and the fourth filter area constitute a pixel combination.

[0036] Optionally, the second filter area and the third filter area have the same configuration, the pixel combination is arranged in a Bayer-based array, and each filter area is set corresponding to the pixel block; wherein, two pixel readout rows in the readout group are arranged adjacent to each other, and two adjacent pixel blocks in adjacent readout groups in the same column share the same metal routing; or, two pixel readout rows in the readout group and two pixel readout rows in adjacent readout groups are arranged alternately, and the pixel blocks in two corresponding positions in adjacent readout groups in the same column share the same metal routing.

[0037] The present invention further provides a control method for the image sensor as described in any one of the above items, when the gain control unit is provided with the metal wiring extending along the first direction and the metal wiring includes at least one bending portion along the second direction, comprising:

[0038] In the low conversion gain mode, the two pixel blocks corresponding to the two adjacent sections of the metal wiring in the column are read out simultaneously through different column lines, so as to introduce feedback capacitance through the bending parts that are close to each other and affect each other.

[0039] Optionally, in the high conversion gain mode, the pixel blocks in the column direction are read out row by row, or the two pixel blocks corresponding to two adjacent sections of the metal wiring in the column direction are read out simultaneously through different column lines.

[0040] As described above, the pixel array, image sensor and control method of the present invention form a feedback capacitor configured in a first direction at the gain control unit, such as by utilizing the proximity and mutual influence of the bent portions in two adjacent sections of metal routing (corresponding to the gain control unit) to form a feedback capacitor, so as to balance the parasitic capacitance in the second direction caused by the adjacent pixel blocks in the row upward, improve the image color degradation problem caused by the crosstalk introduced by the miniaturization of the pixel size of the image sensor, and improve the image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram showing crosstalk introduced into existing image sensors due to the miniaturization of pixel size.

[0042] Figure 2 Shown is a circuit diagram of a pixel array of the present invention.

[0043] Figure 3 Display as Figure 2 A schematic diagram of an arrangement structure of the circuit shown.

[0044] Figure 4 Display as Figure 3 A schematic diagram of a filter area configuration of the arrangement structure shown.

[0045] Figure 5 Display as Figure 2 The circuit shown is a timing diagram for simultaneous readout of two rows in low conversion gain mode.

[0046] Figure 6 Display as Figure 2 The circuit shown is a timing diagram for simultaneous readout of two rows in high conversion gain mode.

[0047] Figure 7 Another circuit diagram of the pixel array of the present invention is shown.

[0048] Figure 8 Display as Figure 7 A schematic diagram of the arrangement structure of the circuit shown.

[0049] Figure 9-11 Display as Figure 8 Schematic diagram of the configuration of different filter areas of the arrangement structure shown.

[0050] Figure 12-14 Shown is a schematic diagram of the arrangement structure corresponding to different pixel arrays.

[0051] Component number description

[0052] 100 pixel array

[0053] 110 pixel block

[0054] 111 Photosensitive unit

[0055] 112 Reset unit

[0056] 113 Gain Control Unit

[0057] 114 Signal output unit DETAILED DESCRIPTION

[0058] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] See also Figures 2 to 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0060] Embodiment 1

[0061] like Figure 2 and Figure 7 As shown, this embodiment provides a pixel array 100, including a plurality of pixel blocks 110 arranged in rows and columns; the pixel block 110 includes a photosensitive unit 111, a floating diffusion active area, a reset unit 112, a gain control unit 113 and a signal output unit 114. Among them:

[0062] The photosensitive unit 111 is used to receive a light signal and generate a charge signal based on the light signal.

[0063] Specifically, the photosensitive unit 111 includes at least one photosensitive element and a corresponding transfer transistor; wherein the control end of the transfer transistor receives a transmission control signal, the first end is coupled to the corresponding floating diffusion active area, the second end is coupled to the first end of the photosensitive element, and the second end of the photosensitive element is coupled to the reference potential.

[0064] As an example, the photosensitive element can be any one of a photodiode, a grating or a photoconductor, and the transfer transistor can be any one of an NMOS tube or a PMOS tube; in this embodiment, the photosensitive element is a photodiode, such as a pin-type photodiode, and the transfer transistor is an NMOS tube.

[0065] Take the photosensitive unit 111 including four photodiodes PD1-PD4 and four NMOS tubes M11-M14 as an example; the anode end of the photodiode PD1-PD4 is connected to the reference potential, the cathode end is correspondingly connected to the source end of the NMOS tube M11-M14, the gate end of the NMOS tube M11-M14 is correspondingly connected to the transmission control signal TX1-TX4, and the drain end is connected to the floating diffusion active area (such as FD_n-1). In practical applications, the reference potential is usually the reference ground potential. Of course, the reference potential can also be a negative potential, which has no substantial impact on this embodiment.

[0066] The reset unit 112 is coupled to the floating diffusion active area, and the gain control unit 113 is coupled to the floating diffusion active area (e.g., the reset unit 112 is coupled to the floating diffusion active area via the gain control unit 113); wherein, the floating diffusion active area is used to receive the charge signal; the reset unit 112 is used to reset the floating diffusion active area; the gain control unit 113 cooperates with the floating diffusion active area to form a modulation storage area to form a voltage signal corresponding to the charge signal based on the modulation storage area.

[0067] Specifically, the reset unit 112 includes a reset transistor, and the gain control unit 113 includes at least one gain control transistor; when the gain control unit 113 includes one gain control transistor, the gain control transistor is coupled between the reset unit 112 and the floating diffusion active area; when the gain control unit 113 includes two or more gain control transistors, each gain control transistor is coupled in series between the reset unit 112 and the floating diffusion active area. It should be noted that when the gain control unit 113 includes multiple gain control transistors, the capacity of the modulation storage area is adjusted by controlling the opening and closing of each gain control transistor, thereby adding more conversion gain modes.

[0068] As an example, the reset transistor may be any one of an NMOS transistor and a PMOS transistor, and the gain control transistor may be any one of an NMOS transistor and a PMOS transistor; in this embodiment, the reset transistor and the gain control transistor are NMOS transistors.

[0069] Taking the reset transistor including the NMOS tube M2 and the gain control transistor including the NMOS tube M3 as an example; the gate end of the NMOS tube M2 is connected to the reset control signal (such as RST_n), the drain end is connected to the first pixel power supply (such as RSTD_n), and the source end is connected to the drain end of the NMOS tube M3; the gate end of the NMOS tube M3 is connected to the gain control signal (such as DCG_n-1), and the source end is connected to the floating diffusion active area (such as FD_n-1).

[0070] Among them, the corresponding reset transistor is turned on when the reset control signal is valid and the first pixel power supply is at a high potential; in practical applications, the first pixel power supply can be designed to be always at a high potential, and the corresponding reset transistor can be turned on and off by controlling the reset control signal; the reset control signal can also be designed to be always valid, and the corresponding reset transistor can be turned on and off by controlling the first pixel power supply; of course, the first pixel power supply and the reset control signal can also be controlled at the same time to turn the corresponding reset transistor on and off.

[0071] The signal output unit 114 is coupled to the floating diffusion active region and is configured to output a voltage signal.

[0072] Specifically, the signal output unit 114 includes a source follower transistor and a selection transistor; the control end of the source follower transistor is coupled to the floating diffusion active area, the first end is coupled to the second pixel power supply, and the second end is coupled to the first end of the selection transistor; the control end of the selection transistor receives a selection control signal, and the second end outputs a pixel signal (including a reset signal and an image signal).

[0073] As an example, the source follower transistor may be any one of an NMOS transistor and a PMOS transistor, and the selection transistor may be any one of an NMOS transistor and a PMOS transistor; in this embodiment, the source follower transistor and the selection transistor are NMOS transistors.

[0074] Take the source follower transistor including NMOS tube M4 and the selection transistor including NMOS tube M5 as an example; the gate end of NMOS tube M4 is connected to the floating diffusion active area (such as FD_n-1), the drain end is connected to the second pixel power supply (such as SFD_n-1), and the source end is connected to the drain end of NMOS tube M5; the gate end of NMOS tube M5 is connected to the selection control signal (such as RS_n), and the source end outputs the pixel signal. Among them, when the second pixel power supply is at a high potential, the corresponding source follower transistor has an output. In practical applications, the design of the second pixel power supply can be used to control whether the corresponding source follower transistor outputs.

[0075] In the pixel block 110 of this embodiment, a feedback capacitor configured in a first direction is formed at the gain control unit 113 to balance the parasitic capacitance (i.e., crosstalk) in a second direction caused by the adjacent pixel blocks in the row, and an angle is formed between the second direction and the first direction; for example, a longitudinal feedback capacitor may be formed at the gain control unit 113 to balance the lateral parasitic capacitance caused by the adjacent pixel blocks 110 in the row; in order to facilitate subsequent image processing, the longitudinal feedback capacitor is used to offset the lateral parasitic capacitance, reduce the influence of signal crosstalk on the image color, and improve the image color degradation problem. Among them, the feedback capacitor can be a device capacitor or a parasitic capacitor of a metal wiring; in practical applications, in order to reduce the pixel size, the parasitic capacitance of a metal wiring is generally used.

[0076] In a possible implementation, the gain control unit 113 is provided with a metal routing extending along a first direction, the metal routing includes at least one bend along a second direction, and an angle is formed between the second direction and the first direction; wherein, in two adjacent metal routing sections in the first direction, each has at least one bend that is close to each other and influences each other to form a feedback capacitor. Of course, in other implementations, the metal routing corresponding to the gain control unit 113 may not include a bend along the second direction, as long as the two adjacent metal routing sections in the first direction form a feedback capacitor due to mutual influence, such as the tail of one metal routing section and the head of another metal routing section are close to each other and influence each other to form a feedback capacitor, or two metal routing sections parallel to the first direction form a feedback capacitor, etc. In addition, when the metal routing includes a bend, the shape of the bend can be a straight line, a folded line, a ring, an irregular shape, etc., and this embodiment does not limit this. In addition, a feedback capacitor is formed at the gain control unit 113, which can be configured based on the drain of the gain control transistor of the gain control unit 113. For example, a metal wiring can be set at the drain of the gain control transistor through an interconnection structure. The metal wiring can be an additionally arranged structure or can be implemented by utilizing an existing structure in the pixel circuit to simplify the structural arrangement.

[0077] In a first embodiment, the arrangement structure of the pixel array 100 is as follows: the transfer transistors in the photosensitive unit 111 are enclosed to form an enclosed area, the source follower transistor is arranged in the enclosed area, the floating diffusion active area is arranged in the enclosed area and is arranged on both sides of the source follower transistor, including a first floating diffusion node and a second floating diffusion node, the gain control transistor is arranged outside the enclosed area and is arranged on one side of the first floating diffusion node or the second floating diffusion node, the reset transistor and the selection transistor are arranged outside the enclosed area and are arranged between adjacent source follower transistors in the column direction, such as Figure 3 and Figure 8As shown; wherein, the metal routing corresponding to the gain control transistor includes at least one bending portion, and in two adjacent sections of the metal routing in the first direction, each has at least one bending portion that is close to each other and influences each other to form a longitudinal feedback capacitor. In this example, the first direction is the column direction of the pixel array, and the second direction is the row direction of the pixel array, and the two are arranged vertically.

[0078] As an example, the photosensitive unit 111 includes four photosensitive elements and corresponding four transfer transistors, the four photosensitive elements are arranged in an array, the four transfer transistors are in the shape of strips, and are arranged at opposite corners of the four photosensitive elements at an inclined angle to form an enclosed area; the first floating diffusion node and the second floating diffusion node are respectively arranged in opposite areas of the two transfer transistors arranged in a column direction, and the source follower transistor is arranged on the center connection line of the first floating diffusion node and the second floating diffusion node, so that the distance between the gate terminal of the source follower transistor and the floating diffusion active area is shorter.

[0079] Of course, the photosensitive unit 111 may also include other numbers of photosensitive elements and corresponding transmission transistors, which has no substantial impact on this embodiment. It should be noted that the enclosed area can be considered as the outline shape formed by the transmission transistor, not a strict enclosure, which can be understood by those skilled in the art.

[0080] As an optional solution, in the multiple pixel blocks 110 in the column direction, two adjacent pixel blocks 110 constitute a pixel group, and the column direction of the pixel array is composed of multiple adjacently arranged pixel groups. In the same pixel group, two pixel blocks 110 share the same reset transistor, and two gain control transistors correspond to a metal wiring section, such as Figure 2 and Figure 7 Further, in the same pixel group, two pixel blocks 110 share the same selection transistor, such as Figure 2 Alternatively, in different pixel groups, two adjacent pixel blocks 110 share the same selection transistor, such as Figure 7 shown.

[0081] For the case where the reset transistor is located outside the adjacent source follower transistor in the same pixel group, such as Figure 3 As shown, it can correspond to Figure 2In the circuit diagram shown, the metal routing includes: a first bend R1, a second bend R2, a third bend R3, a fourth bend R4, a first column routing C1, a second column routing C2 and a third column routing C3; the first bend R1 is connected to a first end of the first column routing C1 and is close to and affects the third bend R3 of the previous metal routing; the second bend R2 bridges the middle end of the first column routing C1 and the first end of the second column routing C2 and is close to and affects the fourth bend R4 of the previous metal routing; the third bend R4 is connected to a first end of the first column routing C1 and the second column routing C2 and is close to and affects the fourth bend R4 of the previous metal routing; The bend R3 bridges the second end of the first column routing C1 and the middle end of the third column routing C3, and is close to and influences the first bend R1 of the next section of the metal routing. The fourth bend R4 is connected to the second end of the third column routing C3, and is close to and influences the second bend R2 of the next section of the metal routing. The second end of the second column routing C2 and the first end of the third column routing C3 are free ends. The second column routing C2 and the third column routing C3 are respectively coupled to two gain control transistors of two pixel blocks 110 in the same pixel group.

[0082] Taking the case where two pixel blocks 110 in the same pixel group share the same selection transistor as an example, Figure 3 The row where the first pixel block of the pixel group is located is defined as the n-1 row, the row above it is defined as the n-2 row, and the two rows below it are defined as the n row and the n+1 row respectively; in this scheme, when the n row and the n+1 row are read out simultaneously in the low conversion gain mode, in the two adjacent metal routings corresponding to the pixel readout row where the n row is located and the pixel readout row where the n+1 row is located, the third bend R3 in the metal routing corresponding to the pixel readout row where the n row is located and the first bend R1 in the metal routing corresponding to the pixel readout row where the n+1 row are located interact with each other to form a longitudinal feedback capacitor, and the fourth bend R4 in the metal routing corresponding to the pixel readout row where the n row is located and the second bend R2 in the metal routing corresponding to the pixel readout row where the n+1 row are located interact with each other to form another longitudinal feedback capacitor.

[0083] For the case where the reset transistor is located between adjacent source follower transistors in the same pixel group, such as Figure 8 As shown, it can correspond to Figure 7In the circuit diagram shown, the metal routing includes: a first bend R1, a second bend R2, a third bend R3, a fourth bend R4, a fifth bend R5, a sixth bend R6, a first column routing C1, a second column routing C2 and a third column routing C3; the first bend R1 is connected to a first end of the first column routing C1 and is close to and affects the third bend R3 of the previous section of the metal routing, the second bend R2 is connected to a first end of the second column routing C2 and is close to and affects the fourth bend R4 of the previous section of the metal routing, the third bend R3 is connected to a second end of the first column routing C1 and is close to the fourth bend R4 of the previous section of the metal routing, The first bends R1 of the metal routing are close to each other and influence each other, the fourth bend R4 is connected to the second end of the third column routing C3 and is close to and influences each other with the second bend R2 of the next section of the metal routing, the fifth bend R5 bridges the middle end of the first column routing C1 and the middle end of the second column routing C2, the sixth bend R6 bridges the middle end of the first column routing C1 and the middle end of the third column routing C3, the second end of the second column routing C2 and the first end of the third column routing C3 are free ends, the second column routing C2 and the third column routing C3 are respectively coupled to two gain control transistors of two pixel blocks 110 in the same pixel group.

[0084] Taking two adjacent pixel blocks 110 in different pixel groups sharing the same selection transistor as an example, Figure 8 The row where the first pixel block of a pixel group is located is defined as the nth row, and the three rows below it are defined as the n+1th row, the n+2th row and the n+3th row respectively; in this scheme, when the nth row and the n+2th row are read out simultaneously in the low gain mode, in the adjacent metal routing lines corresponding to the pixel readout line where the nth row is located and the pixel readout line where the n+2th row is located, the third bend R3 in the metal routing line corresponding to the pixel readout line where the nth row is located and the first bend R1 in the metal routing line corresponding to the pixel readout line where the n+2th row are located interact with each other to form a longitudinal feedback capacitor, and the fourth bend R4 in the metal routing line corresponding to the pixel readout line where the nth row is located and the second bend R2 in the metal routing line corresponding to the pixel readout line where the n+2th row are located interact with each other to form another longitudinal feedback capacitor.

[0085] In practical applications, by designing the length, width and other parameters of the bends that affect each other in two adjacent metal traces, the value of the vertical feedback capacitor can be reasonably designed, so that the sum of the vertical feedback capacitor and the horizontal parasitic capacitor can be balanced. In addition, the capacitance of the feedback capacitor to be formed can be configured according to actual needs.

[0086] In the second embodiment, the arrangement structure of the pixel array 100 is as follows: the transfer transistors in the photosensitive unit 111 are enclosed to form an enclosed area, the source follower transistor is arranged in the enclosed area, the floating diffusion active area is arranged in the enclosed area and on one side of the source follower transistor, the gain control transistor is arranged outside the enclosed area and on one side of the floating diffusion active area, the reset transistor is arranged on the side of the gain control transistor away from the floating diffusion active area, and the selection transistor is arranged outside the enclosed area and above or below the source follower transistor, such as Fig.12 As shown; of course, the floating diffusion active region can also be arranged on both sides of the source follower transistor in the enclosed area, including the first floating diffusion node and the second floating diffusion node, and the gain control transistor is arranged outside the enclosed area and on one side of the first floating diffusion node or the second floating diffusion node, such as Fig.13 As shown. The metal routing corresponding to the gain control transistor includes at least one bend, and in two adjacent metal routing sections in the first direction, each has at least one bend close to each other and influences each other to form a longitudinal feedback capacitor. Of course, other feedback capacitor formation methods are also possible; in this example, the first direction is the column direction of the pixel array, and the second direction is the row direction of the pixel array, and the two are arranged vertically.

[0087] As an example, the metal routing is arranged in an interconnect structure, which is an existing structure in the image sensor that is prepared on a semiconductor substrate and is used to interconnect various transistors. The structure includes multiple metal layers, and feedback can be formed based on each metal layer.

[0088] As an example, the photosensitive unit 111 includes two photosensitive elements and corresponding two transmission transistors, and the two photosensitive elements share a floating diffusion active area, a signal output unit and a gain control unit, such as Fig.12 As shown;

[0089] As an example, the photosensitive unit 111 includes four photosensitive elements and corresponding four transmission transistors, and the four photosensitive elements share a floating diffusion active area, a signal output unit and a gain control unit, such as Fig.13 shown.

[0090] In the third embodiment, the arrangement structure of the pixel array 100 is as follows: the transfer transistors in the photosensitive unit 111 are enclosed to form an enclosed area, the floating diffusion active area is arranged in the enclosed area, the gain control transistor is arranged below the enclosed area, the reset transistor is arranged below the gain control transistor, the source follower transistor is arranged above the enclosed area, and the selection transistor is arranged on one side of the source follower transistor, such as Fig.14As shown; wherein, the metal routing corresponding to the gain control transistor includes at least one bend, and in two adjacent sections of the metal routing in the first direction, each has at least one bend that is close to each other and influences each other to form a longitudinal feedback capacitor. Of course, in other implementations, other feedback capacitor formation methods may also be used; in this example, the first direction is the column direction of the pixel array, and the second direction is the row direction of the pixel array, and the two are arranged vertically.

[0091] As an example, the metal wiring is arranged in an interconnect structure. The interconnect structure is a structure currently prepared on a semiconductor substrate in an image sensor for interconnecting various transistors, including multiple metal layers, and feedback can be formed based on each metal layer.

[0092] As an example, the photosensitive unit 111 includes a photosensitive element and a corresponding transmission transistor, such as Fig.14 As shown, in this example, the enclosed area formed by the transfer transistor can be understood as the area away from the other side of the photoelectric conversion element.

[0093] It should be noted that the second and third embodiments form the longitudinal feedback capacitor in the same manner as the first embodiment, for example, the longitudinal feedback capacitor is formed by mutual influence of the bending portions of two adjacent metal traces in the first direction, which will not be elaborated here.

[0094] Embodiment 2

[0095] This embodiment provides an image sensor, including the pixel array 100 as described in the first embodiment; further including a readout circuit, which reads out pixel signals in the pixel array 100 through column lines, and is used to convert analog quantities of pixel signals into digital quantities.

[0096] Specifically, the signal output unit 114 in each pixel block 110 includes a source follower transistor and a selection transistor. Among the multiple selection transistors in the column direction, two adjacent selection transistors are located in the same readout group. The two selection transistors in the readout group are connected to different column lines, so that the pixel readout rows corresponding to the corresponding two pixel blocks 110 in the readout group are read out simultaneously, so that the bends in the two adjacent metal routing sections in the first direction affect each other to form a feedback capacitor. Furthermore, the corresponding selection transistors in different readout groups are connected to the same or different column lines.

[0097] As an example, the readout group includes a first pixel readout row and a second pixel readout row, the first pixel readout row includes a first filter area and a second filter area arranged alternately, and the second pixel readout row includes a third filter area and a fourth filter area arranged alternately, wherein in the pixel array, adjacent first filter areas, second filter areas, third filter areas, and fourth filter areas constitute a pixel combination. As an optional solution, the second filter area and the third filter area have the same configuration, the pixel combination is arranged in a Bayer-based array, and each filter area is set corresponding to the pixel block 110.

[0098] In practical applications, the first filter area is configured to receive light of the first color, the second filter area is configured to receive light of the second color, the third filter area is configured to receive light of the third color, and the fourth filter area is configured to receive light of the fourth color, wherein the third color and the fourth color are the same color, such as the first color is red (R), the second color is green (G), the third color is green (G), and the fourth color is blue (B). At this time, the pixel combination is arranged in a Bayer array of RGGB. It should be noted that the Bayer-based array refers to an arrangement method that is the same or similar to the Bayer array in terms of structural arrangement, such as four adjacent filter areas constitute a pixel array, but the configuration of the four filter areas can be other color combinations except RGGB.

[0099] In a possible implementation, two pixel readout rows in a readout group are arranged adjacent to each other, and two adjacent pixel blocks 110 in adjacent readout groups in the same column share the same metal wiring; Figure 2 and Figure 3 For example, the nth row in the readout group is used as the first pixel readout row, the n+1th row is used as the second pixel readout row, and in the same column, in the previous readout group adjacent to the readout group, the n-2th row is used as the first pixel readout row, and the n-1th row is used as the second pixel readout row, wherein the pixel blocks 110 corresponding to the pixel readout rows in the n-1th row and the nth row share the same metal wiring, that is, the two pixel readout rows in the readout group are adjacently arranged, and the two adjacent pixel blocks 110 in the adjacent readout groups in the same column share the same metal wiring. In this embodiment, the configuration of each filter area is as follows: Figure 4 As shown, in this way, when the nth row and the (n+1th)th row are read out simultaneously, the RGGB color information can be obtained based on the Bayer array.

[0100] In another possible implementation, two pixel readout rows in a readout group are arranged alternately with two pixel readout rows in an adjacent readout group, and two pixel blocks 110 at corresponding positions in adjacent readout groups in the same column share the same metal routing line; Figure 7 and Figure 8For example, the nth row in the readout group is used as the first pixel readout row, and the n+2th row is used as the second pixel readout row. In the same column, in the next readout group adjacent to the readout group, the n+1th row is used as the first pixel readout row, and the n+3th row is used as the second pixel readout row. The pixel blocks 110 corresponding to the pixel readout rows in the nth row and the n+1th row share the same metal wiring, and the pixel blocks 110 corresponding to the pixel readout rows in the n+2nd row and the n+3rd row share the same metal wiring. That is, the two pixel readout rows in the readout group are alternately arranged with the two pixel readout rows in the adjacent readout group, and the pixel blocks 110 at two corresponding positions in the adjacent readout groups in the same column share the same metal wiring. In this embodiment, the configuration of each filter area is as follows: Figure 9-11 As shown, in this way, when the nth row and the n+2th row are read out simultaneously, the RGGB color information can be obtained based on the Bayer array.

[0101] The above two embodiments show the case where two pixel blocks 110 share the same metal wiring (i.e., the case where two pixel blocks 110 in the same pixel group share a reset transistor). Of course, the case where the metal wiring is not shared is also feasible. Two adjacent pixel blocks 110 in the same column do not share a reset transistor, and each pixel block 110 corresponds to a reset transistor. In this case, taking the case where two adjacent pixel blocks 110 in the same column do not share a selection transistor as an example, each adjacent two rows constitute a readout group, wherein each filter area of ​​each pixel readout row in the readout group is set and configured corresponding to the pixel block 110 as follows: Fig.14 As shown, in this way, when two pixel readout rows in a readout group are read out simultaneously, color information of RGGB can be acquired based on the Bayer array.

[0102] Of course, there is also a situation where one pixel block 110 corresponds to at least two filter areas, such as: Fig.12 It is shown that one pixel block 110 corresponds to two filter areas. Fig.13 It is shown that one pixel block 110 corresponds to four filter areas; at this time, when two pixel readout rows in the readout group are read out simultaneously, by setting some filter areas in the pixel block 110 to be effective, RGGB color information can be obtained based on the Bayer array.

[0103] Moreover, when acquiring color information of RGGB based on the Bayer array, the feedback capacitor of the pixel array of this embodiment can effectively solve the problem of signal mismatch caused by the inconsistent influence of the two G pixels by the R pixels and the B pixels, and can acquire G pixel signals that are consistently influenced by the R pixels and the B pixels based on the Bayer array.

[0104] This embodiment also provides a control method for the image sensor as described above, when the gain control unit 113 is provided with a metal routing extending in a first direction and the metal routing includes at least one bend in a second direction, the control method includes: in a low conversion gain mode, two pixel blocks 110 corresponding to two adjacent metal routing sections in the column direction are read out simultaneously through different column lines, so as to introduce feedback capacitance in the first direction through the bends that are close to each other and influence each other, thereby balancing the parasitic capacitance in the second direction caused by the adjacent pixel blocks in the row direction, and improving the existing crosstalk by introducing feedback. In addition, it should be noted that the low gain here may refer to a low gain mode performed according to the existing operation of the image sensor based on the configuration of the gain control transistor, and does not strictly represent a certain state, and multiple modes may be selected according to the configuration of the gain control transistor.

[0105] by Figure 2 and Figure 3 For example, a gain control transistor corresponding to the corresponding pixel block 110 in the nth row is provided with a metal wiring, and a gain control transistor corresponding to the corresponding pixel block 110 in the n+1th row is provided with another metal wiring, and the two metal wirings are adjacently arranged in the first direction, and each has two bending portions close to each other and affecting each other;

[0106] In the low conversion gain mode, the pixel signals (including reset signals and image signals) of the pixel blocks 110 in the nth row and the n+1th row are read out simultaneously through different column lines; Figure 5 As shown, the specific controls are as follows:

[0107] The gain control transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row are controlled to be turned on, so that the pixel blocks 110 in the nth row and the n+1th row enter the low conversion gain mode; further, the gain control transistors corresponding to the pixel blocks 110 in the n-1th row and the n+2th row are controlled to be turned on, so as to modulate the capacity of the modulation storage area corresponding to the pixel blocks 110 in the nth row and the n+1th row, respectively, and at this time, the conversion gain corresponding to the pixel blocks 110 in the nth row and the n+1th row is the lowest;

[0108] Control the reset transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to turn on, and reset the modulation storage areas corresponding to the pixel blocks 110 in the nth row and the n+1th row;

[0109] Control the reset transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned off, and control the selection transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned on, and read out the reset signals corresponding to the pixel blocks 110 in the nth row and the n+1th row at the same time, and then control the selection transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned off;

[0110] Control the transfer transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned on for charge transfer, and then control the transfer transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned off;

[0111] The selection transistors corresponding to the pixel blocks 110 in the nth and n+1th rows are controlled to be turned on, and the image signals corresponding to the pixel blocks 110 in the nth and n+1th rows are read out at the same time, and then the selection transistors corresponding to the pixel blocks 110 in the nth and n+1th rows are controlled to be turned off.

[0112] Of course, the selection transistors corresponding to the pixel blocks 110 in the nth row and the (n+1th)th row may also be controlled to be always in the on state, which has no effect on signal readout.

[0113] Further, in the high conversion gain mode, each pixel block 110 in the column direction is read out row by row, or two pixel blocks 110 corresponding to two adjacent metal traces in the column direction are read out simultaneously through different column lines to improve the readout speed. The method of selecting simultaneous readout in the high gain mode can refer to the design of selecting the same readout group in the low gain mode.

[0114] For example, two pixel blocks 110 corresponding to two adjacent metal lines in the column are read out simultaneously through different column lines. Figure 6 As shown, the specific controls are as follows:

[0115] Control the reset transistors and gain control transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to turn on, and reset the floating diffusion active areas corresponding to the pixel blocks 110 in the nth row and the n+1th row;

[0116] Controlling the gain control transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned off, so that the pixel blocks 110 in the nth row and the n+1th row enter a high conversion gain mode;

[0117] Control the reset transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned off, and control the selection transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned on, and read out the reset signals corresponding to the pixel blocks 110 in the nth row and the n+1th row at the same time, and then control the selection transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned off;

[0118] Control the transfer transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned on for charge transfer, and then control the transfer transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row to be turned off;

[0119] The selection transistors corresponding to the pixel blocks 110 in the nth and n+1th rows are controlled to be turned on, and the image signals corresponding to the pixel blocks 110 in the nth and n+1th rows are read out at the same time, and then the selection transistors corresponding to the pixel blocks 110 in the nth and n+1th rows are controlled to be turned off.

[0120] Of course, the selection transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row may also be controlled to be always in the on state, which has no effect on the signal readout. In addition, before the selection transistors corresponding to the pixel blocks 110 in the nth row and the n+1th row are controlled to be turned on to read out the reset signal, the gain control transistors corresponding to the pixel blocks 110 in the n-1th row and the n+2th row are also controlled to be turned on and then turned off. It should be noted that the high gain here may refer to a high gain mode performed according to the configuration of the gain control transistor according to the existing operation of the image sensor. In one application, the high gain may represent a state in which all the gain transistors corresponding to a certain pixel block are turned off, and the low gain mode may be a state in which at least one of the gain transistors corresponding to a certain pixel block is turned on.

[0121] In summary, a pixel array, an image sensor and a control method of the present invention form a feedback capacitor configured in a first direction at a gain control unit, such as using the bending portions of two adjacent metal traces (corresponding to the gain control unit) to be close to each other and to influence each other to form a feedback capacitor, so as to balance the parasitic capacitance in the second direction caused by the adjacent pixel blocks in the row, improve the image color degradation problem caused by crosstalk introduced by the miniaturization of pixel size in the image sensor, and improve the image quality. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0122] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A pixel array, characterized in that: It includes a plurality of pixel blocks arranged in rows and columns, wherein the pixel blocks include a photosensitive unit, a floating diffusion active area, a gain control unit, a reset unit and a signal output unit, wherein: The photosensitive unit is used to receive a light signal and generate a charge signal based on the light signal; The floating diffusion active area is used to receive the charge signal; The gain control unit is coupled to the floating diffusion active area, and the gain control unit cooperates with the floating diffusion active area to form a modulation storage area to form a voltage signal corresponding to the charge signal based on the modulation storage area; The reset unit is coupled to the floating diffusion active region and is at least used to reset the floating diffusion active region; The signal output unit is coupled to the floating diffusion active region and is used to output the voltage signal; A feedback capacitor configured in a first direction is formed at the gain control unit to balance the parasitic capacitance in a second direction caused by the pixel blocks adjacent to each other in the row, and the second direction has an angle with the first direction.

2. The pixel array according to claim 1, characterized in that: The gain control unit includes at least one gain control transistor coupled between the reset unit and the floating diffusion active area; when the gain control unit includes two or more gain control transistors, each gain control transistor is coupled in series between the reset unit and the floating diffusion active area.

3. The pixel array according to claim 1, characterized in that: The gain control unit is provided with a metal routing extending along a first direction, the metal routing includes at least one bending portion along a second direction, and the second direction has an angle with the first direction; wherein, in two adjacent sections of the metal routing in the first direction, each has at least one bending portion that is close to each other and influences each other to form a feedback capacitor.

4. The pixel array according to claim 3, characterized in that: The photosensitive unit includes a photosensitive element and a corresponding transmission transistor, the gain control unit includes a gain control transistor, the reset unit includes a reset transistor, and the signal output unit includes a source follower transistor and a selection transistor, wherein: The transfer transistors in the photosensitive unit are enclosed to form an enclosed area, the source follower transistor is arranged in the enclosed area, the floating diffusion active area is arranged in the enclosed area and is arranged on both sides of the source follower transistor, including a first floating diffusion node and a second floating diffusion node, the gain control transistor is arranged outside the enclosed area and is arranged on one side of the first floating diffusion node or the second floating diffusion node, the reset transistor and the selection transistor are arranged outside the enclosed area and are arranged between adjacent source follower transistors in a column direction; The metal routing wire corresponding to the gain control transistor includes at least one bending portion, and in two adjacent sections of the metal routing wire in the first direction, at least one bending portion each is close to each other and affects each other.

5. The pixel array according to claim 4, characterized in that: In the plurality of pixel blocks arranged in a column, every two adjacent pixel blocks form a pixel group. In the same pixel group, two pixel blocks share the same reset transistor, and two gain control transistors correspond to a section of the metal wiring.

6. The pixel array according to claim 5, characterized in that: In the same pixel group, the reset transistor is located outside the adjacent source follower transistor, and the metal routing includes: a first bending portion, a second bending portion, a third bending portion, a fourth bending portion, a first column routing, a second column routing, and a third column routing; The first bending portion is connected to the first end of the first column-oriented routing and is close to and influences the third bending portion of the previous section of the metal routing. The second bending portion spans the middle end of the first column-oriented routing and the first end of the second column-oriented routing and is close to and influences the fourth bending portion of the previous section of the metal routing. The third bending portion spans the second end of the first column-oriented routing and the middle end of the third column-oriented routing and is close to and influences the first bending portion of the next section of the metal routing. The fourth bending portion is connected to the second end of the third column-oriented routing and is close to and influences the second bending portion of the next section of the metal routing. The second end of the second column-oriented routing and the first end of the third column-oriented routing are free ends. The second column-oriented routing and the third column-oriented routing are respectively coupled to the two gain control transistors of the two pixel blocks in the same pixel group.

7. The pixel array according to claim 5, characterized in that: In the same pixel group, the reset transistor is located between adjacent source follower transistors, and the metal routing includes: a first bending portion, a second bending portion, a third bending portion, a fourth bending portion, a fifth bending portion, a sixth bending portion, a first column routing, a second column routing, and a third column routing; The first bending portion is connected to the first end of the first column-oriented routing and is close to and influences the third bending portion of the previous section of the metal routing. The second bending portion is connected to the first end of the second column-oriented routing and is close to and influences the fourth bending portion of the previous section of the metal routing. The third bending portion is connected to the second end of the first column-oriented routing and is close to and influences the first bending portion of the next section of the metal routing. The fourth bending portion is connected to the second end of the third column-oriented routing and is close to and influences the second bending portion of the next section of the metal routing. The fifth bending portion bridges the middle end of the first column-oriented routing and the middle end of the second column-oriented routing. The sixth bending portion bridges the middle end of the first column-oriented routing and the middle end of the third column-oriented routing. The second end of the second column-oriented routing and the first end of the third column-oriented routing are free ends. The second column-oriented routing and the third column-oriented routing are respectively coupled to the two gain control transistors of the two pixel blocks in the same pixel group.

8. The pixel array according to any one of claims 5 to 7, characterized in that: In the same pixel group, two pixel blocks share the same selection transistor; or, in different pixel groups, two adjacent pixel blocks share the same selection transistor.

9. The pixel array according to claim 4, characterized in that: The photosensitive unit includes four photosensitive elements and corresponding four transmission transistors, the four photosensitive elements are arranged in an array, the four transmission transistors are in a strip shape, and are arranged at an inclined angle at the corners of the four photosensitive elements facing each other to form the enclosed area; The first floating diffusion node and the second floating diffusion node are respectively arranged in the regions facing each other of the two transfer transistors arranged in a column direction, and the source follower transistor is arranged on the center connection line between the first floating diffusion node and the second floating diffusion node.

10. The pixel array according to claim 3, characterized in that: The photosensitive unit includes a photosensitive element and a corresponding transmission transistor, the gain control unit includes a gain control transistor, the reset unit includes a reset transistor, and the signal output unit includes a source follower transistor and a selection transistor, wherein: The transfer transistors in the photosensitive unit are enclosed to form an enclosed area, the source follower transistor is arranged in the enclosed area, the floating diffusion active area is arranged in the enclosed area and on one side of the source follower transistor, the gain control transistor is arranged outside the enclosed area and on one side of the floating diffusion active area, the reset transistor is arranged on a side of the gain control transistor away from the floating diffusion active area, and the selection transistor is arranged outside the enclosed area and above or below the source follower transistor; The metal routing wire corresponding to the gain control transistor includes at least one bending portion, and in two adjacent sections of the metal routing wire in the first direction, at least one bending portion each is close to each other and affects each other.

11. The pixel array according to claim 10, characterized in that: The metal routing is arranged in an interconnection structure; and / or the photosensitive unit includes two photosensitive elements and corresponding two transmission transistors, the two photosensitive elements share the floating diffusion active area, the signal output unit and the gain control unit, or the photosensitive unit includes one photosensitive element, or the photosensitive unit includes four photosensitive elements and corresponding four transmission transistors, the four photosensitive elements share the floating diffusion active area, the signal output unit and the gain control unit.

12. An image sensor, characterized in that: Comprising a pixel array as described in any one of claims 1-11.

13. The image sensor according to claim 12, characterized in that: The signal output unit in each pixel block includes a source follower transistor and a selection transistor. Among the multiple selection transistors in the column, two adjacent selection transistors are located in the same readout group, and the two selection transistors in the readout group are connected to different column lines.

14. The image sensor according to claim 13, characterized in that: The corresponding selection transistors in different readout groups are connected to the same or different column lines.

15. The image sensor according to claim 13, characterized in that: The readout group includes a first pixel readout row and a second pixel readout row, the first pixel readout row includes a first filter area and a second filter area arranged alternately, the second pixel readout row includes a third filter area and a fourth filter area arranged alternately, and the adjacent first filter area, the second filter area, the third filter area and the fourth filter area constitute a pixel combination.

16. The image sensor according to claim 15, characterized in that The configurations corresponding to the second filter area and the third filter area are the same, the pixel groups are arranged in a Bayer-based array, and each filter area is set corresponding to the pixel block; wherein, two pixel readout rows in the readout group are arranged adjacent to each other, and two adjacent pixel blocks in adjacent readout groups in the same column share the same metal routing; or, two pixel readout rows in the readout group are arranged alternately with two pixel readout rows in adjacent readout groups, and the pixel blocks in two corresponding positions in adjacent readout groups in the same column share the same metal routing.

17. A method for controlling an image sensor according to any one of claims 12 to 16, characterized in that: When the gain control unit is provided with the metal wiring extending along the first direction and the metal wiring includes at least one bending portion along the second direction, the method comprises: In the low conversion gain mode, the two pixel blocks corresponding to the two adjacent sections of the metal wiring in the column are read out simultaneously through different column lines, so as to introduce feedback capacitance through the bending parts that are close to each other and affect each other.

18. The control method according to claim 17, characterized in that: In the high conversion gain mode, the pixel blocks in the column direction are read out row by row, or the two pixel blocks corresponding to two adjacent sections of the metal wiring in the column direction are read out simultaneously through different column lines.

Images