Output buffer circuit with metal selections

Abstract

The invention relates to an output buffer circuit with a metal option. Disclosed herein is an apparatus including first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of the source / drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and the other of the source / drain regions of the first transistor, and the fifth wiring pattern is connected to one of the source / drain regions of the second transistor. The first wiring pattern is connected to one of the source / drain regions of the first transistor, the fifth wiring pattern overlaps the first wiring pattern, and the sixth wiring pattern is connected to the other of the source / drain regions of the second transistor, the sixth wiring pattern overlaps the second wiring pattern. Widths of the third and fourth wiring patterns in the first direction are greater than those of the fifth and sixth wiring patterns.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of February 23, 2021, an invention name of “Output buffer circuit with metal option”, and an application number of 202110201918.2. Technical Field

[0003] The present application relates to an output buffer circuit with a metal option. Background Art

[0004] In a semiconductor device such as a DRAM, a large current flows through a transistor constituting an output buffer. Therefore, when the semiconductor device is used for a long time, it may cause the shape of a wiring pattern connected to the output buffer to change due to a migration phenomenon. In particular, when the cross-sectional area of ​​the wiring pattern becomes smaller due to miniaturization, the density of the current flowing through the wiring pattern becomes high, so there is a risk of disconnection caused by the migration phenomenon. Summary of the invention

[0005] One embodiment of the present disclosure provides a device, comprising: first and second wiring patterns extending in a first direction in a first wiring layer; a plurality of transistors arranged along the first direction between the first and second wiring patterns, the plurality of transistors including first and second transistors arranged adjacent to each other; and third, fourth, fifth and sixth wiring patterns extending in a second direction intersecting the first direction in a second wiring layer, wherein the third wiring pattern is electrically connected between the first wiring pattern and one of the source / drain regions of the first transistor, wherein the fourth wiring pattern is electrically connected between the second wiring pattern and the other of the source / drain regions of the first transistor, wherein the fifth wiring pattern is electrically connected to one of the source / drain regions of the second transistor, the fifth wiring pattern overlaps with the first wiring pattern, wherein the sixth wiring pattern is electrically connected to the other of the source / drain regions of the second transistor, the sixth wiring pattern overlaps with the second wiring pattern, and wherein the widths of the third and fourth wiring patterns in the first direction are greater than those of the fifth and sixth wiring patterns.

[0006] Another embodiment of the present disclosure provides a device, which includes: first, second and third transistors, which are arranged in a first direction so that the second transistor is arranged between the first and third transistors; a power supply pattern extending in the first direction; first, second, third, fourth, fifth and sixth wiring patterns extending in a second direction intersecting the first direction, wherein the first, third and fifth wiring patterns are respectively electrically connected to one of the source / drain regions of the first, second and third transistors, wherein the second, fourth and sixth wiring patterns are respectively electrically connected between the power supply pattern and the other of the source / drain regions of the first, second and third transistors, wherein the second and third wiring patterns are arranged adjacent to each other with a first space, wherein the fourth and fifth wiring patterns are arranged adjacent to each other with a second space, wherein the other of the source / drain regions of the first transistor and one of the source / drain regions of the second transistor are arranged adjacent to each other with a third space, wherein the other of the source / drain regions of the second transistor and one of the source / drain regions of the third transistor are arranged adjacent to each other with a fourth space, wherein the first space is narrower than the second space, and wherein the fourth space is narrower than the third space.

[0007] Yet another embodiment of the present disclosure provides a device, comprising: first, second and third transistors, which are arranged in a first direction so that the second transistor is arranged between the first and third transistors; a power supply pattern extending in the first direction; first, second, third, fourth, fifth and sixth wiring patterns extending in a second direction intersecting the first direction, wherein the first, third and fifth wiring patterns are electrically connected to one of the source / drain regions of the first, second and third transistors, respectively, wherein the second, fourth and sixth wiring patterns are electrically connected between the power supply pattern and the other of the source / drain regions of the first, second and third transistors, respectively, wherein the second and third wiring patterns are arranged adjacent to each other with a first space, wherein the fourth and fifth wiring patterns are arranged adjacent to each other with a second space, wherein the other of the source / drain regions of the first transistor and one of the source / drain regions of the second transistor are arranged adjacent to each other with a third space, wherein the other of the source / drain regions of the second transistor and one of the source / drain regions of the third transistor are arranged adjacent to each other with a fourth space, wherein the first space is narrower than the third space, and wherein the fourth space is narrower than the second space. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram showing a configuration of a semiconductor device according to the present disclosure.

[0009] Figure 2is a block diagram showing a circuit of a data output system included in an I / O circuit.

[0010] Figure 3 is the circuit diagram of the unit driver.

[0011] Figure 4 is a circuit diagram of a circuit that generates an enable signal.

[0012] Figure 5 is a schematic plan view showing the layout of the main drive.

[0013] Figures 6A to 6C is a circuit diagram showing several configurations of the main drive switched by metal options.

[0014] Figures 7A to 7C is a layout diagram showing several configurations of main drives switched by metal options. DETAILED DESCRIPTION

[0015] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of the present invention that can be practiced by means of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized without departing from the scope of the present invention, and structural, logical and electrical changes may be made. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0016] Figure 1 The semiconductor device 10 shown is, for example, a DRAM, and includes a memory cell array 11, an access control circuit 12 that accesses the memory cell array 11, and an I / O circuit 13 that inputs and outputs data to and from the memory cell array 11. The access control circuit 12 accesses the memory cell array 11 based on a command address signal CA input from an external controller via a command address terminal 14. In a read operation, data DQ read out from the memory cell array 11 is output to an external data I / O terminal 15 via the I / O circuit 13. In a write operation, data DQ input to the external data I / O terminal 15 from an external controller is provided to the memory cell array 11 via the I / O circuit 13.

[0017] Figure 2 1 shows a circuit block as a circuit of a data output system included in the I / O circuit 13, and the data output system corresponds to one external data I / O terminal 15. Figure 2As shown, the I / O circuit 13 includes a pull-up circuit 21, a pull-down circuit 22, and pre-emphasis circuits 23 and 24. The pull-up circuit 21 is activated in the pull-up operation, that is, when the high-level read data DQ is output from the external data I / O terminal 15. The pull-down circuit 22 is activated in the pull-down operation, that is, when the low-level read data DQ is output from the external data I / O terminal 15. Each of the pre-emphasis circuits 23 and 24 temporarily reduces its output resistance only during data conversion in order to compensate for the skin resistance loss and dielectric loss generated in high-frequency operation. Therefore, also in high-frequency operation, data conversion can be allowed to be performed at an appropriate conversion rate, and the external data I / O terminal 15 is driven with a set resistance in a stable state.

[0018] The pull-up data DATAu is supplied to the pull-up circuit 21 and the pre-emphasis circuit 23. The pull-down data DATAd is supplied to the pull-down circuit 22 and the pre-emphasis circuit 24. The calibration code signal ZQ and the driver strength selection signal DS are supplied to the pull-up circuit 21 and the pull-down circuit 22. The pull-up circuit 21 has a configuration in which a plurality of unit drivers 30 are connected in parallel. The unit drivers 30 have the same circuit configuration as each other, and one or two or more unit drivers 30 are selected based on the driver strength selection signal DS. The pull-down circuit 22 has a configuration in which a plurality of unit drivers 40 are connected in parallel. The unit drivers 40 have the same circuit configuration as each other, and one or two or more unit drivers 40 are selected based on the driver strength selection signal DS.

[0019] like Figure 3 As shown, each unit driver 30 includes a main driver 31 and a sub-driver 32. The main driver 31 includes four N-channel MOS transistors 311 to 314 connected in parallel. The sources of the transistors 311 to 314 are connected to the external data I / O terminal 15, and the power supply potential VDDQ is supplied to the drains of the transistors 311 to 314. An enable signal En or a ground potential GND is supplied to the gate electrodes of the transistors 311 to 314. Figure 3 In the example shown, the enable signal En is supplied to the gate electrode of the transistor 311, and the ground potential GND is supplied to the gate electrodes of the other transistors 312 to 314. Whether the enable signal En is supplied to the gate electrodes of the transistors 311 to 314 is determined by the metal option at the time of manufacturing. For the transistors 312 to 314 to which the ground potential GND is supplied, their sources can be disconnected from the external data I / O terminal 15 by the metal option. In this case, it is not always necessary to supply the ground potential GND to the gate electrode.

[0020] The enable signal En is always supplied to the gate electrode of the transistor 311, which is one of the transistors 311 to 314 constituting the main driver 31. Figure 3In the example shown, when the ground potential GND is provided to the gate electrodes of other transistors 312 to 314, the transistor activated in the main driver 31 is one. Therefore, the conversion rate of the unit driver 30 becomes the minimum. In the case where the conversion rate needs to be set to be higher, the wiring is switched by metal selection in the manufacturing stage in such a way that the enable signal En is provided to the gate electrodes of the transistors 311 and 312 and the ground potential GND is provided to the gate electrodes of the other transistors 313 and 314, so that the number of transistors activated in the main driver 31 becomes two. In addition, by designing the wiring in such a way that the enable signal En is provided to the gate electrodes of the transistors 311 to 313 and the ground potential GND is provided to the gate electrode of another transistor 314, the number of transistors activated in the main driver 31 becomes three, and the conversion rate becomes higher. By designing the wiring in such a way that the enable signal En is provided to the gate electrodes of all transistors 311 to 314, the number of transistors activated in the main driver 31 becomes four, and the conversion rate becomes the maximum. The sizes of the transistors 311 to 314 can be the same as each other.

[0021] The sub-driver 32 includes seven transistors 321 to 327. The sources of the transistors 321 to 327 are connected to the external data I / O terminal 15, and the power supply potential VDDQ is provided to the drains of the transistors 321 to 327. The enable signal En1 is provided to the gate electrode of the transistor 321, the enable signal En2 is generally provided to the gate electrodes of the transistors 322 and 323, and the enable signal En3 is generally provided to the gate electrodes of the transistors 324 to 327. The sizes of the transistors 321 to 327 can be the same as each other. Therefore, the impedance of the unit driver 30 can be adjusted to eight levels by using the sub-driver 32.

[0022] It is also possible to generate enable signals En and En1 to En3 based on the pull-up data DATAu and the calibration code signal ZQ. Figure 4 In the example shown, the enable signal En is generated by buffering the pull-up data DATAu using the buffer circuit 50. Furthermore, the enable signals En1 to En3 are generated by logical synthesis of the bit signals ZQ1 to ZQ3 which constitute the calibration code signal ZQ and the pull-up data DATAu through the AND circuits 51 to 53, respectively.

[0023] Figure 5 3 is a schematic plan view showing the layout of the main driver 31. The transistors 311 to 314 constituting the main driver 31 are arranged between the wiring patterns 61 and 62 extending in the X direction in the plan view. The wiring pattern 61 is connected to the external data I / O terminal 15, and the read data DQ appears thereon. The power supply potential VDDQ is supplied to the wiring pattern 62. Figure 5As shown, transistors 311, 314, 313, and 312 are arranged in this order in the X direction. Figure 5 On the left side of the leftmost transistor 311, a diffusion region SC1 for providing a fixed potential to the semiconductor substrate is arranged. Figure 5 On the right side of the rightmost transistor 312, a diffusion region SC2 for providing a fixed potential to the semiconductor substrate is arranged.

[0024] The transistor 311 is composed of a source region 311S, a drain region 311D, and a gate electrode 311G. The source region 311S is connected to the wiring pattern 71 via the contact electrode 81, and the drain region 311D is connected to the wiring pattern 72 via the contact electrode 82. The transistor 314 is composed of a source region 314S, a drain region 314D, and a gate electrode 314G. The source region 314S is connected to the wiring pattern 73 via the contact electrode 83, and the drain region 314D is connected to the wiring pattern 74 via the contact electrode 84. The transistor 313 is composed of a source region 313S, a drain region 313D, and a gate electrode 313G. The source region 313S is connected to the wiring pattern 75 via the contact electrode 85, and the drain region 313D is connected to the wiring pattern 76 via the contact electrode 86. The transistor 312 is composed of a source region 312S, a drain region 312D, and a gate electrode 312G. The source region 312S is connected to the wiring pattern 77 via the contact electrode 87, and the drain region 312D is connected to the wiring pattern 78 via the contact electrode 88. Figure 5 In the example shown, the source regions 311S to 314S are located on the left side, and the drain regions 311D to 314D are located on the right side; however, the positional relationship therebetween may be reversed.

[0025] The wiring patterns 71 to 78 are wirings provided in a second wiring layer located below the first wiring layer in which the wiring patterns 61 and 62 are provided, and all the wiring patterns extend in the Y direction. Tungsten can be used as the material of the wiring patterns 71 to 78, and aluminum or copper having a lower resistance than tungsten can be used as the material of the wiring patterns 61 and 62. Here, when it is assumed that the X-direction width of each of the wiring patterns 71 and 72 is W1, the X-direction width of each of the wiring patterns 73 and 74 is W4, the X-direction width of each of the wiring patterns 75 and 76 is W3, and the X-direction width of each of the wiring patterns 77 and 78 is W2, these widths satisfy the relationship of W1>W2>W3>W4.

[0026] like Figure 5As shown, wiring patterns 71, 73, 75 and 77 overlap with wiring pattern 61, and wiring patterns 72, 74, 76 and 78 overlap with wiring pattern 62. Wiring patterns 72, 74, 76 and 78 are connected to wiring pattern 62 via contact electrodes 92, 94, 96 and 98, respectively. With this configuration, power supply potential VDDQ is supplied to all drain regions 311D to 314D of transistors 311 to 314. At the same time, Figure 5 In the example shown, although the wiring pattern 71 and the wiring pattern 61 are connected to each other via the contact electrode 91, no contact electrode is provided between each of the wiring patterns 73, 75 and 77 and the wiring pattern 61, so that the wiring patterns 73, 75 and 77 and the wiring pattern 61 are electrically isolated from each other. This means that the contact electrode connecting each of the wiring patterns 73, 75 and 77 and the wiring pattern 61 to each other is omitted due to the metal selection. Therefore, Figure 5 The main driver 31 shown is used as Figure 3 That is, only the transistor 311 is enabled, while the other transistors 312 to 314 are disabled.

[0027] In the case where only the transistor 311 is enabled and the other transistors 312 to 314 are disabled, in this way, whenever the high-level read data DQ is output, the transistor 311 is turned on, and thus a large current flows through the wiring patterns 71 and 72. Therefore, when the cross-sectional area of ​​each of the wiring patterns 71 and 72 is small, the wiring patterns 71 and 72 may be deformed due to the migration phenomenon, and this may cause disconnection. However, in the present embodiment, the wiring width W1 of the wiring patterns 71 and 72 is set to be wider than the wiring width of the other wiring patterns 73 to 78, and thus a sufficient cross-sectional area is ensured, so that the occurrence of the migration phenomenon can be prevented.

[0028] like Fig. 6A As shown, when the transistors 311 and 312 are enabled and the other transistors 313 and 314 are disabled by metal selection, the enable signal En is supplied to the gate electrodes of the transistors 311 and 312. In order to implement such supply, the wiring pattern 77 and the wiring pattern 61 are connected to each other via the contact electrode 97, as shown in FIG. Fig. 7AAs shown. In this case, when the enable signal En is activated, the two transistors 311 and 312 connected in parallel are turned on. Since the value of the current flowing through the main driver 31 is kept substantially constant by the external circuit connected to the external data I / O terminal 15, the value of the current flowing through each of the transistors 311 and 312 is 1 / 2 of the current flowing when only the transistor 311 is turned on. In this way, because the maximum value of the current flowing through the transistor 312 is smaller than the maximum value of the current flowing through the transistor 311, the wiring width W2 of each of the wiring patterns 77 and 78 is designed to be smaller than the wiring width W1 of each of the wiring patterns 71 and 72, so that the occupied area is reduced.

[0029] like Figure 6B As shown, when the transistors 311 to 313 are enabled by the metal option and the other transistors 314 are disabled, the enable signal En is supplied to the gate electrodes of the transistors 311 to 313. In order to implement this supply, the wiring pattern 75 and the wiring pattern 61 are connected to each other via the contact electrode 95, as shown in FIG. Figure 7B As shown. In this case, when the enable signal En is activated, the three transistors 311 to 313 connected in parallel are turned on. As described above, since the value of the current flowing through the main driver 31 is substantially constant, the value of the current flowing through each of the transistors 311 to 313 is 1 / 3 of the current flowing when only the transistor 311 is turned on. In this way, since the maximum value of the current flowing through the transistor 313 is smaller than the maximum value of the current flowing through the transistor 312, the wiring width W3 of each of the wiring patterns 75 and 76 is designed to be smaller than the wiring width W2 of each of the wiring patterns 77 and 78, so that the occupied area is reduced.

[0030] like Figure 6C As shown, when all transistors 311 to 314 are enabled by metal selection, the enable signal En is supplied to the gate electrodes of the transistors 311 to 314. In order to implement this supply, the wiring pattern 73 and the wiring pattern 61 are connected to each other via the contact electrode 93, as shown in FIG. Figure 7C As shown. In this case, when the enable signal En is activated, the four transistors 311 to 314 connected in parallel are turned on. As described above, since the value of the current flowing through the main driver 31 is substantially constant, the value of the current flowing through each of the transistors 311 to 314 is 1 / 4 of the current flowing when only the transistor 311 is turned on. In this way, since the maximum value of the current flowing through the transistor 314 is smaller than the maximum value of the current flowing through the transistor 313, the wiring width W4 of each of the wiring patterns 73 and 74 is designed to be smaller than the wiring width W3 of each of the wiring patterns 75 and 76, so that the occupied area is reduced.

[0031] Here, when it is assumed that the space between the wiring patterns 72 and 73 in the X direction is S1, the space between the wiring patterns 74 and 75 in the X direction is S2, and the space between the wiring patterns 76 and 77 in the X direction is S6, these spaces satisfy the relationship of S2>S6>S1. In addition, when it is assumed that the space between the drain region 311D and the source region 314S in the X direction is S3, the space between the drain region 314D and the source region 313S in the X direction is S4, and the space between the drain region 313D and the source region 312S in the X direction is S7, these spaces satisfy the relationship of S3>S7>S4.

[0032] like Figure 5 As shown, the wiring pattern 72 has a wiring width W1 as the widest width and protrudes beyond the drain region 311D in the X direction in a plan view. Therefore, the distance between the transistors 311 and 314 is limited by the minimum space (S1) required between the wiring patterns 72 and 73. As a result, the space S3 between the drain region 311D and the source region 314S is wider than the minimum space (S4) required between the drain region 311D and the source region 314S. Figure 5 In the example shown, the relationship S3>S1 is satisfied.

[0033] Meanwhile, the wiring pattern 74 has a wiring width W4 as the narrowest width, and does not protrude beyond the drain region 314D in the X direction in a plan view. This is also the same for the wiring pattern 75, and the wiring pattern 75 does not protrude beyond the source region 313S in the X direction in a plan view. Therefore, the distance between the transistors 314 and 313 is limited by the minimum space (S4) required between the drain region 314D and the source region 313S, and as a result, the space S2 between the wiring patterns 74 and 75 is wider than the minimum space (S1) required between the wiring patterns 74 and 75. Figure 5 In the example shown, the relationship S2>S4 is satisfied.

[0034] The wiring pattern 77 has a wiring width W2 as the second widest width and protrudes beyond the source region 312S in the X direction in a plan view. Therefore, the distance between the transistors 313 and 312 is limited by the minimum space (S1=S6) required between the wiring patterns 76 and 77. As a result, the space S7 between the drain region 313D and the source region 312S is wider than the minimum space (S4) required between the drain region 313D and the source region 312S. Figure 5 In the example shown, the relationship of S7 > S6 is satisfied. However, since the amount of protrusion in the X direction of the wiring pattern 77 is smaller than the amount of protrusion of the wiring pattern 72, the relationship of S3 > S7 is satisfied.

[0035] The source region 311S of the leftmost transistor 311 must be separated from the diffusion region SC1 by a predetermined distance or more. Similarly, the drain region 312D of the rightmost transistor 312 must be separated from the diffusion region SC2 by a predetermined distance or more. Here, generally, the minimum space S5 required between the source region 311S and the diffusion region SC1 and the minimum space S8 required between the drain region 312D and the diffusion region SC2 are wider than the minimum space (S4) required for the diffusion regions between the transistors 311 to 314. Therefore, even in the case where the wiring patterns 101 and 102 extending in the Y direction are provided at positions overlapping with the diffusion regions SC1 and SC2, respectively, sufficient space between the wiring patterns 71 and 101 and sufficient space between the wiring patterns 78 and 102 are ensured. By using this, the transistor 311 allocated with the wiring patterns 71 and 72 having the widest wiring width W1 is arranged close to the diffusion area SC1, and the transistor 312 allocated with the wiring patterns 77 and 78 having the second widest wiring width W2 is arranged close to the diffusion area SC2, so that the occupied area is reduced.

[0036] As described above, while suppressing the migration phenomenon, by arranging the transistor 311 to which the wiring patterns 71 and 72 having the widest wiring width W1 are assigned and the transistor 312 to which the wiring patterns 77 and 78 having the second widest wiring width W2 are assigned at both ends in the X direction, and arranging the transistor 314 to which the wiring patterns 73 and 74 having the narrowest wiring width W4 are assigned to be adjacent to the transistor 311, it is possible to minimize the increase in the occupied area.

[0037] Although the above description focuses on the cell driver 30 included in the pull-up circuit 21 , also regarding the cell driver 30 included in the pull-down circuit 22 , by applying the same layout as the cell driver 30 , an increase in occupied area can be minimized while suppressing the migration phenomenon.

[0038] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be appreciated by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the present invention and its obvious modifications and use of equivalents. In addition, based on this disclosure, other modifications within the scope of the present invention will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed, and still be within the scope of the present invention. It should be understood that the various features and aspects of the disclosed embodiments may be combined or replaced with one another to form a variation pattern of the disclosed invention. Therefore, it is desirable that the scope of at least some of the present invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A device comprising: a main driver comprising a plurality of transistors including a first transistor and a second transistor connected in parallel; and wherein the first transistor includes a first wiring pattern and a second wiring pattern, and the second transistor includes a third wiring pattern and a fourth wiring pattern, The first wiring pattern and the second wiring pattern of the first transistor have widths in the first direction greater than the third wiring pattern and the fourth wiring pattern of the second transistor.

2. The device according to claim 1, further comprising an external data terminal, wherein sources of the plurality of transistors are connected to the external data terminal, wherein drains of the plurality of transistors are connected to a power supply potential, wherein gate electrodes of the plurality of transistors are configured to be connected to a ground potential or a first enable signal based on wiring of corresponding metal options, and The first enable signal is provided to the first transistor among the plurality of transistors, and the ground potential is provided to the second transistor among the plurality of transistors.

3. The device according to claim 2, wherein sources of the second plurality of transistors are connected to the external data terminal, and wherein drains of the second plurality of transistors are connected to the power supply potential, wherein a second enable signal is provided to a first gate electrode of a first transistor of the second plurality of transistors, wherein a third enable signal is provided to second gate electrodes and third gate electrodes of second and third transistors of the second plurality of transistors, and Wherein a fourth enable signal is provided to remaining gate electrodes of remaining transistors in the second plurality of transistors. 4 . The apparatus of claim 3 , wherein the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal are generated based on a pull-up data signal and a calibration code signal.

5. The apparatus according to claim 4, wherein the first enable signal is generated by buffering the pull-up data signal using a buffer circuit, and wherein the second enable signal, the third enable signal and the fourth enable signal are generated by logically synthesizing corresponding bit signals of the calibration code signal and the pull-up data signal by corresponding gate circuits.

6. The apparatus of claim 2, further comprising: a third wiring pattern coupled to the external data terminal; and a fourth wiring pattern coupled to the power supply potential, wherein the plurality of transistors are arranged between the third wiring pattern and the fourth wiring pattern in the first direction, wherein the first transistor is arranged on a first end between the third wiring pattern and the fourth wiring pattern along the first direction, and The second transistor is arranged along the first direction at a second end between the third wiring pattern and the fourth wiring pattern, which is opposite to the first end.

7. The apparatus of claim 2, further comprising: a first diffusion region adjacent to the first transistor at the first end away from the second transistor; a second diffusion region adjacent to the second transistor at the second end away from the first transistor; a fifth wiring pattern overlapping the first diffusion region; and a sixth wiring pattern overlapping the second diffusion region, wherein the first diffusion region and the second diffusion region extend in a second direction opposite to the first direction, and The fifth wiring pattern overlaps with the first diffusion region, and the sixth wiring pattern overlaps with the second diffusion region. 8 . The apparatus according to claim 6 , wherein the first wiring pattern and the second wiring pattern include a first material, and the third wiring pattern and the fourth wiring pattern include a second material having a lower resistance than the first material.

9. The apparatus of claim 1, further comprising a subunit of a second plurality of transistors coupled to the main driver, wherein each of the second plurality of transistors has a same size.

10. A method comprising: activating the first transistor among a plurality of transistors connected in parallel in response to an enable signal provided to a first gate electrode of the first transistor; and outputting a ground potential to remaining gate electrodes of other transistors among the plurality of transistors, in The first transistor includes a first wiring pattern and a second wiring pattern, and the second transistor includes a third wiring pattern and a fourth wiring pattern, The first wiring pattern and the second wiring pattern have widths greater than the third wiring pattern and the fourth wiring pattern.

11. The method according to claim 10, further comprising: outputting the read data to a fifth wiring pattern; A power supply potential is supplied to drain regions of the plurality of transistors via a sixth wiring pattern, wherein the first wiring pattern, the second wiring pattern, the third wiring pattern, and the fourth wiring pattern intersect the fifth wiring pattern and the sixth wiring pattern.

12. The method according to claim 10, wherein A first source of the first transistor is connected to the first wiring pattern, and a first drain of the first transistor is connected to the second wiring pattern.

13. The method according to claim 10, further comprising: activating a second transistor of the plurality of transistors connected in parallel in response to the enable signal provided to a second gate electrode of the second transistor, wherein the second gate electrode is connected to a data terminal through a metal connection; and The ground potential is output to remaining gate electrodes of remaining transistors of the plurality of transistors except for the activated first transistor and the activated second transistor.

14. The method according to claim 10, further comprising: Buffer pull-up data signal; and The enable signal is generated based on the pull-up data signal.

15. An apparatus comprising: A first transistor, a second transistor and a third transistor, which are arranged along a first direction, the second transistor is arranged between the first transistor and the third transistor, and the first transistor, the second transistor and the third transistor are connected in parallel; a first wiring pattern, a second wiring pattern, a third wiring pattern, a fourth wiring pattern, a fifth wiring pattern, and a sixth wiring pattern extending in a second direction different from the first direction, wherein the first transistor includes the first wiring pattern and the second wiring pattern, wherein the second transistor includes the third wiring pattern and the fourth wiring pattern, wherein the third transistor includes the fifth wiring pattern and the sixth wiring pattern, wherein the widths of the first wiring pattern and the second wiring pattern are greater than the widths of the third wiring pattern and the fourth wiring pattern, and The fifth wiring pattern and the sixth wiring pattern have widths greater than the third wiring pattern and the fourth wiring pattern.

16. The apparatus of claim 15, further comprising: A power supply wiring pattern extends in the first direction.

17. The device of claim 16, wherein the first wiring pattern, the third wiring pattern, and the fifth wiring pattern are respectively connected to one of the source / drain regions of the first transistor, the second transistor, and the third transistor, and wherein the second wiring pattern, the fourth wiring pattern, and the sixth wiring pattern are respectively connected between the power supply wiring pattern and the other of the source / drain regions of the first transistor, the second transistor, and the third transistor.

18. The device according to claim 17, wherein the other source / drain region of the first transistor and the one source / drain region of the second transistor are arranged adjacent to each other in a first space, and wherein the other source / drain region of the second transistor and the one source / drain region of the third transistor are arranged adjacent to each other in a second space. The apparatus of claim 18 , wherein the second space is narrower than the first space.

20. The device according to claim 15, wherein the second wiring pattern and the third wiring pattern are arranged adjacent to each other with a third space, wherein the fourth wiring pattern and the fifth wiring pattern are arranged adjacent to each other with a fourth space, and The third space is narrower than the fourth space.

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