Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The method for manufacturing the semiconductor structure comprises the steps that a plurality of virtual channel structures penetrating through a first laminated structure are formed, the virtual channel structures are arranged in the first direction, and the first direction is perpendicular to the stacking direction of the first laminated structure; and forming a gate gap structure penetrating through a part of the virtual channel structure, wherein the gate gap structure extends along the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the storage density requirements for semiconductor structures such as three-dimensional semiconductor memory devices are becoming higher and higher. However, as the number of stacked layers in the semiconductor structure increases, the suspended dielectric layer is easily bent during the gate replacement process. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The method includes: forming a plurality of virtual channel structures penetrating a first stacked structure, wherein the plurality of virtual channel structures are arranged along a first direction, and the first direction is perpendicular to the stacking direction of the first stacked structure; and forming a gate gap structure penetrating a portion of the virtual channel structure, wherein the gate gap structure extends along the first direction.

[0005] In one embodiment, the virtual channel structure includes a first supporting portion and a second supporting portion adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and a gate gap structure is formed that penetrates a portion of the virtual channel structure, including: forming a gate gap structure that penetrates the first supporting portion, wherein the second supporting portion is in contact with the gate gap structure.

[0006] In one embodiment, the virtual channel structure includes a first supporting portion, a second supporting portion, and a third supporting portion adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and a gate gap structure is formed that penetrates a portion of the virtual channel structure, including: forming a gate gap structure that penetrates the second supporting portion, wherein the first supporting portion and the third supporting portion are respectively in contact with two sides of the gate gap structure.

[0007] In one embodiment, the multiple virtual channel structures include a first virtual channel structure and a second virtual channel structure adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and the gate gap structure passes through a portion of at least one of the first virtual channel structure and the second virtual channel structure.

[0008] In one embodiment, the first virtual channel structure includes a first supporting portion and a second supporting portion adjacently distributed along a second direction, and the second virtual channel structure includes a third supporting portion and a fourth supporting portion adjacently distributed along the second direction, wherein the second supporting portion and the third supporting portion are adjacent to each other, forming a gate gap structure that passes through a portion of the virtual channel structure, including: forming a gate gap structure that passes through the second supporting portion and the third supporting portion, wherein the first supporting portion and the fourth supporting portion are respectively in contact with two sides of the gate gap structure.

[0009] In one embodiment, the method includes: forming a plurality of virtual channel structures penetrating a first stacked structure and a channel structure penetrating a second stacked structure and the first stacked structure, wherein the second stacked structure is located on a surface of the first stacked structure, forming a gate gap structure penetrating a portion of the virtual channel structure, including: forming a gate gap structure penetrating the second stacked structure and penetrating a portion of the virtual channel structure.

[0010] In one embodiment, a plurality of virtual channel structures penetrating a first stacked structure and a channel structure penetrating a second stacked structure and the first stacked structure are formed, including: forming a plurality of virtual channel structures penetrating the first stacked structure and an initial first channel structure; forming a second stacked structure and forming a second channel hole penetrating the second stacked structure, wherein the second channel hole is connected to the initial first channel structure; removing the initial first channel structure via the second channel hole to form a channel hole; and forming a channel structure in the channel hole.

[0011] In one embodiment, a plurality of virtual channel structures and an initial first channel structure are formed through a first stacked structure, including: forming a plurality of virtual channel holes and a first channel hole through the first stacked structure; filling sacrificial materials in the virtual channel holes and the first channel holes to form an initial virtual channel structure and an initial first channel structure, respectively; and replacing the initial virtual channel structure with a virtual channel structure.

[0012] In one embodiment, replacing the initial dummy channel structure with the dummy channel structure includes: removing sacrificial material in the dummy channel hole to form a gap; and forming a filling dielectric layer in the gap.

[0013] In one embodiment, a first stacked structure includes a first dielectric layer and a first sacrificial layer alternately stacked, and a second stacked structure includes a second dielectric layer and a second sacrificial layer alternately stacked, forming a gate gap structure that penetrates the second stacked structure and penetrates a portion of the virtual channel structure, including: forming a gate gap that penetrates the second stacked structure and penetrates a portion of the virtual channel structure; removing the first sacrificial layer and the second sacrificial layer through the gate gap to form a sacrificial gap; forming a gate layer in the sacrificial gap; and forming a gate gap structure in the gate gap.

[0014] In one embodiment, the method further includes: forming a top selection gate structure on a surface of the second stacked structure; forming a top channel structure passing through the top selection gate structure along a stacking direction and extending to the channel structure; and forming an electrical contact structure connected to the top channel structure.

[0015] In one embodiment, the gate gap structure penetrates the top select gate structure, the second stacked structure, and a portion of the dummy channel structure.

[0016] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: a first stacked structure; a plurality of support structures, which penetrate the first stacked structure, wherein the plurality of support structures are arranged along a first direction, and the first direction is perpendicular to the stacking direction of the first stacked structure; and a gate gap structure, which penetrates the first stacked structure and extends along the first direction, wherein the gate gap structure contacts the support structure. In one embodiment, the support structure is located on at least one side of the gate gap structure.

[0017] In one embodiment, the plurality of support structures include a first support structure and a second support structure adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and the first support structure and the second support structure are respectively located on both sides of the gate gap structure.

[0018] In one embodiment, the material of the support structure comprises an oxide.

[0019] In one embodiment, the semiconductor structure also includes: a second stacked structure, located on the surface of the first stacked structure, wherein the gate gap structure penetrates the second stacked structure and the first stacked structure along the stacking direction; and a channel structure, penetrating the first stacked structure and the second stacked structure, and including a blocking layer, a charge capture layer, a tunneling layer and a channel layer from the outside to the inside.

[0020] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0021] In one or more embodiments of the present application, by setting a gate gap structure to pass through a portion of the virtual channel structure, the remaining portion of the virtual channel structure can be made to contact the gate gap structure. When a gate replacement process is performed through the gate gap (the gate gap structure can be formed by filling a dielectric material into the gate gap), the remaining portion of the virtual channel structure can serve as a supporting structure around the gate gap to reduce the bending phenomenon of the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0023] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0024] Figures 2 to 8 is a process step diagram for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0025] Figures 9 to 11 is a schematic diagram of the positional relationship between the virtual channel structure and the gate gap structure according to three implementation modes of the present application;

[0026] Fig.12 is a schematic diagram of a semiconductor structure manufactured according to another exemplary embodiment of the present application;

[0027] Figures 13 to 21 is a process step diagram for manufacturing a semiconductor structure according to another exemplary embodiment of the present application;

[0028] Figure 22 to Figure 24 is a schematic diagram of the positional relationship between the virtual channel structure and the gate gap structure according to three other implementation modes of the present application;

[0029] Fig.25 is a schematic diagram of a semiconductor structure manufactured according to another exemplary embodiment of the present application;

[0030] Fig.26 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application;

[0031] Figure 27 to Figure 29 is a schematic diagram of the positional relationship between the support structure and the gate gap structure according to three other implementation modes of the present application;

[0032] Fig.30 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0033] Fig.31A and Fig.31B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0035] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, and especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first stacked structure discussed in this application may also be referred to as the second stacked structure, and the first virtual channel structure may also be referred to as the second virtual channel structure, and vice versa.

[0036] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0037] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0038] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0039] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0041] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0043] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0044] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0045] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a plurality of dummy channel structures penetrating a first stacked structure, wherein the plurality of dummy channel structures are arranged along a first direction, and the first direction is perpendicular to the stacking direction of the first stacked structure; and S1200, forming a gate gap structure penetrating a portion of the dummy channel structure, wherein the gate gap structure extends along the first direction. Steps S1100 and S1200 will be described in detail below.

[0046] like Figure 5 As shown, a plurality of dummy channel structures 1200 penetrating the first stacked structure 1100 may be formed, wherein the plurality of dummy channel structures 1200 are arranged along a first direction X, and the first direction X is perpendicular to a stacking direction Z of the first stacked structure 1100 .

[0047] Specifically, Figure 2 As shown, the first dielectric layer 1110 and the first sacrificial layer 1120 may be alternately stacked to form the first stacked structure 1100. For example, a virtual channel hole 1210 ( Figure 3 ), and then forming a filling dielectric layer 100 in the dummy channel hole 1200 to form a dummy channel structure 1200 ( Figure 5 ).

[0048] For example, the first stacked structure 1100 may be formed by sequentially stacking the first dielectric layer 1110 and the first sacrificial layer 1120 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It should be understood that the number and thickness of the first dielectric layer 1110 and the first sacrificial layer 1120 are not limited to Figure 2 The number and thickness shown in , without departing from the concept of the present application, those skilled in the art can set any number and thickness of the first dielectric layer 1110 and the first sacrificial layer 1120 as needed. In addition, the materials of the first dielectric layer 1110 and the first sacrificial layer 1120 can be selected from suitable materials known in the art, for example, the material of the first dielectric layer 1110 may include oxides such as silicon oxide, and the material of the first sacrificial layer 1120 may include nitrides such as silicon nitride.

[0049] For example, Figure 2 As shown, a first stacked structure 1100 may be formed on a substrate 1400. The substrate 1400 may be used to support the first stacked structure 1100 thereon, and may be removed in a subsequent process. The material of the substrate 1400 includes at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 1400 may be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon germanium substrate, or may be a multi-layer structure such as a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, a plurality of layers prepared from different materials may be sequentially arranged by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate 1400.

[0050] For example, in the process of forming the dummy channel hole 1210, a plurality of channel holes 1310 ( Figure 3 ), and then the sacrificial material 200 may be filled in the channel hole 1310 to form an initial channel structure 1320 ( Figure 4 After forming the dummy channel structure 1200, the sacrificial material 200 in the channel hole 1310 may be removed, and then the channel structure 1300 may be formed in the channel hole 1310 ( Figure 7 ).

[0051] For example, the dummy channel hole 1210 and the channel hole 1310 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The dummy channel hole 1210 and the channel hole 1310 may have a cylindrical or columnar shape extending along the stacking direction in the first stacked structure 1100. As an option, the dummy channel hole 1210 and the channel hole 1310 may extend into the substrate 1400.

[0052] In the process of forming the dummy channel structure 1200, as shown in FIG. Figure 4 As shown, the sacrificial material 200 may be filled in the virtual channel hole 1210 and the channel hole 1310 to form the initial virtual channel structure 1220 and the initial channel structure 1320, respectively. The sacrificial material 200 may include a material such as carbide, which has a low density to facilitate subsequent removal. Figure 5 As shown, a mask layer 300 may be formed on the surface of the initial channel structure 1320 to cover the initial channel structure 1320. Then, the sacrificial material 200 in the virtual channel hole 1210 may be removed to form a gap (not shown), and a filling dielectric layer 100 may be formed in the gap to form the virtual channel structure 1200. It should be understood that in the process of forming the filling dielectric layer 100, the filling dielectric layer 100 ( Figure 5 ), the filling dielectric layer 100 on the first stacked structure 1100 may be removed by a mechanical grinding process to form Figure 6 The structure shown.

[0053] For example, in forming Figure 6 After the structure shown in FIG. 1 is formed, the sacrificial material 200 in the channel hole 1310 may be removed, and then a channel structure 1300 ( Figure 7 ). Forming the channel structure 1300 may include: forming a functional layer 1370 and a channel layer 1360 in sequence from outside to inside in the channel hole 1310; and forming a channel filling dielectric layer 1380 and a channel plug 1390.

[0054] The functional layer 1370 may include a blocking layer 1330 formed on the inner wall of the channel hole 1310 to block the outflow of charges, a charge capture layer 1340 formed on the surface of the blocking layer 1330 to store charges during the operation of the semiconductor structure, and a tunneling layer 1350 formed on the surface of the charge capture layer 1340.

[0055] In some embodiments, the functional layer 1370 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 1370 may have a structure different from the ONO configuration. The channel layer 1360 may be formed on the surface of the tunneling layer 1350 and can be used to transport the required charges (electrons or holes).

[0056] For example, as an option, according to one embodiment of the present application, a functional layer 1370 may be formed on the inner wall and bottom surface of the channel hole 1310, and a channel layer 1360 may be formed on the surface of the tunneling layer 1350 of the functional layer 1370 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0057] In addition, the channel structure 1300 also includes a channel plug 1390 formed at one end of the channel layer 1360 away from the substrate 1400 (which can be understood as the top of the channel structure 1300). Specifically, after forming the functional layer 1370 and the channel layer 1360, the channel hole 1310 can be filled with a channel filling dielectric layer 1380. The channel filling dielectric layer 1380 can include an oxidized dielectric layer, such as silicon oxide. Further, during the filling process, a plurality of insulating gaps can be formed in the channel filling dielectric layer 1380 by controlling the channel filling process to relieve structural stress. Then, a channel plug 1390 is formed in the portion of the channel filling dielectric layer 1380 located at the top of the channel hole 1310. The material of the channel plug 1390 can be prepared using the same material as the channel layer 1360, such as N-type doped or P-type doped polysilicon. The channel plug 1390 is connected to the channel layer 1360.

[0058] In the exemplary embodiment of the present application, Figure 8 As shown, a gate gap structure 1500 penetrating a portion of the dummy channel structure 1200 may be formed, wherein the gate gap structure 1500 extends along the first direction X. For example, as Figures 9 to 11 Schematic diagrams showing the positional relationship between the dummy channel structure 1200 and the gate gap structure 1500 in three implementation modes are shown.

[0059] In the present application, a plurality of dummy channel structures 1200 may be arranged along the first direction X. Fig. 9 and Fig.10 As shown, the gate gap structure 1500 may penetrate a portion of a row of dummy channel structures 1200 arranged along the first direction X. In addition, a plurality of dummy channel structures 1200 may be adjacently distributed along a second direction Y, wherein the second direction Y may be perpendicular to the first direction X and the stacking direction Z. Fig.11As shown, the gate gap structure 1500 may penetrate a portion of each row of dummy channel structures 1200 in two rows of dummy channel structures 1200 arranged along the first direction X and adjacently distributed along the second direction Y.

[0060] Specifically, in an exemplary embodiment of the present application, Fig. 9 As shown, the maximum cross-sectional dimension of the dummy channel structure 1200 along the second direction Y may be greater than the maximum cross-sectional dimension of the channel structure 1300 along the second direction Y. The second direction Y may be perpendicular to the first direction X and the stacking direction Z. The dummy channel structure 1200 may include a first supporting portion (not shown) and a second supporting portion 1230 adjacently distributed along the second direction Y.

[0061] Forming the gate gap structure 1500 penetrating a portion of the dummy channel structure 1200 may include forming the gate gap structure 1500 penetrating the first supporting portion, wherein the second supporting portion 1230 may contact the gate gap structure 1500 .

[0062] In another exemplary embodiment of the present application, Fig.10 As shown, the maximum cross-sectional dimension H1 of the dummy channel structure 1200 along the second direction Y may be greater than the maximum cross-sectional dimension H2 of the channel structure 1300 along the second direction Y. The dummy channel structure 1200 may include a first supporting portion 1230 , a second supporting portion (not shown), and a third supporting portion 1240 adjacently distributed along the second direction Y.

[0063] Forming the gate gap structure 1500 penetrating a portion of the dummy channel structure 1200 may include forming the gate gap structure 1500 penetrating the second supporting portion, wherein the first supporting portion 1230 and the third supporting portion 1240 may contact both sides of the gate gap structure 1500 , respectively.

[0064] In another exemplary embodiment of the present application, Fig.11 As shown, the maximum cross-sectional dimension of the dummy channel structure 1200 along the second direction Y may be the same as the maximum cross-sectional dimension of the channel structure 1300 along the second direction Y. The plurality of dummy channel structures 1200 may include a first dummy channel structure 1200-1 and a second dummy channel structure 1200-2 adjacently distributed along the second direction Y. The gate gap structure 1500 may penetrate a portion of at least one of the first dummy channel structure 1200-1 and the second dummy channel structure 1200-2. For example, the gate gap structure 1500 may penetrate a portion of the first dummy channel structure 1200-1 or the second dummy channel structure 1200-2 to form a similar Fig. 9 or Fig.10 The structure shown.

[0065] In addition, the gate gap structure 1500 may penetrate a portion of the first dummy channel structure 1200-1 and the second dummy channel structure 1200-2. Fig.11 As shown, the first dummy channel structure 1200-1 may include a first supporting portion 1230 and a second supporting portion (not shown) adjacently arranged along the second direction Y. The second dummy channel structure 1200-2 may include a third supporting portion (not shown) and a fourth supporting portion 1240 adjacently arranged along the second direction Y.

[0066] The second support portion may be adjacent to the third support portion.

[0067] Forming a gate gap structure 1500 penetrating a portion of the dummy channel structure 1200 may include forming a gate gap structure 1500 penetrating a second support portion and a third support portion, wherein the first support portion 1230 and the fourth support portion 1260 may contact both sides of the gate gap structure 1500 , respectively.

[0068] It should be understood that the manner in which the gate gap structure 1500 penetrates a portion of the virtual channel structure 1200 listed in the present application is only an example and is not an exhaustive description. In the present application, the gate gap structure 1500 may penetrate any portion of the virtual channel structure 1200 that satisfies the actual process, so that the remaining portion of the virtual channel structure 1200 is in contact with the gate gap structure 1500. In this way, when a gate replacement process is performed via the gate gap (the gate gap structure 1500 may be formed by filling a dielectric material into the gate gap), the remaining portion of the virtual channel structure 1200 may serve as a supporting structure around the gate gap, thereby reducing the bending phenomenon of the first stacked structure. In addition, by setting the remaining portion of the virtual channel structure 1200 in contact with the gate gap structure 1500 (i.e., in contact with the gate gap), the difficulty of the gate gap formation process may also be reduced.

[0069] In the exemplary embodiment of the present application, Figure 8 As shown, forming the gate gap structure 1500 may include: forming a gate gap (not shown) that passes through the first stacked structure 1100; removing the first sacrificial layer 1120 through the gate gap to form a sacrificial gap (not shown); forming a gate layer 1130 in the sacrificial gap; and forming the gate gap structure 1500 in the gate gap.

[0070] For example, the gate gap may serve as a path for providing an etchant. For example, the gate gap may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate gap may penetrate a portion of the dummy channel structure 1200 along the stacking direction Z and may extend along the first direction X. As an alternative, Figure 8As shown, the gate gap structure 1500 may penetrate a portion of the dummy channel structure 1200 along the stacking direction Z and extend to the substrate 1400 . In other words, the gate gap structure 1500 may penetrate a portion of the dummy channel structure 1200 along the stacking direction Z and extend to the substrate 1400 .

[0071] It should be understood that the gate layer 1130 may include, for example, metal, etc. The gate layer 1130 may act as a control gate of each layer of memory cells to improve the control capability of the control gate. Exemplarily, the first sacrificial layer 1120 may be removed by a process such as wet etching to form a sacrificial gap.

[0072] In the exemplary embodiment of the present application, Figure 8 As shown, forming the gate layer 1130 in the sacrificial gap may include: sequentially forming a barrier layer 1140 and a gate layer 1130 in the sacrificial gap. The barrier layer 1140 may be located between the first dielectric layer 1110 and the gate layer 1130. In other words, the first dielectric layer 1110, the barrier layer 1140, and the gate layer 1130 are alternately stacked along the stacking direction Z of the first stacked structure 1100. It should be understood that the barrier layer 1140 may include, for example, aluminum oxide. The barrier layer 1140 may effectively prevent the charges in the gate layer 1130 from diffusing into the first dielectric layer 1110. On the other hand, the barrier layer 1140 may increase the dielectric constant between the gate layer 1130 and the first dielectric layer 1110, thereby enhancing the control capability of the gate layer 1130. For example, the barrier layer 1140 and the gate layer 1130 may be sequentially formed in the sacrificial gap by using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0073] In the exemplary embodiment of the present application, the gate gap may be filled with insulating material 1510 and dielectric material 1520 in sequence from outside to inside to form a gate gap structure 1500. The present application can disconnect adjacent gate layers 1130 by filling the inner wall of the gate gap with insulating material 1510, thereby avoiding the subsequent electrical connection of gate layers 1130 at different levels.

[0074] Exemplarily, after filling the insulating material 1510, the dielectric material 1520 may be filled in the remaining area of ​​the gate gap 1510 to form a gate gap structure 1500. The gate gap structure 1500 may be used to divide the storage area into a plurality of storage blocks. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to fill the dielectric material 1520 in the remaining area of ​​the gate gap to form the gate gap structure 1500. The dielectric material 1520 may be an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or may be a semiconductor material such as polysilicon, which is not limited in the present application.

[0075] In the exemplary embodiment of the present application, Figure 8 As shown, a top selection gate structure 1600 can be formed on the surface of the first stacked structure 1100 ; a top channel structure 1700 is formed along the stacking direction Z passing through the top selection gate structure 1600 and extending to the channel structure 1300 ; and an electrical contact structure 1800 connected to the top channel structure 1700 is formed.

[0076] For example, the top selection gate structure 1600 may include a multi-layer structure sequentially stacked on the surface of the first stacked structure 1100. The top channel structure 1700 may pass through the top selection gate structure 1600 along the stacking direction Z and extend to the channel plug 1390 of the channel structure 1300. The electrical contact structure 1800 may be used to transmit electrical signals between the outside and the channel structure 1300.

[0077] In another exemplary embodiment of the present application, Fig.12 As shown, the gate gap structure 1500 may be formed after forming the top selection gate structure 1600. In this way, the gate gap structure 1500 may penetrate the top selection gate structure 1600 and a portion of the dummy channel structure 1200.

[0078] It should be understood that the present application does not limit the order of the formation process of the gate gap structure 1500 and the top selection gate structure 1600. The order of the formation process of the gate gap structure 1500 and the top selection gate structure 1600 can be interchanged. In other words, the top selection gate structure 1600 can be formed after the gate gap structure 1500 is formed; of course, the gate gap structure 1500 can also be formed after the top selection gate structure 1600 is formed, and the present application does not make specific limitations on this.

[0079] As the storage capacity requirements of semiconductor structures continue to increase, the storage stack gradually increases. In the exemplary embodiment of the present application, multiple stack structures may be provided, such as a first stack structure and a second stack structure.

[0080] For example, Figures 13 to 21 As shown, the method 1000 for manufacturing a semiconductor structure is described by assuming that the semiconductor structure includes two stacked structures. It should be understood that the semiconductor structure may also include more stacked structures, and the present application does not impose any specific limitation on this.

[0081] like Fig.16 As shown, a plurality of dummy channel structures 1200 penetrating the first stacked structure 1100 may be formed, wherein the plurality of dummy channel structures 1200 are arranged along a first direction X, and the first direction X is perpendicular to a stacking direction Z of the first stacked structure 1100 .

[0082] Specifically, Fig.13 As shown, the first dielectric layer 1110 and the first sacrificial layer 1120 may be alternately stacked to form the first stacked structure 1100. For example, a virtual channel hole 1210 ( Fig.14 ), and then forming a filling dielectric layer 100 in the dummy channel hole 1200 to form a dummy channel structure 1200 ( Fig.16 ).

[0083] For example, Fig.13 As shown, a first stacked structure 1100 may be formed on a substrate 1400. The substrate 1400 may be used to support the first stacked structure 1100 thereon, and may be removed in a subsequent process.

[0084] For example, in the process of forming the dummy channel hole 1210, a plurality of first channel holes 1310 ( Fig.14 ), and then the sacrificial material 200 may be filled in the first channel hole 1310 to form an initial first channel structure 1320 ( Fig.15 ).

[0085] In the process of forming the dummy channel structure 1200, as shown in FIG. Fig.15 As shown, the sacrificial material 200 may be filled in the virtual channel hole 1210 and the first channel hole 1310 to form an initial virtual channel structure 1220 and an initial first channel structure 1320, respectively. The sacrificial material 200 may include a material such as carbide, which has a low density to facilitate subsequent removal. Fig.16 As shown, a mask layer 300 may be formed on the surface of the initial first channel structure 1320 to cover the initial first channel structure 1320. Then, the sacrificial material 200 in the virtual channel hole 1210 may be removed to form a gap (not shown), and a filling dielectric layer 100 may be formed in the gap to form the virtual channel structure 1200. It should be understood that in the process of forming the filling dielectric layer 100, the filling dielectric layer 100 ( Fig.16), the filling dielectric layer 100 on the first stacked structure 1100 may be removed by a mechanical grinding process to form Fig.17 The structure shown.

[0086] For example, in forming Fig.17 After the structure shown in Fig.18 As shown, the second dielectric layer 2110 and the second sacrificial layer 2120 may be alternately stacked on the surface of the first stacked structure 1100 to form the second stacked structure 2100 .

[0087] For example, the second dielectric layer 2110 and the second sacrificial layer 2120 may be sequentially stacked by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the second stacked structure 2100. It should be understood that the number and thickness of the second dielectric layer 2110 and the second sacrificial layer 2120 are not limited to Fig.18 As shown in the number and thickness, those skilled in the art can set any number and thickness of the second dielectric layer 2110 and the second sacrificial layer 2120 as needed without departing from the concept of the present application. In addition, the materials of the second dielectric layer 2110 and the second sacrificial layer 2120 can be selected from suitable materials known in the art, for example, the material of the second dielectric layer 2110 may include oxides such as silicon oxide, and the material of the second sacrificial layer 2120 may include nitrides such as silicon nitride.

[0088] For example, Fig.19 As shown, a second channel hole 2210 penetrating the second stacked structure 2100 may be formed, wherein the second channel hole 2210 may be connected to the initial first channel structure 1320. For example, the initial first channel structure 1320 may be removed via the second channel hole 2210 to form the channel hole 2200 ( Fig.19 ); and forming a channel structure 2300 in the channel hole 2200 ( Fig. 20 ). It should be understood that the channel hole 2200 may include a first channel hole 1310 and a second channel hole 2210 .

[0089] like Fig. 20 As shown, forming the channel structure 2300 may include: forming a functional layer 2370 and a channel layer 2360 in the channel hole 2200 from outside to inside; and forming a channel filling dielectric layer 2380 and a channel plug 2390. It should be understood that the channel structure 2300 may penetrate the first stacked structure 1100 and the second stacked structure 2100 and extend to the substrate 1400.

[0090] In the exemplary embodiment of the present application, Fig.21As shown, a gate gap structure 2500 penetrating a portion of the dummy channel structure 1200 may be formed, wherein the gate gap structure 2500 extends along the first direction X. Specifically, a gate gap structure 2500 penetrating the second stacked structure 2100 and penetrating a portion of the dummy channel structure 1200 may be formed. Figure 22 to Figure 24 Schematic diagrams showing the positional relationship between the dummy channel structure 1200 and the gate gap structure 2500 in three implementation modes are shown.

[0091] In the present application, a plurality of dummy channel structures 1200 may be arranged along the first direction X. Fig. 22 and Fig.23 As shown, the gate gap structure 2500 may penetrate the second stacked structure 2100 and penetrate a portion of a row of dummy channel structures 1200 arranged along the first direction X. In addition, a plurality of dummy channel structures 1200 may be adjacently distributed along the second direction Y, wherein the second direction Y may be perpendicular to the first direction X and the stacking direction Z. Fig.24 As shown, the gate gap structure 2500 may penetrate the second stacked structure 2100 and a portion of each row of dummy channel structures 1200 in two rows of dummy channel structures 1200 arranged along the first direction X and adjacently distributed along the second direction Y.

[0092] Specifically, in an exemplary embodiment of the present application, Fig. 22 As shown, the maximum cross-sectional dimension of the dummy channel structure 1200 along the second direction Y may be greater than the maximum cross-sectional dimension of the channel structure 2300 along the second direction Y. The second direction Y may be perpendicular to the first direction X and the stacking direction Z. The dummy channel structure 1200 may include a first supporting portion (not shown) and a second supporting portion 1230 adjacently distributed along the second direction Y.

[0093] Forming a gate gap structure 2500 penetrating the second stack structure 2100 and a portion of the dummy channel structure 1200 may include forming a gate gap structure 2500 penetrating the second stack structure 2100 and the first supporting portion, wherein the second supporting portion 1230 may contact the gate gap structure 2500 .

[0094] In another exemplary embodiment of the present application, Fig.23 As shown, the maximum cross-sectional dimension H1 of the dummy channel structure 1200 along the second direction Y may be greater than the maximum cross-sectional dimension H2 of the channel structure 2300 along the second direction Y. The dummy channel structure 1200 may include a first support portion 1230 , a second support portion (not shown), and a third support portion 1240 adjacently distributed along the second direction Y.

[0095] Forming a gate gap structure 2500 that penetrates the second stacked structure 2100 and a portion of the dummy channel structure 1200 may include: forming a gate gap structure 2500 that penetrates the second stacked structure 2100 and the second supporting portion, wherein the first supporting portion 1230 and the third supporting portion 1240 may contact two sides of the gate gap structure 2500 respectively.

[0096] In another exemplary embodiment of the present application, Fig.24 As shown, the maximum cross-sectional dimension of the dummy channel structure 1200 along the second direction Y may be the same as the maximum cross-sectional dimension of the channel structure 2300 along the second direction Y. The plurality of dummy channel structures 1200 may include a first dummy channel structure 1200-1 and a second dummy channel structure 1200-2 adjacently distributed along the second direction Y. The gate gap structure 2500 may penetrate a portion of at least one of the first dummy channel structure 1200-1 and the second dummy channel structure 1200-2. For example, the gate gap structure 2500 may penetrate the second stacked structure 2100, and penetrate a portion of the first dummy channel structure 1200-1 or the second dummy channel structure 1200-2 to form a similar Fig. 22 or Fig.23 The structure shown.

[0097] In addition, the gate gap structure 2500 may penetrate a portion of the first dummy channel structure 1200-1 and the second dummy channel structure 1200-2. Fig.24 As shown, the first dummy channel structure 1200-1 may include a first supporting portion 1230 and a second supporting portion (not shown) adjacently arranged along the second direction Y. The second dummy channel structure 1200-2 may include a third supporting portion (not shown) and a fourth supporting portion 1240 adjacently arranged along the second direction Y.

[0098] The second support portion may be adjacent to the third support portion.

[0099] Forming a gate gap structure 2500 that passes through the second stacked structure 2100 and a portion of the dummy channel structure 1200 may include: forming a gate gap structure 2500 that passes through the second stacked structure 2100, the second supporting portion, and the third supporting portion, wherein the first supporting portion 1230 and the fourth supporting portion 1260 may contact two sides of the gate gap structure 2500, respectively.

[0100] It should be understood that the manner in which the gate gap structure 2500 penetrates a portion of the virtual channel structure 1200 listed in the present application is only an example and is not exhaustive. In the present application, the gate gap structure 2500 may penetrate any portion of the virtual channel structure 1200 that satisfies the actual process, so that the remaining portion of the virtual channel structure 1200 is in contact with the gate gap structure 2500. In this way, when a gate replacement process is performed via the gate gap (the gate gap structure 2500 may be formed by filling a dielectric material into the gate gap), the remaining portion of the virtual channel structure 1200 may serve as a support structure around the gate gap, thereby reducing the bending phenomenon of the first stacked structure. In addition, by setting the remaining portion of the virtual channel structure 1200 in contact with the gate gap structure 1500 (i.e., in contact with the gate gap), the difficulty of the gate gap formation process may also be reduced.

[0101] In the exemplary embodiment of the present application, Fig.21 As shown, forming a gate gap structure 2500 may include: forming a gate gap (not shown) that passes through the second stacked structure 2100 and a portion of the virtual channel structure 1200; removing the first sacrificial layer 1120 and the second sacrificial layer 2120 through the gate gap to form a sacrificial gap (not shown); forming a gate layer 2130 within the sacrificial gap; and forming the gate gap structure 2500 within the gate gap.

[0102] For example, the gate gap may serve as a passage for providing an etchant. For example, the gate gap may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate gap may penetrate the second stacked structure 2100 and a portion of the dummy channel structure 1200 along the stacking direction Z, and may extend along the first direction X. As an alternative, as Fig.21 As shown, the gate gap may penetrate the second stacked structure 2100 and a portion of the dummy channel structure 1200 along the stacking direction Z, and extend to the substrate 1400. In other words, the gate gap structure 2500 may penetrate the second stacked structure 2100 and a portion of the dummy channel structure 1200 along the stacking direction Z, and extend to the substrate 1400.

[0103] It should be understood that the gate layer 2130 may include, for example, metal, etc. The gate layer 2130 may serve as a control gate of each layer of memory cells to improve the control capability of the control gate. Exemplarily, the first sacrificial layer 1120 and the second sacrificial layer 2120 may be removed by using a process such as wet etching to form a sacrificial gap.

[0104] In the exemplary embodiment of the present application, Fig.21As shown, forming the gate layer 2130 in the sacrificial gap may include: sequentially forming a barrier layer 2140 and a gate layer 2130 in the sacrificial gap. The barrier layer 2140 may be located between the first dielectric layer 1110 and the gate layer 2130 and between the second dielectric layer 2110 and the gate layer 2130. In other words, the first dielectric layer 1110 (or the second dielectric layer 2110), the barrier layer 2140 and the gate layer 2130 are alternately stacked along the stacking direction Z. It should be understood that the barrier layer 2140 may include, for example, aluminum oxide. The barrier layer 2140 may effectively prevent the charges in the gate layer 2130 from diffusing into the first dielectric layer 1110 and the second dielectric layer 2110. On the other hand, the barrier layer 2140 may increase the dielectric constant between the gate layer 2130 and the first dielectric layer 1110, and between the gate layer 2130 and the second dielectric layer 2110, thereby enhancing the control capability of the gate layer 2130. For example, the barrier layer 2140 and the gate layer 2130 may be sequentially formed in the sacrificial gap by using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0105] In the exemplary embodiment of the present application, the gate gap may be filled with insulating material 2510 and dielectric material 2520 in sequence from outside to inside to form a gate gap structure 2500. The present application can disconnect adjacent gate layers 2130 by filling the inner wall of the gate gap with insulating material 2510, thereby avoiding the subsequent electrical connection of gate layers 2130 at different levels.

[0106] Exemplarily, after filling the insulating material 2510, the dielectric material 2520 may be filled in the remaining area of ​​the gate gap 2510 to form a gate gap structure 2500. The gate gap structure 2500 may be used to divide the storage area into a plurality of storage blocks. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to fill the dielectric material 2520 in the remaining area of ​​the gate gap to form the gate gap structure 2500. The dielectric material 2520 may be an insulating dielectric material such as silicon oxide, silicon nitride, and silicon oxynitride, or may be a semiconductor material such as polysilicon, which is not limited in the present application.

[0107] In the exemplary embodiment of the present application, Fig.21 As shown, a top selection gate structure 1600 can be formed on the surface of the second stacked structure 2100 ; a top channel structure 1700 is formed along the stacking direction Z passing through the top selection gate structure 1600 and extending to the channel structure 2300 ; and an electrical contact structure 1800 connected to the top channel structure 1700 is formed.

[0108] For example, the top selection gate structure 1600 may include a multi-layer structure sequentially stacked on the surface of the second stacked structure 2100. The top channel structure 1700 may pass through the top selection gate structure 1600 along the stacking direction Z and extend to the channel plug 2390 of the channel structure 2300. The electrical contact structure 1800 may be used to transmit electrical signals between the outside and the channel structure 2300.

[0109] In another exemplary embodiment of the present application, Fig.25 As shown, the gate gap structure 2500 may be formed after forming the top selection gate structure 1600 . In this way, the gate gap structure 2500 may penetrate the top selection gate structure 1600 , the second stacked structure 2100 , and a portion of the dummy channel structure 1200 .

[0110] It should be understood that the present application does not limit the order of the formation process of the gate gap structure 2500 and the top selection gate structure 1600. The order of the formation process of the gate gap structure 2500 and the top selection gate structure 1600 can be interchanged. In other words, the top selection gate structure 1600 can be formed after the gate gap structure 2500 is formed; of course, the gate gap structure 2500 can also be formed after the top selection gate structure 1600 is formed, and the present application does not make specific limitations on this.

[0111] Fig.26 is a schematic structural diagram of a semiconductor structure 3000 according to an exemplary embodiment of the present application.

[0112] The semiconductor structure 3000 may include a first stacked structure 3100 , a plurality of support structures 3200 , and a gate spacer structure 3500 .

[0113] The first stacked structure 3100 may include alternately stacked first dielectric layers 3110, barrier layers 3140, and gate layers 3130. It should be understood that the number and thickness of the first dielectric layers 3110, barrier layers 3140, and gate layers 3130 are not limited to Fig.26 The number and thickness shown in the figure, without departing from the concept of the present application, those skilled in the art can set any number and thickness of the first dielectric layer 3110, the barrier layer 3140 and the gate layer 3130 as needed. In addition, the materials of the first dielectric layer 3110, the barrier layer 3140 and the gate layer 3130 can be selected from suitable materials known in the art, for example, the material of the first dielectric layer 3110 may include oxide. The material of the barrier layer 1140 may include aluminum oxide, etc. The material of the gate layer 3130 may include a combination of metals and / or metal compounds.

[0114] The plurality of support structures 3200 may penetrate the first stacked structure 3100. The plurality of support structures 3200 may be arranged along a first direction X, and the first direction X may be perpendicular to a stacking direction Z of the first stacked structure 3100. The material of the support structure 3200 may include oxide.

[0115] The gate gap structure 3500 may penetrate the first stacked structure 3100 and extend along the first direction X, wherein the gate gap structure 3500 may contact the support structure 3200. By way of example, the support structure 3200 may be located on at least one side of the gate gap structure 3500. By setting the gate gap structure 3500 in contact with the support structure 3200, the present application can achieve that in the process of manufacturing the semiconductor structure 3000, the support structure 3200 has a supporting function, reduces the bending phenomenon of the first stacked structure, and reduces the difficulty of the formation process of the gate gap structure 3500. By way of example, the gate gap structure 3500 may include an insulating material 3510 and a dielectric material 3520 in sequence from the outside to the inside.

[0116] In an exemplary embodiment of the present application, the semiconductor structure 3000 may further include a channel structure 3300 that penetrates the first stacked structure. The channel structure 3300 includes a blocking layer, a charge trapping layer, a tunneling layer, and a channel layer in sequence from the outside to the inside. In addition, the channel structure 3300 may further include a channel filling dielectric layer located inside the channel layer and a channel plug 3390 connected to the channel layer.

[0117] like Figure 27 to Figure 29 Schematic diagrams showing the positional relationship between the support structure 3200 and the gate gap structure 3500 of three embodiments of the present application are shown.

[0118] In an exemplary embodiment of the present application, Fig. 27 As shown, the support structure 3200 may be located on one side of the gate gap structure 3500. In another exemplary embodiment of the present application, as shown in FIG. Fig.28 or Fig.29 As shown, the support structure 3200 may be located on both sides of the gate gap structure 3500. Exemplarily, the plurality of support structures 3200 include a first support structure 3210 and a second support structure 3220 adjacently distributed along a second direction Y, wherein the second direction Y is perpendicular to the first direction X and the stacking direction Z. The first support structure 3210 and the second support structure 3220 may be located on both sides of the gate gap structure 3500, respectively.

[0119] In the present application, the shapes of the multiple support structures 3200 can be any shape that meets the actual process requirements, and the present application does not specifically limit this. For example, the support structure 3200 can have a partial cylindrical or partial columnar shape extending along the stacking direction Z in the first stacked structure 1100. In addition, in the actual process, the curvature of the partial cylindrical shape can be arbitrarily adjusted according to the requirements, that is, the degree of curvature of the partial cylindrical shape can be reasonably set according to the requirements. Specifically, in the case of Fig.28 In the embodiment shown, the curvatures of the first support structure 3210 and the second support structure 3220 are relatively large, and the number of support structures in contact with the gate gap structure 3500 is relatively small. Fig.29 In the illustrated embodiment, the curvatures of the first support structure 3210 and the second support structure 3220 are relatively small, and the number of support structures in contact with the gate gap structure 3500 is relatively large.

[0120] In the exemplary embodiment of the present application, Fig.26 As shown, the semiconductor structure 3000 may further include a substrate 3400 , a top select gate structure 3600 , a top channel structure 3700 , and an electrical contact structure 3800 .

[0121] The first stacked structure 3100 may be located on a substrate 3400. The substrate 3400 may be used to support the first stacked structure 3100 thereon. The top selection gate structure 3600 may include a multi-layer structure sequentially stacked on the surface of the first stacked structure 3100. The top channel structure 3700 may pass through the top selection gate structure 3600 along the stacking direction Z and extend to the channel plug 3390 of the channel structure 3300. The electrical contact structure 3800 may be used to transmit an electrical signal between the outside and the channel structure 3300.

[0122] In another exemplary embodiment of the present application, the gate gap structure 3500 may penetrate the top selection gate structure 3600 and the first stacked structure 3100 and extend along the first direction X, wherein the gate gap structure 3500 may contact the support structure 3200 .

[0123] In another exemplary embodiment of the present application, the semiconductor structure 3000 may further include a second stacked structure (not shown). The second stacked structure may be located on the surface of the first stacked structure 3100. The gate gap structure 3500 may penetrate the second stacked structure and the first stacked structure 3100 along the stacking direction Z and extend along the first direction X, wherein the gate gap structure 3500 may contact the support structure 3200. The channel structure 3300 may penetrate the first stacked structure 3100 and the second stacked structure.

[0124] In another exemplary embodiment of the present application, the gate gap structure 3500 may penetrate the top selection gate structure 3600 , the second stacked structure, and the first stacked structure 3100 and extend along the first direction X, wherein the gate gap structure 3500 may contact the support structure 3200 .

[0125] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure 3000 described herein, the contents related or similar thereto will not be described in detail herein.

[0126] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0127] Fig.30 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0128] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.30 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0129] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0130] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.31AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.30 The host 18 in the memory card connector 24 is coupled. Fig.31B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig. 20 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0131] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of dummy channel structures penetrating the first stacked structure, wherein the plurality of dummy channel structures are arranged along a first direction, the first direction being perpendicular to a stacking direction of the first stacked structure; and A gate gap structure is formed penetrating a portion of the dummy channel structure, wherein the gate gap structure extends along the first direction.

2. The method according to claim 1, characterized in that: The dummy channel structure includes a first supporting portion and a second supporting portion adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and a gate gap structure is formed that penetrates a portion of the dummy channel structure, including: The gate gap structure is formed to penetrate the first support portion, wherein the second support portion is in contact with the gate gap structure.

3. The method according to claim 1, characterized in that The virtual channel structure includes a first supporting portion, a second supporting portion, and a third supporting portion adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and a gate gap structure is formed that penetrates a portion of the virtual channel structure, including: The gate gap structure is formed to penetrate the second supporting portion, wherein the first supporting portion and the third supporting portion are in contact with two sides of the gate gap structure, respectively.

4. The method according to claim 1, characterized in that: The multiple virtual channel structures include a first virtual channel structure and a second virtual channel structure adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and the gate gap structure penetrates a portion of at least one of the first virtual channel structure and the second virtual channel structure.

5. The method according to claim 4, characterized in that The first dummy channel structure includes a first supporting portion and a second supporting portion adjacently distributed along the second direction, and the second dummy channel structure includes a third supporting portion and a fourth supporting portion adjacently distributed along the second direction, wherein the second supporting portion and the third supporting portion are adjacent to each other, forming a gate gap structure that penetrates a portion of the dummy channel structure, including: The gate gap structure is formed to penetrate the second support portion and the third support portion, wherein the first support portion and the fourth support portion are in contact with both sides of the gate gap structure, respectively.

6. The method according to claim 1, characterized in that The method comprises: Forming a plurality of the dummy channel structures penetrating the first stacked structure and a channel structure penetrating a second stacked structure and the first stacked structure, wherein the second stacked structure is located on a surface of the first stacked structure, and forming a gate gap structure penetrating a portion of the dummy channel structure, comprising: The gate gap structure is formed to penetrate the second stacked structure and a portion of the dummy channel structure.

7. The method according to claim 6, characterized in that Forming a plurality of the dummy channel structures penetrating the first stacked structure and a channel structure penetrating the second stacked structure and the first stacked structure, comprising: forming a plurality of dummy channel structures and an initial first channel structure penetrating the first stacked structure; forming the second stacked structure, and forming a second channel hole penetrating the second stacked structure, wherein the second channel hole is connected to the initial first channel structure; removing the initial first channel structure through the second channel hole to form a channel hole; and A channel structure is formed in the channel hole.

8. The method according to claim 7, characterized in that Forming a plurality of dummy channel structures and an initial first channel structure that penetrate the first stacked structure, comprising: forming a plurality of virtual channel holes and first channel holes penetrating the first stacked structure; Filling sacrificial material in the dummy channel hole and the first channel hole to form an initial dummy channel structure and the initial first channel structure, respectively; and The initial dummy channel structure is replaced with the dummy channel structure.

9. The method according to claim 8, characterized in that Replacing the initial virtual channel structure with the virtual channel structure comprises: removing the sacrificial material in the virtual channel hole to form a gap; and A filling dielectric layer is formed in the gap.

10. The method according to any one of claims 6 to 9, characterized in that: The first stacked structure includes alternately stacked first dielectric layers and first sacrificial layers, the second stacked structure includes alternately stacked second dielectric layers and second sacrificial layers, and the gate gap structure that penetrates the second stacked structure and penetrates a portion of the dummy channel structure is formed, including: forming a gate gap penetrating the second stacked structure and penetrating a portion of the dummy channel structure; removing the first sacrificial layer and the second sacrificial layer through the gate gap to form a sacrificial gap; forming a gate layer in the sacrificial gap; and The gate gap structure is formed in the gate gap.

11. The method according to any one of claims 6 to 9, characterized in that: The method further comprises: forming a top selection gate structure on a surface of the second stacked structure; forming a top channel structure passing through the top select gate structure and extending to the channel structure along the stacking direction; and An electrical contact structure is formed in connection with the top trench structure.

12. The method according to claim 11, characterized in that The gate gap structure penetrates the top selection gate structure, the second stacked structure, and a portion of the dummy channel structure.

13. A semiconductor structure, characterized in that: include: A first laminate structure; A plurality of support structures, which penetrate the first stacked structure, wherein the plurality of support structures are arranged along a first direction, and the first direction is perpendicular to a stacking direction of the first stacked structure; as well as A gate gap structure penetrates the first stacked structure and extends along the first direction, wherein the gate gap structure is in contact with the support structure.

14. The semiconductor structure according to claim 13, characterized in that: The support structure is located on at least one side of the gate gap structure.

15. The semiconductor structure according to claim 13, characterized in that The plurality of support structures include a first support structure and a second support structure adjacently distributed along a second direction, wherein the second direction is perpendicular to the first direction and the stacking direction, and the first support structure and the second support structure are respectively located on both sides of the gate gap structure.

16. The semiconductor structure according to claim 13, characterized in that The material of the support structure includes oxide.

17. The semiconductor structure according to claim 13, characterized in that The semiconductor structure further comprises: a second stacked structure, located on a surface of the first stacked structure, wherein the gate gap structure penetrates the second stacked structure and the first stacked structure along the stacking direction; and The channel structure runs through the first stacked structure and the second stacked structure, and includes a blocking layer, a charge trapping layer, a tunneling layer and a channel layer in sequence from the outside to the inside.

18. A storage system, characterized in that: include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 13 to 17; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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