A high-density linear capacitor and its preparation method, and image sensor

Abstract

The present invention provides a high-density linear capacitor and a preparation method thereof, and an image sensor, comprising: providing a basic capacitor structure; forming a functional column on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area; forming a multi-layer stacked extended capacitor structure in the first area and the second area. By forming a multi-layer stacked extended capacitor structure on the existing basic capacitor structure, the capacitance per unit area of ​​the capacitor is effectively increased; at the same time, by forming a functional column, the extended capacitor structure is supported, the stability of the extended capacitor structure relative to the basic capacitor structure is ensured, and the problem of small capacitance of the existing capacitor used for image sensors is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a high-density linear capacitor and a preparation method thereof, and an image sensor. Background Art

[0002] Image sensors are mainly composed of pixel arrays and readout circuits. Their working performance is not only related to the quantum efficiency, spectral response, noise, uniformity, etc. of the pixel array, but also to the charge storage, uniformity, linearity, noise, injection efficiency, etc. of the readout circuit. At present, the main factor limiting the working performance of image sensors is the integral capacitor in the readout circuit. The integral capacitor reflects the ability of the readout circuit to store charge. The larger its capacitance, the more effectively it can improve the charge processing capability of the image sensor, thereby improving the dynamic range, signal-to-noise ratio, sensitivity and other performance of the image sensor, and improving the quality of the final output image.

[0003] However, the integrating capacitors used in the current image sensor readout circuits are usually single-layer MOS capacitors, and the capacitance density of this structure is usually about 5fF / μm 2 , which cannot meet the 50~100fF / μm required by the application 2 . Summary of the invention

[0004] The object of the present invention is to provide a high-density linear capacitor and a preparation method thereof, and an image sensor, so as to at least solve the problem that the existing capacitor used for image sensors has a relatively small capacitance.

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a high-density linear capacitor, comprising:

[0006] Provide basic capacitor structure;

[0007] forming a functional column on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area;

[0008] A multi-layer stacked extended capacitor structure is formed in the first region and the second region.

[0009] Optionally, in the method for preparing the high-density linear capacitor, the basic capacitor structure is a MOS capacitor, a MOM capacitor, a MIM capacitor or a PIP capacitor.

[0010] Optionally, in the method for preparing the high-density linear capacitor, the bottom of the functional column is in contact with the top metal layer of the basic capacitor structure.

[0011] Optionally, in the method for preparing the high-density linear capacitor, the material of the functional column is indium or silicon.

[0012] Optionally, in the method for preparing the high-density linear capacitor, the method for forming a multi-layer stacked extended capacitor structure in the first region and the second region includes:

[0013] Preparing conductive masks and dielectric masks;

[0014] Alternately using a conductive mask and a dielectric mask to alternately form a conductive electrode plate and a dielectric layer in the first area and the second area from bottom to top;

[0015] All the conductive electrode plates in the first region are alternately connected through the first through hole and the second through hole, and all the conductive electrode plates in the second region are alternately connected through the third through hole and the fourth through hole.

[0016] Optionally, in the method for preparing the high-density linear capacitor, one of the first through hole and the second through hole contacts the top metal layer of the basic capacitor structure; one of the third through hole and the fourth through hole contacts the top metal layer of the basic capacitor structure.

[0017] Optionally, in the method for preparing the high-density linear capacitor, the layout structure of the conductive electrode plate and the dielectric layer in the first region is consistent with the layout structure of the conductive electrode plate and the dielectric layer in the second region.

[0018] Optionally, in the method for preparing the high-density linear capacitor, the conductive mask includes a first conductive mask and a second conductive mask, and the method of alternately using the conductive mask and the dielectric mask to alternately form the conductive electrode plate and the dielectric layer in the first region and the second region from bottom to top includes:

[0019] A first conductive mask, a dielectric mask, and a second conductive mask are alternately used to form a first conductive electrode plate, a dielectric layer, and a second conductive electrode plate in the first region and the second region from bottom to top, wherein a vertical projection of the first conductive electrode plate and a vertical projection of the second conductive electrode plate do not completely overlap.

[0020] In order to solve the above technical problems, the present invention also provides a high-density linear capacitor, which is prepared using the preparation method of the high-density linear capacitor as described in any of the above items, and the high-density linear capacitor includes a basic capacitor structure, a functional column, a first extended capacitor structure and a second extended capacitor structure; the functional column is formed on the top of the basic capacitor structure, and divides the top of the basic capacitor structure into a first area and a second area; the first extended capacitor structure is located in the first area and is in contact with the top of the basic capacitor structure; the second extended capacitor structure is located in the second area and is in contact with the top of the basic capacitor structure.

[0021] Optionally, in the high-density linear capacitor, the bottom of the functional column is in contact with the top metal layer of the basic capacitor structure.

[0022] Optionally, in the high-density linear capacitor, the first extended capacitor structure and the second extended capacitor structure both include multiple layers of conductive electrode plates and dielectric layers alternately stacked in sequence from bottom to top; all conductive electrode plates of the first extended capacitor structure are alternately connected through the first through hole and the second through hole, and one of the first through hole and the second through hole is in contact with the top metal layer of the basic capacitor structure; all conductive electrode plates of the second extended capacitor structure are alternately connected through the third through hole and the fourth through hole, and one of the third through hole and the fourth through hole is in contact with the top metal layer of the basic capacitor structure.

[0023] Optionally, in the high-density linear capacitor, the layout structure of the conductive plates and the dielectric layer of the first extended capacitor structure is consistent with the layout structure of the conductive plates and the dielectric layer of the second extended capacitor structure.

[0024] In order to solve the above technical problem, the present invention further provides an image sensor, comprising a readout circuit, wherein the integral capacitor in the readout circuit is a high-density linear capacitor as described in any one of the above items.

[0025] The high-density linear capacitor and its preparation method, and image sensor provided by the present invention include: providing a basic capacitor structure; forming a functional column on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area; forming a multi-layer stacked extended capacitor structure in the first area and the second area. By forming a multi-layer stacked extended capacitor structure on the existing basic capacitor structure, the capacitance per unit area of ​​the capacitor is effectively increased; at the same time, by forming a functional column, the extended capacitor structure is supported, the stability of the extended capacitor structure relative to the basic capacitor structure is ensured, and the problem of small capacitance of the existing capacitor used for image sensors is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the capacitance variation curve of multilayer stack capacitor, MOS capacitor, PIP capacitor and MIM capacitor with voltage;

[0027] Figure 2 A flow chart of a method for preparing a high-density linear capacitor provided in this embodiment;

[0028] FIG3 (A) is a schematic diagram of the structure of the high-density linear capacitor provided in step S1 of this embodiment;

[0029] FIG3 (B) is a schematic diagram of the structure of the high-density linear capacitor provided in step S2 of this embodiment;

[0030] FIG3 (C) is a schematic diagram of the structure of the high-density linear capacitor provided in this embodiment in step S32;

[0031] FIG3 (D) is a schematic diagram of the structure of the high-density linear capacitor provided in this embodiment in step S33;

[0032] The descriptions of the reference numerals are as follows:

[0033] 100-basic capacitor structure; 110-top metal layer; 120-top dielectric layer; 200-functional column; 201-first region; 202-second region; 210-first conductive electrode plate; 220-dielectric layer; 230-second conductive electrode plate; 240-first through hole; 250-second through hole; 260-third through hole; 270-fourth through hole. DETAILED DESCRIPTION

[0034] The high-density linear capacitor and its preparation method and image sensor proposed in the present invention are further described in detail below in combination with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used.

[0035] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] In order to expand the capacitance, researchers proposed a multi-layer stack capacitor, which uses a multi-layer vertical "stacking" process to obtain a larger capacitance in a smaller space. For example, on the existing MOS capacitor structure, PIP (Poly-Insulator-Poly) capacitors and MIM (Metal-Insulator-Metal) capacitors are stacked in sequence. Although this type of capacitor has a larger capacitance, Figure 1 As shown, the capacitance value of the capacitor changes with the voltage across it, which makes the capacitor insufficiently linear. When applied to an image sensor, it is easy to cause nonlinearity in signal integration, thereby affecting the output image quality.

[0037] Based on this, this embodiment provides a method for preparing a high-density linear capacitor, such as Figure 2 As shown, including:

[0038] S1, provides basic capacitor structure;

[0039] S2, forming a functional column on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area;

[0040] S3, forming a multi-layer stacked extended capacitor structure in the first region and the second region.

[0041] The preparation method of the high-density linear capacitor provided in this embodiment effectively increases the capacitance per unit area of ​​the capacitor by forming a multi-layer stacked extended capacitor structure on the existing basic capacitor structure; at the same time, by forming functional columns, the extended capacitor structure is supported, thereby ensuring the stability of the extended capacitor structure relative to the basic capacitor structure, thereby solving the problem of the small capacitance of existing capacitors used for image sensors.

[0042] Specifically, in this embodiment, step S1 provides a basic capacitor structure, wherein the basic capacitor structure can be a MOS capacitor, a MOM capacitor, a MIM capacitor or a PIP capacitor. The preparation method of the basic capacitor structure is well known to those skilled in the art and will not be described in detail in this application.

[0043] In this embodiment, as shown in FIG3 (A), the basic capacitor structure 100 has a top metal layer 110 and a top dielectric layer 120 formed on the top, wherein the top dielectric layer 120 covers the top metal layer 110. Of course, no matter what structure the capacitor has, the top metal layer 110 and the top dielectric layer 120 are essential structural layers.

[0044] In practical applications, the material of the top metal layer 110 may be metal, and the material of the top dielectric layer 120 may be silicide such as silicon nitride.

[0045] Furthermore, in this embodiment, in step S2, a functional column is formed on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area.

[0046] Specifically, in order to facilitate effective electrical connection between the output MOS tube in the pixel array and the integral capacitor of the readout circuit in the subsequent manufacturing process, in this embodiment, the functional column 200 can be used as a conductor between the two.

[0047] At this time, as shown in FIG3 (B), a contact hole can be opened on the top dielectric layer 120 by using a photolithography process and a photomask, and the bottom of the contact hole should be the top metal layer 110; then a functional column 200 with a certain height is formed on the contact hole. In this way, a functional column 200 is formed on the top of the basic capacitor structure 100, and the area on the left side of the functional column 200 is defined as a first area 201, and the area on the right side is defined as a second area 202, and the bottom of the functional column 200 is in contact with the top metal layer 110 of the basic capacitor structure 100.

[0048] In practical applications, the material of the functional column 200 can be indium or silicon.

[0049] Further, in this embodiment, in step S3, the method of forming a multi-layer stacked extended capacitor structure in the first region and the second region includes:

[0050] S31, preparing a conductive mask and a dielectric mask.

[0051] Specifically, in this embodiment, considering that a multi-layer stacked extended capacitor structure needs to be formed in the first region and the second region, the conductive mask and the dielectric mask can be reused multiple times, thereby saving costs.

[0052] Preferably, considering that in order to facilitate the interconnection of multi-layer stacked conductive plates in subsequent processes so that the multi-layer capacitors in the extended capacitor structure can be connected in parallel, in this embodiment, the conductive mask plate includes a first conductive mask plate and a second conductive mask plate, and the conductive plates formed by the first conductive mask plate and the second conductive mask plate do not completely overlap in vertical projection. In this way, all conductive plates formed by the first conductive mask plate can be connected in non-overlapping areas through through holes, and all conductive plates formed by the second conductive mask plate can be connected.

[0053] S32, alternately using a conductive mask and a dielectric mask to alternately form a conductive electrode plate and a dielectric layer in the first area and the second area from bottom to top.

[0054] Specifically, in this embodiment, alternately forming conductive electrodes and dielectric layers means that a conductive electrode layer is first formed using a conductive mask, and then a dielectric layer is formed on the surface of the conductive electrode plate using a dielectric mask, and then a conductive electrode is formed on the surface of the dielectric layer using a conductive mask... This process is repeated many times until the preparation of a preset number of conductive electrodes and dielectric layers is completed.

[0055] As described above, when the conductive mask includes a first conductive mask and a second conductive mask, the method of alternately using the conductive mask and the dielectric mask to alternately form the conductive electrode and the dielectric layer in the first region and the second region from bottom to top includes:

[0056] A first conductive mask, a dielectric mask, and a second conductive mask are alternately used to form a first conductive electrode plate, a dielectric layer, and a second conductive electrode plate in the first region and the second region from bottom to top, wherein a vertical projection of the first conductive electrode plate and a vertical projection of the second conductive electrode plate do not completely overlap.

[0057] As shown in FIG3 (C), a first conductive electrode plate 210 is first formed on the surface of the top dielectric layer 120 using a first conductive mask, and then a dielectric layer 220 is formed on the surface of the first conductive electrode plate 210 using a dielectric mask. Then, a second conductive electrode plate 230 is formed on the surface of the dielectric layer 220 using a second conductive mask, and then a dielectric layer 220 is formed on the surface of the second conductive electrode plate 230 using a dielectric mask. The above steps are repeated to form a first conductive electrode plate 210, and so on. Multiple layers of stacked conductive electrode plates and dielectric layers are formed repeatedly.

[0058] The conductive electrode plates (the first conductive electrode plate 210 and the second conductive electrode plate 230 ) may be made of metal, and the dielectric layer 220 may be made of silicide.

[0059] Preferably, in order to ensure the stability of the capacitor structure and reduce process complexity, in this embodiment, the layout structure of the conductive electrode plate and the dielectric layer in the first area 201 is consistent with the layout structure of the conductive electrode plate and the dielectric layer in the second area 202.

[0060] S33, all the conductive electrode plates in the first region are alternately connected through the first through hole and the second through hole, and all the conductive electrode plates in the second region are alternately connected through the third through hole and the fourth through hole.

[0061] Specifically, in this embodiment, since in the first region 201, the conductive electrode plates are divided into the first conductive electrode plates 210 and the second conductive electrode plates 220, and all the first conductive electrode plates 210 completely overlap in the vertical projection, all the second conductive electrode plates 230 completely overlap in the vertical projection, and the first conductive electrode plates 210 and the second conductive electrode plates 230 do not completely overlap in the vertical projection, therefore, as shown in FIG3 (D), all the first conductive electrode plates 210 can be turned on through the first through hole 240, and all the second conductive electrode plates 230 can be turned on through the second through hole 250. That is, using through holes to alternately turn on the conductive electrode plates means that through the same through hole, the conductive electrode plates separated by one conductive electrode plate are turned on, so that a plurality of parallel MIM structure capacitors can be formed.

[0062] Similarly, all the conductive electrode plates in the second region 202 may be alternately connected through the third through holes 260 and the fourth through holes 270 .

[0063] In addition, in order to ensure that the extended capacitor structure is connected in parallel with the basic capacitor structure to increase the capacitance, in the present embodiment, one of the first through hole 240 and the second through hole 250 is in contact with the top metal layer 110 of the basic capacitor structure. In the structure shown in FIG. 3 (D), the second through hole 250 is in contact with the top metal layer 110; one of the third through hole 260 and the fourth through hole 270 is in contact with the top metal layer 110 of the basic capacitor structure. In the structure shown in FIG. 3 (D), the fourth through hole 270 is in contact with the top metal layer 110.

[0064] It should be noted that, although in the capacitor structure shown in FIG. 3 (D), the first through hole 240 and the third through hole 260 are formed downward from the first conductive electrode plate 210 of the top layer, in the actual process, in order to reduce the complexity of the process, the through holes can be formed downward from the top of the capacitor structure together with the second through hole 250 and the fourth through hole 270. This not only integrates the through hole process into one step, but also does not affect the connection of the through holes to the corresponding conductive electrode plates.

[0065] In practical applications, the number of stacking times of the conductive plates can be reasonably set according to the actual capacitance value requirements, and this application does not impose any restrictions on this.

[0066] Furthermore, on the top of the extended capacitor structure, a structure of an output MOS tube in a pixel array can be formed, and its specific preparation method is well known to those skilled in the art, and will not be described in detail in this application.

[0067] The method for preparing a high-density linear capacitor provided in this embodiment forms an extended capacitor structure by stacking multiple MIM structure capacitors on an existing basic capacitor structure, and organically connects the extended capacitor structure to the basic capacitor structure through a through hole, thereby connecting multiple capacitors in parallel to increase the capacitance without increasing the capacitor area. In addition, the functional column is used to not only provide strong support for the extended capacitor structure and improve the stability of the capacitor structure, but also to realize the electrical connection between the capacitor and other components by using the functional column, thereby reducing the overall circuit area and improving the circuit integration.

[0068] The present embodiment also provides a high-density linear capacitor, which is prepared by the preparation method of the high-density linear capacitor as described above, as shown in Figure 3 (D), the high-density linear capacitor includes a basic capacitor structure 100, a functional column 200, a first extended capacitor structure and a second extended capacitor structure; the functional column 200 is formed on the top of the basic capacitor structure 100, and divides the top of the basic capacitor structure 100 into a first area and a second area; the first extended capacitor structure is located in the first area and is in contact with the top of the basic capacitor structure 100; the second extended capacitor structure is located in the second area and is in contact with the top of the basic capacitor structure 100.

[0069] Specifically, in the present embodiment, both the first extended capacitor structure and the second extended capacitor structure include a plurality of conductive electrode plates (a first conductive electrode plate 210 and a second conductive electrode plate 230) and a dielectric layer 220 alternately stacked in sequence from bottom to top; all conductive electrode plates of the first extended capacitor structure are alternately connected through the first through hole 240 and the second through hole 250, and one of the first through hole 240 and the second through hole 250 is in contact with the top metal layer 110 of the basic capacitor structure 100; all conductive electrode plates of the second extended capacitor structure (the first conductive electrode plate 210 and the second conductive electrode plate 230) are alternately connected through the third through hole 260 and the fourth through hole 270, and one of the third through hole 260 and the fourth through hole 270 is in contact with the top metal layer 110 of the basic capacitor structure 100.

[0070] Preferably, in order to ensure the stability of the capacitor structure, in this embodiment, the layout structure of the conductive plate and the dielectric layer of the first extended capacitor structure is consistent with the layout structure of the conductive plate and the dielectric layer of the second extended capacitor structure.

[0071] In practical applications, other devices may be formed on the top of the high-density linear capacitor, i.e., the conductive plate on the top of the first extended capacitor structure and the second extended capacitor structure, to be integrated with other devices. For example, an output MOS tube with a pixel array may be integrated on the conductive plate on the top of the first extended capacitor structure and the second extended capacitor structure.

[0072] The high-density linear capacitor provided in this embodiment effectively increases the capacitance per unit area of ​​the capacitor by forming a multi-layer stacked extended capacitor structure on the existing basic capacitor structure; at the same time, by forming functional columns, the extended capacitor structure is supported, thereby ensuring the stability of the extended capacitor structure relative to the basic capacitor structure, thereby solving the problem of the small capacitance of existing capacitors used for image sensors.

[0073] Furthermore, this embodiment further provides an image sensor, including a readout circuit, wherein the integral capacitor in the readout circuit is the high-density linear capacitor as described above.

[0074] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0075] The high-density linear capacitor and its preparation method, and the image sensor provided in this embodiment include: providing a basic capacitor structure; forming a functional column on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area; forming a multi-layer stacked extended capacitor structure in the first area and the second area. By forming a multi-layer stacked extended capacitor structure on the existing basic capacitor structure, the capacitance per unit area of ​​the capacitor is effectively increased; at the same time, by forming a functional column, the extended capacitor structure is supported, the stability of the extended capacitor structure relative to the basic capacitor structure is ensured, and the problem of small capacitance of the existing capacitor used for image sensors is solved.

[0076] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a high-density linear capacitor, characterized in that: include: Provide basic capacitor structure; forming a functional column on the top of the basic capacitor structure to divide the top of the basic capacitor structure into a first area and a second area; A multi-layer stacked extended capacitor structure is formed in the first region and the second region, comprising: Preparing a conductive mask and a dielectric mask, wherein the conductive mask comprises a first conductive mask and a second conductive mask; Alternately using a first conductive mask, a dielectric mask, and a second conductive mask to sequentially form a first conductive electrode plate, a dielectric layer, and a second conductive electrode plate in the first region and the second region from bottom to top, wherein a vertical projection of the first conductive electrode plate and a vertical projection of the second conductive electrode plate do not completely overlap; All conductive electrode plates in the first region are alternately connected through the first through hole and the second through hole, and all conductive electrode plates in the second region are alternately connected through the third through hole and the fourth through hole, wherein one of the first through hole and the second through hole is in contact with the top metal layer of the basic capacitor structure; and one of the third through hole and the fourth through hole is in contact with the top metal layer of the basic capacitor structure.

2. The method for preparing a high-density linear capacitor according to claim 1, characterized in that: The basic capacitor structure is a MOS capacitor, a MOM capacitor, a MIM capacitor or a PIP capacitor.

3. The method for preparing a high-density linear capacitor according to claim 1, characterized in that: The bottom of the functional column contacts the top metal layer of the basic capacitor structure.

4. The method for preparing a high-density linear capacitor according to claim 1, characterized in that: The material of the functional column is indium or silicon.

5. The method for preparing a high-density linear capacitor according to claim 1, characterized in that: The layout structure of the conductive electrode plate and the dielectric layer in the first region is consistent with the layout structure of the conductive electrode plate and the dielectric layer in the second region.

6. A high-density linear capacitor, prepared by the method for preparing a high-density linear capacitor according to any one of claims 1 to 5, characterized in that: The high-density linear capacitor comprises a basic capacitor structure, a functional column, a first extended capacitor structure and a second extended capacitor structure; the functional column is formed on the top of the basic capacitor structure and divides the top of the basic capacitor structure into a first area and a second area; The first extended capacitor structure is located in the first area and contacts the top of the basic capacitor structure; The second extended capacitor structure is located in the second region and contacts the top of the basic capacitor structure.

7. The high-density linear capacitor according to claim 6, characterized in that: The bottom of the functional column contacts the top metal layer of the basic capacitor structure.

8. The high-density linear capacitor according to claim 6, characterized in that: The first extended capacitor structure and the second extended capacitor structure both include multiple layers of conductive electrode plates and dielectric layers alternately stacked in sequence from bottom to top; all conductive electrode plates of the first extended capacitor structure are alternately connected through the first through hole and the second through hole, and one of the first through hole and the second through hole is in contact with the top metal layer of the basic capacitor structure; all conductive electrode plates of the second extended capacitor structure are alternately connected through the third through hole and the fourth through hole, and one of the third through hole and the fourth through hole is in contact with the top metal layer of the basic capacitor structure.

9. The high-density linear capacitor according to claim 8, characterized in that: The layout structure of the conductive plate and the dielectric layer of the first extended capacitor structure is consistent with the layout structure of the conductive plate and the dielectric layer of the second extended capacitor structure.

10. An image sensor, characterized in that: It comprises a readout circuit, wherein the integral capacitor in the readout circuit is the high-density linear capacitor as described in any one of claims 6 to 9.

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