Optical computing system and chip

Abstract

An optical computing system is applied to the field of optical processing, a first optical processing unit in a first optical processing array of the optical computing system is used for outputting a first optical signal according to first sub-data separated from first data, and the first optical signal indicates a bit of the first data, namely the first sub-data; a second optical processing unit in a second optical processing array of the optical computing system is used for outputting a second optical signal according to the first optical signal and second sub-data separated from the second data, the second sub-data is a bit of the second data, and the second optical signal indicates a product result of the first sub-data and the second sub-data. According to the invention, the power consumption and the device size required by the device can be reduced, and the packaging difficulty is reduced.

Description

An optical computing system and chip Technical Field This application relates to the field of optical computing, and more particularly to an optical computing system and chip. Background Technology With the rapid development of optical integration technology, multiple optical devices can be integrated into a single chip. These devices can then process optical signals to perform mathematical calculations, which is known as optical computation. In recent years, with the increasing demands from scientific research, meteorological and hydrological forecasting, and autonomous driving, and the development of industries such as artificial intelligence, big data, and cloud computing, artificial intelligence (AI) computing has experienced rapid development and widespread application. While advancements in manufacturing processes have significantly improved the power consumption and latency of integrated circuits, the speed at which electrons travel between logic gates still limits the overall computing speed. Furthermore, the power consumption of integrated circuits increases exponentially with the increase in computing speed. Optical computing opens up a different technological path from AI computing, effectively avoiding the aforementioned problems and significantly improving computing speed without relying on advanced processes or drastically increasing power consumption. In the optoelectronic convergence analog computing architecture, to achieve data multiplication, the corresponding data is converted from digital to analog to obtain analog signals, which are then input to the optical modulator in the optical computing system to complete electro-optical conversion. Further multiplication operations are then performed on these data in the optical domain. However, the signals input to the optical computing system are analog signals, that is, multi-level signals with a certain voltage amplitude in the electrical domain, such as 4-level electrical signals. Correspondingly, a modulator that can support multi-level electrical signals is required, and the driving voltage applied to the modulator needs to be increased, resulting in higher power consumption and cost. Summary of the Invention This application provides an optical computing system and chip that can reduce power consumption. In a first aspect, this application provides an optical computing system, wherein a first optical processing array may include a plurality of first optical processing units, wherein the first optical processing units are used to output a first optical signal based on a first sub-data separated from first data, the first optical signal indicating the first sub-data, and the first sub-data being a bit of the first data; a second optical processing unit in a second optical processing array is used to output a second optical signal based on a first optical signal and a second sub-data separated from second data, wherein the second data is carried in an electrical signal, the second sub-data is a bit of the second data, the second optical signal indicating the product of the first sub-data and the second sub-data, and the second optical processing unit is an optical switch. Unlike existing solutions where the electrical signal input to the optical domain is an analog electrical signal indicating the first data, in this embodiment, no digital-to-analog converter is required. Instead, a digital electrical signal indicating the first data is directly input into the optical domain. The first data is binary data and may include multiple first sub-data. Each first sub-data may be a bit of the first data, and each bit may be 0 or 1. In this embodiment, each first optical processing unit only needs to support input of two-level electrical signals and output of two-level optical signals. In this case, on the one hand, the optical modulator requires a lower signal driving voltage (generally, the multi-level driving voltage of analog schemes is as high as several volts, while in this embodiment, achieving two-level electro-optical conversion only requires a few hundred millivolts of driving voltage, necessitating the deployment of an electrical amplifier before the optical modulator; however, this solution eliminates the need for additional components and corresponding power consumption). On the other hand, since the input first data is carried on digital signals through multiple first sub-data, no additional digital-to-analog converters, analog-to-digital converters, or corresponding power consumption are required. Generally, digital-to-analog converters (DACs), electrical amplifiers, and analog-to-digital converters (ADCs) are millimeter-sized devices with watt-level power consumption, and their encapsulation with optical devices increases packaging complexity. The optical devices used in this embodiment are micrometer-sized with milliwatt-level power consumption; therefore, this solution offers significant advantages in both power consumption and size. Using mature processes, such as silicon photonics 130nm technology, monolithic integration of optical devices can be achieved, greatly reducing packaging difficulty. Furthermore, the multi-unit array architecture in this embodiment also has the advantage of scalable precision, that is, by increasing the number of optical processing units, higher precision optical bit operation processing can be achieved. Furthermore, the second sub-data itself is carried in an electrical signal. The multiplication operation between the first and second sub-data in the optical domain is realized by an optical switch. This is equivalent to using an optical switch to realize electro-optic conversion and multiplication operation, without the need for additional devices to realize electro-optic conversion, thereby reducing the number of required devices. It should be understood that the process of separating the first data into sub-data to obtain the first sub-data described above can be implemented by a device with data separation function, or by inputting each bit of the first data into the corresponding first optical processing unit through a preset data path, which is equivalent to achieving data separation. The process of separating the second data into sub-data can be referred to the first data, and the similarities will not be repeated. In one possible implementation, the second optical processing unit is specifically used to: obtain the optical signal corresponding to the second sub-data based on the electrical signal; and perform a product operation of the first sub-data and the second sub-data based on the first optical signal and the optical signal corresponding to the second sub-data to output the second optical signal. It should be understood that there is no requirement for a specific timing between the electro-optical conversion and the product operation. Optionally, the optical switch can perform both functions simultaneously. In one possible implementation, the first optical processing unit is a two-level driven optical device. In this embodiment, each first optical processing unit only needs to be able to support input two-level electrical signals and output two-level optical signals. In this case, the input data is carried on digital signals, eliminating the need for additional digital-to-analog converters, analog-to-digital converters, and corresponding power consumption. In one possible implementation, the second optical processing unit is a two-level driven optical device. In this embodiment, each second optical processing unit only needs to be able to support input two-level electrical signals and output two-level optical signals. In this case, the input data is carried on digital signals, eliminating the need for additional digital-to-analog converters, analog-to-digital converters, and corresponding power consumption. In one possible implementation, the driving voltage of the first optical processing unit is less than 1 kMV, for example, it can be 100 mV, 200 mV, 300 mV, 400 mV, 500 mV, 600 mV, 700 mV, 800 mV, 900 mV, etc. In this embodiment, each first optical processing unit only needs to be able to support input of two-level electrical signals and output of two-level optical signals. In this case, the optical modulator requires a lower signal driving voltage (that is, there is no need to deploy an amplifier before the optical modulator, and thus no need for additional devices and corresponding power consumption). In one possible implementation, the driving voltage of the second optical processing unit is less than 1 kMV, for example, it can be 100 mV, 200 mV, 300 mV, 400 mV, 500 mV, 600 mV, 700 mV, 800 mV, 900 mV, etc. In this embodiment, each second optical processing unit only needs to be able to support input of two-level electrical signals and output of two-level optical signals. In this case, the optical modulator requires a lower signal driving voltage (that is, there is no need to deploy an amplifier before the optical modulator, and thus no additional devices and corresponding power consumption are required). In one possible implementation, when the first data is used as input data, its signal input frequency is relatively high. Therefore, the first optical processing unit needs to support a high signal input frequency (i.e., the maximum signal input frequency, which can be understood as an inherent property of the device). Consequently, the cost of the optical processing unit supporting a higher signal input frequency is also higher. When the second data is coefficient data (weights), its refresh frequency is lower than its calculation frequency. Therefore, the second optical processing unit can be a low-speed device (compared to the first optical processing unit). In other words, the signal input frequency supported by the first optical processing unit can be higher than that supported by the second optical processing unit, thereby reducing the cost of the selected second optical processing unit. In one possible implementation, the second optical processing unit is an optical switch. It should be noted that, in this embodiment, since bit operations are used, the multiplication unit (second optical processing unit) only needs to implement two states, [0] or [1], so an optical switch can be used; while in the prior art, the coefficient multiplication unit needs to implement PAM-N electro-optic modulation, so a modulator is required, and the power consumption and cost of the optical switch are less than those of the modulator. In one possible implementation, the first sub-optical processing units in the first optical processing array are arranged in an ordered manner, and the first sub-data are input into each first sub-optical processing unit in the order of the high-order bits to the low-order bits in the first data. In one possible implementation, the first optical processing unit is specifically configured to output a first optical signal based on first sub-data carried in a digital electrical signal; or, The second optical processing unit is used to output a second optical signal based on a first optical signal and second sub-data carried in a digital electrical signal. In one possible implementation, the first optical processing array includes M first optical processing units, the first data includes M bits, the M first optical processing units are used to output M first optical signals, and the M first optical signals indicate the first data, where M is an integer greater than 1. In one possible implementation, the optical computing system also includes a beam splitter. In one possible implementation, the first optical processing unit is specifically used to output a first optical signal to a beam splitter, which divides the first optical signal into N first optical signals by power, and outputs each of the N first optical signals to a second optical processing unit. The N first optical signals indicate the same first sub-data, where N is an integer greater than 1. In one possible implementation, the beam splitter can be a 1×N power beam splitter. In one possible implementation, the beam splitter can output N first optical signals to a second optical processing array. The second optical processing array can perform product operations between the various first sub-data points of the first data and the various second sub-data points of the second data. In one possible implementation, the second sub-optical processing units in the second optical processing array are arranged in an ordered manner, and the input second sub-data is input into each group of the second sub-optical processing units in the order of the high-order bits to the low-order bits of the second data. In one possible implementation, the second data may include N second sub-data. In order to realize the product operation between each first sub-data of the first data and each second sub-data of the second data, each first optical processing unit may specifically output a first optical signal to a beam splitter. The beam splitter may divide the power of the first optical signal to obtain N first optical signals (for example, the power of the first optical signal may be equally divided into N first optical signals). The N first optical signals indicate the same first sub-data, that is, each of the N first optical signals indicates the same first sub-data. It should be understood that the use of the same name for the optical signals before and after power division in the embodiments of this application does not limit the optical signals before and after power division to be completely identical, but can indicate that the data indicated by the optical signals before and after power division is the same data. In one possible implementation, the second data includes N bits, the second optical processing array includes multiple groups of optical processing units, each group of optical processing units includes N second optical processing units, and the beam splitter is specifically used to output N first optical signals to the same group of optical processing units in the second optical processing array. In one possible implementation, the second optical processing array may include M groups of second optical processing units, each group of second optical processing units may include N second optical processing units, each second optical processing unit may obtain a second optical signal, the second optical signal indicates the product result of the first sub-data and the second sub-data, the second optical processing array may obtain M*N second optical signals, the M*N second optical signals may indicate the product operation result between each first sub-data of the first data and each second sub-data of the second data. In one possible implementation, the second optical processing array is specifically used to output a second optical signal to an optical full adder so that the optical full adder obtains a plurality of third optical signals based on the plurality of second optical signals, each third optical signal indicating a third sub-data in the third data, the third data being the product of the first data and the second data, and the third sub-data being a bit in the third data. In one possible implementation, the optical computing system also includes an optical full adder. It should be understood that the second optical processing array can directly output some data (e.g., the last bit) without passing through the optical full adder, and thus serve as the last bit of the product of the first and second data. In one possible implementation, the optical full adder can also be in the form of an array, specifically including multiple optical full adders, each of which can perform an addition operation on two objects (or may also include the carry result of the previous addition operation). In one possible implementation, the optical full adder can be a nonlinear adder. For example, it could be a photonic crystal structure, a coupling structure based on highly nonlinear materials (e.g., a nonlinear waveguide adder), or others. Nonlinear adders can be implemented with a single structure (a coupling structure excluding sub-units), thereby reducing the number and complexity of devices. In one possible implementation, an optical full adder is used to input multiple third optical signals to a photodetector PD, so that the photodetector PD generates an electrical signal indicating third data based on the multiple third optical signals. In one possible implementation, if the optical processing system described above (including the first optical processing array, the second optical processing array, and the optical full adder) processes multiplication operations involving only two data objects (e.g., 2-bit * 2-bit), or the final product operation involving more than two objects (e.g., 2-bit * 2-bit * 2-bit, where the first multiplication operation yields 4-bit * 2-bit, and 4-bit * 2-bit is the final product operation), the output of the optical full adder (multiple third optical signals) can represent the final result of the multiplication operation, which needs to be transmitted to the electrical domain. Therefore, the output of the optical full adder can be transmitted to the PD, which can generate an electrical signal indicating the third data (or, in other words, perform photoelectric conversion on the multiple third optical signals) based on the multiple third optical signals. In one possible implementation, the third data is binary data, and each third optical signal indicates one bit of the third data; the optical computing system also includes: a third optical processing array, comprising multiple third optical processing units, each third optical processing unit being used to output a fourth optical signal based on a third optical signal and the fourth sub-data in the fourth data, the fourth optical signal indicating the product of the bit indicated by the third optical signal and the fourth sub-data. In one possible implementation, if the optical processing system described above (including the first optical processing array, the second optical processing array, and the optical full adder) is handling a non-final multiplication operation (e.g., 2-bit * 2-bit * 2-bit, where the non-final multiplication operation is the first multiplication operation: 2-bit * 2-bit) involving more than two objects, the output of the optical full adder (multiple third optical signals) can represent the intermediate result of the multiplication operation. This intermediate result needs to be passed to the next-level optical processing array (i.e., the third optical processing array in this embodiment) so that the third optical processing array can perform the next multiplication operation. Therefore, the output of the optical full adder can be passed to the third optical processing array. In one possible implementation, the first optical processing unit is an optical modulator or an optical switch. In one possible implementation, the optical modulator can be a low-drive piezoelectric optical modulator, such as a silicon photonic integrated microring modulator, a Mach-Zehnder modulator, or others. It should be noted that, optionally, the operating frequency of the optical modulator is the same as the calculation frequency. In one possible implementation, the optical switch could be a silicon photonic integrated electro-optic Mach-Zehnder interferometer, a thermo-optic Mach-Zehnder interferometer, or something else. In one possible implementation, each first optical processing unit is specifically used to modulate a first sub-data of the first data onto a laser carrier provided by the light source to output a first optical signal. In one possible implementation, the system also includes a light source. It should be understood that, in one possible implementation, the first data and the second data can be two matrix elements that need to be multiplied in a matrix product (for example, if a product operation of matrix A and matrix B is to be performed, the first data can be an element of matrix A, and the second data can be an element of matrix B). The optical processing system described above (including a first optical processing array, a second optical processing array, and an optical full adder) can perform the product operation between the first data and the second data. The optical processing system can also include multiple subsystems similar to the first optical processing array, the second optical processing array, and the optical full adder. Each subsystem can perform the product operation of two matrix elements that need to be multiplied in a matrix product, and each subsystem can obtain a product result (for example, the subsystem including the first optical processing array, the second optical processing array, and the optical full adder can obtain multiple third optical signals). The optical processing system can also include an optical full adder for summing the product results obtained by each subsystem to obtain the matrix product result. The specific description of each subsystem can refer to the description of the subsystem including the first optical processing array, the second optical processing array, and the optical full adder in the above embodiments, and the similarities will not be repeated. In addition to optoelectronic fusion computing, the embodiments of this application can also be used for direct computation of optical signals, such as in distributed acoustic sensing (DAS) systems or lidar (Light Detection and Ranging) systems. In this application, there is no need for a first optical processing array to perform electro-optical conversion of the input data; the input data is directly an optical signal. Only a second optical processing array is needed to perform coefficient multiplication and an optical full adder to process the input data. Secondly, this application provides an optical computing system, which includes: The second optical processing array includes a second optical processing unit. The second optical processing unit is used to perform a product operation of the first sub-data and the second sub-data separated from the second data according to the first optical signal and the second sub-data, and output a second optical signal. The second sub-data is one bit of the second data, the second data is binary data, the second data is carried in an electrical signal, and the second optical signal indicates the product result of the first sub-data and the second sub-data. The second optical processing unit is an optical switch. In one possible implementation, the second optical processing unit is specifically used for: Based on the electrical signal, the optical signal corresponding to the second sub-data is obtained; Based on the first optical signal and the optical signal corresponding to the second sub-data, perform the product operation of the first sub-data and the second sub-data to output the second optical signal. In one possible implementation, the second optical processing unit is a two-level driven optical device. In one possible implementation, the driving voltage of the second optical processing unit is less than 1 kmV. In one possible implementation, each second optical processing unit is used to output a second optical signal based on the first optical signal and the second sub-data carried in the digital electrical signal. In one possible implementation, the second data includes N bits, the second optical processing array includes multiple sets of optical processing units, each set of optical processing units includes N second optical processing units, the beam splitter is used to divide the power of the first optical signal to obtain N first optical signals (for example, the power of the first optical signal can be equally divided into N first optical signals), and each of the N first optical signals is output to a second optical processing unit, the N first optical signals indicate the same first sub-data, and N is an integer greater than 1. In one possible implementation, the second optical processing array is specifically used to output a second optical signal to an optical full adder so that the optical full adder obtains a plurality of third optical signals based on the plurality of second optical signals, each third optical signal indicating a third sub-data in the third data, the third data being the product of the first data and the second data, and the third sub-data being a bit in the third data. In one possible implementation, the optical computing system also includes an optical full adder. In one possible implementation, an optical full adder is used to input multiple third optical signals to a photodetector PD, so that the photodetector PD generates an electrical signal indicating third data based on the multiple third optical signals. In one possible implementation, the optical full adder is a nonlinear adder. In one possible implementation, the third data is binary data, with each third optical signal indicating one bit of the third data; the optical computing system also includes: The third optical processing array includes multiple third optical processing units. Each third optical processing unit is used to output a fourth optical signal based on a third optical signal and a fourth sub-data in the fourth data. The fourth optical signal indicates the product of a bit indicated by a third optical signal and the fourth sub-data. In one possible implementation, the second optical processing unit is an optical switch. Thirdly, this application provides an optical computing chip, which includes a system as described in any of the first aspects or a system as described in any of the second aspects, an input interface, and an output interface. The input interface is communicatively connected to the processor or memory, and is used to acquire first data and second data sent from the processor or memory; The output interface is communicatively connected to the processor or the memory, and is used to transmit the product result obtained based on the first data and the second data to the processor or the memory. Fourthly, this application provides a computing device, including a processor and an optical computing chip as described in the third aspect; the processor and the optical computing chip are communicatively connected. In one possible implementation, the computing device is a terminal device or a server. Fifthly, this application provides an optical computing method applied to an optical computing system, comprising a first optical processing unit, a second optical processing array including a second optical processing unit; the second optical processing unit being an optical switch; the method comprising: The first optical processing unit outputs a first optical signal based on the first sub-data separated from the first data, wherein the first data is binary data and the first sub-data is one bit of the first data; The second optical processing unit performs a product operation on the first optical signal and the second sub-data separated from the second data, and outputs a second optical signal. The second sub-data is one bit of the second data, the second data is binary data, the second data is carried in an electrical signal, and the second optical signal indicates the product result of the first sub-data and the second sub-data. The second optical processing unit is an optical switch. In one possible implementation, a first optical signal is output based on a first sub-data separated from the first data, including: Based on the first optical signal and the optical signal corresponding to the second sub-data, perform the product operation of the first sub-data and the second sub-data to output the second optical signal. In one possible implementation, the first optical processing unit is a two-level driven optical device. In one possible implementation, the second optical processing unit is a two-level driven optical device. In one possible implementation, the driving voltage of the first optical processing unit is less than 1 kmV. In one possible implementation, the driving voltage of the second optical processing unit is less than 1 kmV. In one possible implementation, the maximum signal input frequency of the first optical processing unit is greater than the maximum signal input frequency of the second optical processing unit. In one possible implementation, a first optical signal is output based on a first sub-data separated from the first data, including: Based on the first sub-data carried in the digital electrical signal, output the first optical signal; or... Based on the first optical signal and the second sub-data separated from the second data, including: The second optical signal is output based on the first optical signal and the second sub-data carried in the digital electrical signal. In one possible implementation, the first optical processing array includes M first optical processing units, the first data includes M bits, the M first optical processing units are used to output M first optical signals, and the M first optical signals indicate the first data, where M is an integer greater than 1. In one possible implementation, the optical computing system also includes a beam splitter. In one possible implementation, the method also includes: Each first optical processing unit outputs a first optical signal to a beam splitter. The beam splitter divides the first optical signal into N first optical signals by power, and outputs each of the N first optical signals to a second optical processing unit. The N first optical signals indicate the same first sub-data, where N is an integer greater than 1. In one possible implementation, the second data includes N bits, the second optical processing array includes multiple sets of optical processing units, each first optical processing unit is specifically used to output a first optical signal to a beam splitter, the beam splitter is used to divide the first optical signal into N first optical signals by power, and output each of the N first optical signals to a second optical processing unit, the N first optical signals indicate the same first sub-data, and N is an integer greater than 1. In one possible implementation, the method further includes: a second optical processing array outputting a second optical signal to an optical full adder, so that the optical full adder obtains a plurality of third optical signals based on the plurality of second optical signals, each third optical signal indicating a third sub-data in the third data, the third data being the product of the first data and the second data, and the third sub-data being a bit in the third data. In one possible implementation, the optical computing system also includes an optical full adder. In one possible implementation, the method further includes: an optical full adder inputting multiple third optical signals to a photodetector PD, so that the photodetector PD generates an electrical signal indicating third data based on the multiple third optical signals. In one possible implementation, the third data is binary data, and each third optical signal indicates one bit of the third data; the optical computing system further includes: a third optical processing array, including multiple third optical processing units; the method further includes: each third optical processing unit outputs a fourth optical signal based on a third optical signal and a fourth sub-data in the fourth data, the fourth optical signal indicating the product of the bit indicated by the third optical signal and the fourth sub-data. In one possible implementation, the first optical processing unit is an optical modulator or an optical switch. In one possible implementation, the method further includes: each first optical processing unit modulating first sub-data of the first data onto a laser carrier provided by the light source to output a first optical signal. Sixthly, this application provides an optical computing method applied to an optical computing system, the optical computing system comprising: a second optical processing array including a plurality of second optical processing units; the method comprising: The second optical processing unit performs a product operation on the first optical signal and the second sub-data separated from the second data, and outputs a second optical signal. The second sub-data is one bit of the second data, the second data is binary data, the second data is carried in an electrical signal, and the second optical signal indicates the product result of the first sub-data and the second sub-data. The second optical processing unit is an optical switch. In one possible implementation, based on the first optical signal and the second sub-data separated from the second data, a product operation of the first sub-data and the second sub-data is performed to output the second optical signal, including: Based on the electrical signal, the optical signal corresponding to the second sub-data is obtained; Based on the first optical signal and the optical signal corresponding to the second sub-data, perform the product operation of the first sub-data and the second sub-data to output the second optical signal. In one possible implementation, the second optical processing unit is a two-level driven optical device. In one possible implementation, the driving voltage of the second optical processing unit is less than 1 kmV. In one possible implementation, the step of using the first optical signal and the second sub-data separated from the second data includes: outputting the second optical signal based on the first optical signal and the second sub-data carried in the digital electrical signal. In one possible implementation, the second data includes N bits, the second optical processing array includes multiple groups of optical processing units, each group of optical processing units includes N second optical processing units, and the method further includes: a beam splitter divides the power of the first optical signal to obtain N first optical signals (for example, the power of the first optical signal can be equally divided into N first optical signals), and outputs each of the N first optical signals to a second optical processing unit, wherein the N first optical signals indicate the same first sub-data, and N is an integer greater than 1. In one possible implementation, the method further includes: a second optical processing array outputting a second optical signal to an optical full adder, so that the optical full adder obtains a plurality of third optical signals based on the plurality of second optical signals, each third optical signal indicating a third sub-data in the third data, the third data being the product of the first data and the second data, and the third sub-data being a bit in the third data. In one possible implementation, the optical computing system also includes an optical full adder. In one possible implementation, the method further includes: an optical full adder inputting multiple third optical signals to a photodetector PD, so that the photodetector PD generates an electrical signal indicating third data based on the multiple third optical signals. In one possible implementation, the optical full adder is a nonlinear adder. In one possible implementation, the third data is binary data, and each third optical signal indicates one bit of the third data; the optical computing system also includes: a third optical processing array, comprising third optical processing units; The method further includes: Each third optical processing unit outputs a fourth optical signal based on a third optical signal and the fourth sub-data in the fourth data. The fourth optical signal indicates the product of the bit indicated by the third optical signal and the fourth sub-data. In one possible implementation, the second optical processing unit is an optical switch. In a seventh aspect, this application also provides a computer program product, including program code, the instructions of which are executed by a computer to implement the optical computing method in the fifth aspect and any possible implementation thereof, or the optical computing method in the sixth aspect and any possible implementation thereof. Eighthly, this application also provides a computer-readable storage medium for storing program code, the program code including instructions that are executed by a computer to implement the optical computing method in the fifth aspect and any possible implementation of the fifth aspect, or the optical computing method in the sixth aspect and any possible implementation of the sixth aspect. Attached Figure Description Figure 1 illustrates an architecture provided in this application; Figure 2 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 3 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 4 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 5 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 6 is a schematic diagram of a product operation provided in this application; Figure 7 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 8 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 9 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 10 illustrates the effect provided by this application; Figure 11 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 12 illustrates a product operation provided by this application; Figure 13 illustrates the effect provided by this application; Figure 14 is a schematic diagram of the architecture of an optical processing system provided in this application; Figure 15 is a schematic diagram of the architecture of an optical processing device provided in this application; Figure 16 is a schematic diagram of the architecture of an execution device provided in this application; Figure 17 is a schematic diagram of a server architecture provided in this application; Figure 18 is a schematic diagram of the chip architecture provided in this application. Detailed Implementation The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention. The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems. The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly located on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intermediate elements or layers. It should also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intermediate elements or layers. The terms “substantially,” “about,” and similar terms used herein are used as approximations, not as terms of degree, and are intended to take into account the inherent biases of measurements or calculations known to those skilled in the art. Furthermore, the use of “may” when illustrating embodiments of the invention concept means “one or more possible embodiments.” The terms “use,” “using,” and “used” used herein are to be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Additionally, the term “exemplary” is intended to refer to an instance or illustration. Artificial neural networks (ANNs), also known simply as neural networks (NNs) or neural network-like systems, are mathematical or computational models in machine learning and cognitive science that mimic the structure and function of biological neural networks (the central nervous system of animals, especially the brain) to estimate or approximate functions. Artificial neural networks can include convolutional neural networks (CNNs), deep neural networks (DNNs), and multilayer perceptrons (MLPs), among others. The algorithms of neural network systems are complex and computationally intensive, placing high demands on computational efficiency. To improve computational efficiency, optical computing, which utilizes the physical properties of optical devices to perform the corresponding mathematical operations, has been applied. First, let's introduce the application scenarios of this application: Due to the increasing volume of internet data and the rapid development of the AI ​​field, deep learning (DL) has been widely applied in areas such as image recognition, speech recognition, and natural language processing. Deep learning is a neural network designed to mimic the structure of the human brain, achieving better recognition results than traditional shallow learning methods. Because deep learning algorithms are complex and computationally intensive, traditional central processing units (CPUs) are inefficient at handling large-scale computations, making hardware research for AI acceleration a hot research topic. Compared to traditional microelectronic chips, optical computing offers significant performance improvements in certain applications. In one possible implementation, this application can be applied to AI-related computing scenarios, such as image-related AI operations, audio-related AI operations, video-related AI operations, text-related AI operations, and so on. More specifically, it can be applied to product operations in AI computing, such as the product operation between input data and coefficient data (exemplarily, it can also be called weights). In one possible implementation, this application can be applied to a system for the optoelectronic fusion computing of AI. Referring to Figure 1, which is a schematic diagram of the application system according to an embodiment of this application, the system may include an electrical domain and an optical domain. The electrical domain may include a processor (e.g., CPU, GPU, TPU, etc.) for performing AI calculations and a memory (e.g., RAM). The processor can perform instruction control, and the memory can be used to store data. The processor can load the data in the memory (e.g., input data and coefficient data) into the optical domain in the form of electrical signals. The optical processor system (e.g., optical modulator, etc.) in the optical domain performs calculations on the data in the dimension of the optical signal (e.g., product operation in the embodiment of this application), converts the calculation result into an electrical signal, and sends it back to the electrical domain. On the one hand, during the calculation in the optical domain, photons propagate at the speed of light, which is one to two orders of magnitude higher than that of electrons, and the power consumption of optical devices in the optical domain is only proportional to the clock frequency (while the power consumption of electrical devices in microelectronic chips is proportional to the cube of the clock frequency). The performance of optical devices does not depend on the manufacturing process. In addition, as bosons, photons, unlike electrons, are not limited by the Pauli exclusion principle and can be reused in multiple dimensions such as wavelength and polarization, which can further improve the overall computing speed. To facilitate understanding, the relevant terms involved in the embodiments of this application will be introduced below. (1) Digital-to-analog converter (DAC) Generally referring to a digital-to-analog converter, also known as a D / A converter or DAC for short, it is a device that converts digital signals into analog signals. A D / A converter basically consists of four parts: a weighted resistor network, an operational amplifier, a reference power supply, and analog switches. (2) Analog-to-digital converter (ADC) Generally refers to an analog-to-digital converter, also known as an A / D converter or simply ADC, which is usually a device that converts analog signals into digital signals. (3) Optical modulator Optical modulation is a modulation technique that superimposes an electrical signal carrying information onto a carrier light wave. Optical modulation can cause certain parameters of a light wave, such as amplitude, frequency, phase, polarization state, and duration, to change according to certain rules. The device that realizes optical modulation is called an optical modulator. (4) Optical switch An optical switch is an optical device with one or more optional transmission ports, which is used to physically switch or logically operate optical signals in optical transmission lines or integrated optical circuits. (5) Power beam splitter A beam splitter (or power divider) is an optical device that splits an incident beam of light (e.g., a laser beam) into two or more beams that may not have the same power. (6)Precision Precision can be expressed as the number of bits contained in binary data. For example, the precision of binary data 1011 can be 4. In existing implementations, the electrical domain section includes: a processor for instruction control, a memory for storing data, and a driver circuit. The digital-to-analog converter (DAC) in the driver circuit reads data from the memory (for example, the data can be input data and coefficient data), performs digital-to-analog conversion to obtain the corresponding electrical signals, and loads them onto the modulator and coefficient multiplication unit, respectively. For high-speed modulation, the driving voltage output by the DAC is only on the order of hundreds of millivolts, which cannot effectively drive the modulator to achieve electro-optical conversion. An amplifier is needed after the DAC to boost the driving voltage to the order of volts. The analog-to-digital converter (ADC) in the driver circuit can perform analog-to-digital conversion on the data output from the optical domain to the electrical domain and then feed the output data back to the memory or processor. The optical domain portion may include: a light source (e.g., a laser for generating a specific wavelength), a modulator, a coefficient multiplication unit, and a photodetector (PD). The modulator modulates the input data (carried on an analog electrical signal) onto the laser carrier to form optical signal input data. The coefficient multiplication unit converts the coefficient data (carried on an analog electrical signal) into optical signal coefficient data and performs a multiplication operation with the optical signal input data in the optical domain to form optical signal output data. The photodetector can perform photoelectric conversion on the optical signal output data to form optical domain output data (i.e., electrical signal output data). In the existing technology, the input data, coefficient data and output data are all analog electrical signals, that is, multi-level signals with a certain voltage amplitude in the electrical domain, such as 4-level electrical signals. Therefore, a modulator that can modulate multi-level electrical signals is required, which means that the signal driving voltage applied to the modulator needs to be increased, which will bring additional power consumption and cost. Furthermore, existing solutions require a DAC to read data and perform digital-to-analog conversion. For high-speed modulation, the DAC output drive voltage is only on the order of hundreds of millivolts, which is insufficient to effectively drive the modulator to achieve electro-optical conversion. An amplifier is needed after the DAC to boost the drive voltage to the volt level. Existing technologies rely on DACs and amplifiers, resulting in high power consumption, high cost, and large device size, leading to low integration. At the same time, high-precision DACs also heavily rely on advanced manufacturing processes for very large scale integration (VLSI) circuits. Furthermore, existing solutions also require ADCs for analog-to-digital conversion, and their accuracy requirements are higher than those of DACs. For example, multiplying two 4-bit signals results in an 8-bit output signal; if addition is also involved, the output signal accuracy is even higher. Therefore, while the accuracy requirement for a DAC is 4 bits, the accuracy requirement for an ADC is 8 bits or even higher. High-precision ADCs also suffer from high power consumption, high cost, and low integration, and are more dependent on advanced VLSI circuit manufacturing processes. In summary, existing solutions suffer from drawbacks such as limited computational accuracy, high power consumption, low integration, and dependence on advanced manufacturing processes. To address the aforementioned issues, please refer to Figure 2, which is a schematic diagram of the architecture of an optical computing system provided in an embodiment of this application. In one possible implementation, the optical computing system may include a light source 201, which may be a laser 2011 for providing a laser carrier. For example, referring to FIG3, the input light source 201 may employ one laser 2011 to provide laser light, which may be transmitted to a 1×M power beam splitter 2012 to obtain M lasers (for example, the M lasers are lasers of the same wavelength); for example, referring to FIG4, the input light source 201 may employ M lasers 2011 to provide M lasers (one laser 2011 provides one laser, for example, the M lasers are lasers of the same wavelength). In one possible implementation, the laser carrier provided by the light source 201 can be a continuous wave (CW) laser, such as a single-wavelength CW laser. Optionally, the light source 201 can be a III / V integrated distributed feed back (DFB) laser 2011 or others; the 1×M power beam splitter 2012 can be a 1×M multimode interferometer, or a log2(M) level 1×2 beam splitter cascade or others, which are not limited in this application. In one possible implementation, the optical computing system may include a first optical processing array 202, which can load (exemplarily, the loading can specifically be modulation) data indicated by an electrical signal from the electrical domain onto a laser carrier provided by the light source 201. The optical computing system can perform a product operation, which can be the product of data A and data B. In the context of AI computation, data A can be input data, data B can be coefficient data (or weights), and the data indicated by the electrical signal can be the aforementioned data A. That is, the first optical processing array 202 can load data A indicated by an electrical signal from the electrical domain onto the laser carrier provided by the light source 201. The following explanation uses data A as the first data point: In one possible implementation, the optical computing system may include a first optical processing array 202, which can load first data from the electrical domain into a laser carrier provided by the light source 201. Unlike existing solutions where the electrical signal input into the optical domain is an analog electrical signal indicating the first data, in this embodiment, no digital-to-analog converter is required. Instead, a digital electrical signal indicating the first data is directly input into the optical domain. The first data is binary data and may include multiple first sub-data. Each first sub-data may be a bit of the first data, and each bit may be 0 or 1. For example, the first data could be 1101 (corresponding to decimal 13), which could include 4 bits: "1", "1", "0", and "1". Each bit of data (i.e., the first sub-data) can be input to a first optical processing unit 2021 in the first optical processing array 202. In existing implementations, 1101 is input to the optical modulator in the optical domain in the form of an analog signal. Since 1101 is 4-bit data with a precision of 4 bits, the optical modulator needs to support 4-bit precision modulation capability, that is, be able to support input 2... 4 That is, 16 levels of electrical signals, and output 2 4 (That is, 16) levels of optical signal. In this case, on the one hand, the optical modulation itself requires high power consumption, and on the other hand, the optical modulator requires high signal drive voltage (that is, an amplifier needs to be deployed before the optical modulator, which in turn requires additional devices and corresponding power consumption). In this embodiment of the application, referring to FIG5, the first optical processing array 202 may include a plurality of first optical processing units 2021. Each first optical processing unit 2021 is configured to output a first optical signal based on a first sub-data of the first data, wherein the first optical signal indicates the first sub-data. That is, each first optical processing unit 2021 may load the first sub-data of the first data into an optical signal (exemplarily, this may be referred to as electro-optic conversion of the first sub-data) to obtain the first optical signal. In other words, each first optical processing unit 2021 only needs to support input of two-level electrical signals and output of two-level optical signals. In this case, on the one hand, the optical modulator requires a lower signal driving voltage (generally, the multi-level driving voltage of analog schemes is as high as several volts, while in this embodiment, the two-level electro-optical conversion only requires a driving voltage of hundreds of millivolts, requiring the deployment of an electrical amplifier before the optical modulator, while this solution does not require additional devices and corresponding power consumption). On the other hand, since the input first data is carried on digital signals through multiple first sub-data, no additional digital-to-analog converters, analog-to-digital converters, and corresponding power consumption are required. Generally speaking, DACs, amplifiers, and ADCs are millimeter-sized devices with power consumption in the watt range, and their encapsulation with optical devices increases packaging complexity. The optical devices used in this embodiment are in the micrometer range with power consumption in the milliwatt range, so this solution has significant advantages in terms of power consumption and size. Using mature processes, such as silicon photonics 130nm process, monolithic integration of optical devices can be achieved, which also greatly reduces packaging difficulty. Furthermore, the multi-unit array architecture in this embodiment also has the advantage of scalable precision, that is, by increasing the number of optical processing units, higher precision optical bit operation processing can be achieved. In one possible implementation, referring to FIG5, the first optical processing array 202 may include M first sub-optical processing units, and the light source 201 may provide M laser carriers, wherein each laser carrier may be input into a first optical processing unit 2021, and each first optical processing unit 2021 may load a first sub-data of the first data into the corresponding laser carrier to obtain a first optical signal. Thus, the first optical processing array 202 may obtain M first optical signals, and the M first optical signals may indicate the first data. For example, the first optical processing array 202 may include four first optical processing units (exemplarily, it may include first optical processing unit 1, first optical processing unit 2, first optical processing unit 3, and first optical processing unit 4). The first data may be 1101. Then, bit "1" can be input to first optical processing unit 1, bit "1" can be input to first optical processing unit 2, bit "0" can be input to first optical processing unit 3, and bit "1" can be input to first optical processing unit 4. First optical processing unit 1 can load bit "1" into the input optical signal to obtain first optical signal 1 (indicating "1"). First optical processing unit 2 can load bit "1" into the input optical signal to obtain first optical signal 2 (indicating "1"). First optical processing unit 3 can load bit "0" into the input optical signal to obtain first optical signal 3 (indicating "0"). First optical processing unit 4 can load bit "1" into the input optical signal to obtain first optical signal 4 (indicating "1"). In one possible implementation, the first sub-optical processing units in the first optical processing array 202 are arranged in an ordered manner, and the input first sub-data is input into each first sub-optical processing unit in the order of the most significant bit to the least significant bit in the first data. For example, the first optical processing array 202 may include a first optical processing unit 1, a first optical processing unit 2, a first optical processing unit 3, and a first optical processing unit 4. The first optical processing unit 1 is configured to process the most significant bit in the input data, the first optical processing unit 2 is configured to process the second most significant bit in the input data, the first optical processing unit 3 is configured to process the third most significant bit in the input data, and the first optical processing unit 4 is configured to process the fourth most significant bit in the input data. In one possible implementation, the first optical processing unit 2021 can be an optical modulator or an optical switch. In one possible implementation, the first optical processing unit 2021 is a two-level driven optical device. In this embodiment, each first optical processing unit 2021 only needs to be able to support input of two-level electrical signals and output of two-level optical signals. In this case, on the one hand, the power consumption required for optical modulation itself is low, and on the other hand, there is no need for a DAC to perform digital-to-analog conversion, which greatly saves power consumption, size, and packaging difficulty. In one possible implementation, the driving voltage of the first optical processing unit 2021 is less than 1 kMV, for example, it can be 100 mV, 200 mV, 300 mV, 400 mV, 500 mV, 600 mV, 700 mV, 800 mV, 900 mV, etc. In this embodiment, each first optical processing unit 2021 only needs to be able to support input of two-level electrical signals and output of two-level optical signals. In this case, the optical modulator requires a lower signal driving voltage (that is, there is no need to deploy an amplifier before the optical modulator, and thus no additional devices and corresponding power consumption are required). In one possible implementation, the optical modulator can be a low-drive piezoelectric optical modulator, such as a silicon photonic integrated microring modulator, a Mach-Zehnder modulator, or others. It should be noted that, optionally, the operating frequency of the optical modulator is the same as the calculation frequency. For example, to record and modulate the intensity of incident light, the modulator can be implemented using structures based on different principles, such as doped silicon waveguides, electro-absorption modulators, and semiconductor optical amplifiers (SOAs). For instance, when using an SOA as a modulator, the intensity of the incident light can be recorded by detecting the magnitude of the incident photocurrent. Furthermore, the intensity of the light signal passing through the SOA can be changed by altering the light transmittance. In practical applications, the SOA can be fabricated using semiconductor quantum well materials. Since different voltages can cause different changes in the transmittance of the SOA, the transmittance of the SOA can be varied between 0 and 1 by voltage control. Specifically, when the voltage passing through the SOA is reverse-biased, the incident light will generate a photocurrent in the SOA, and the intensity distribution can be obtained by detecting the magnitude of the photocurrent. To perform a product operation between binary data, it is necessary to perform a product operation between each bit of the object of the product operation (the first data and the second data) (specifically, between each first sub-data of the first data and each second sub-data of the second data), and then perform an addition operation between the results of the product operation, as shown in Figure 6. In one possible implementation, the second data carried in the electrical signal may include N second sub-data. In order to realize the product operation between each first sub-data of the first data and each second sub-data of the second data, each first optical processing unit 2021 may specifically output a first optical signal to a beam splitter 204. The beam splitter 204 may divide the power of the first optical signal to obtain N first optical signals (for example, the power of the first optical signal may be equally divided into N first optical signals). The N first optical signals indicate the same first sub-data, that is, each of the N first optical signals indicates the same first sub-data. The second sub-data is carried in an electrical signal. The multiplication of the first and second sub-data in the optical domain is achieved by an optical switch. This is equivalent to using an optical switch to realize electro-optical conversion and multiplication, without the need for additional devices to achieve electro-optical conversion, thereby reducing the number of required devices. For example, the first optical processing array 202 may include four first optical processing units (for example, it may include first optical processing unit 1, first optical processing unit 2, first optical processing unit 3, and first optical processing unit 4). The first data can be 1101, and the second data can be 1011. Then, bit "1" can be input to first optical processing unit 1, bit "1" can be input to first optical processing unit 2, bit "0" can be input to first optical processing unit 3, and bit "1" can be input to first optical processing unit 4. First optical processing unit 1 can load bit "1" into the input optical signal to obtain first optical signal 1 (indicating "1"). First optical processing unit 2 can load bit "1" into the input optical signal to obtain first optical signal 2 (indicating "1"). First optical processing unit 3 can load bit "0" into the input optical signal to obtain first optical signal 3 (indicating "0"). First optical processing unit 4 can load bit "1" into the input optical signal to obtain first optical signal 4 (indicating "1"). Beam splitter 204 may include beam splitter 1, beam splitter 2, beam splitter 3 and beam splitter 4. First optical processing unit 1 can input first optical signal 1 (indicating "1") into beam splitter 1 to obtain 4 first optical signals 1 (indicating "1"). First optical processing unit 2 can input first optical signal 2 (indicating "1") into beam splitter 2 to obtain 4 first optical signals 2 (indicating "1"). First optical processing unit 3 can input first optical signal 3 (indicating "0") into beam splitter 3 to obtain 4 first optical signals 3 (indicating "0"). First optical processing unit 4 can input first optical signal 4 (indicating "1") into beam splitter 4 to obtain 4 first optical signals 4 (indicating "4"). In one possible implementation, beam splitter 204 can be a 1×N power beam splitter. In one possible implementation, the beam splitter 204 can output the N first optical signals to the second optical processing array 203. The second optical processing array 203 can perform product operations between the various first sub-data of the first data and the various second sub-data of the second data. In one possible implementation, the second optical processing array 203 may include a plurality of second optical processing units 2031. Each second optical processing unit 2031 may perform a product operation between a set of first sub-data and second sub-data. For example, the first data may include M first sub-data and the second data may include N second sub-data. In this case, a total of N*M sets of first sub-data and second sub-data need to be multiplied, which means N*M second sub-optical processing units are required. In one possible implementation, referring to Figure 7, the second data includes the N bits, the second optical processing array 203 includes M groups of optical processing units, each group of optical processing units includes the N second optical processing units 2031, and the beam splitter is used to input the N first optical signals to the same group of optical processing units in the second optical processing array 203. That is, each group of optical processing units can process the product operation of the same first sub-data and each of the second sub-data. In one possible implementation, each of the second optical processing units 2031 can output a second optical signal based on a first optical signal and a second sub-data in the second data, wherein the second data is binary data, the second sub-data is a bit of the second data, and the second optical signal indicates the product of the first sub-data and the second sub-data. In other words, each second optical processing unit 2031 only needs to be able to support the input of two 2-level electrical signals and output the product result of the two optical signals indicating the data (the product result is represented by a 2-level optical signal). In this case, on the one hand, the optical modulator requires a low signal driving voltage (generally, the multi-level driving voltage of analog schemes is as high as several volts, while the implementation of 2-level electro-optic conversion in this application embodiment only requires a hundred millivolt driving voltage, and an electrical amplifier needs to be deployed before the optical modulator, while this scheme does not require additional devices and corresponding power consumption). On the other hand, since the input first data is carried on digital signals through multiple first sub-data, no additional digital-to-analog converter, analog-to-digital converter and corresponding power consumption are required. In one possible implementation, the second optical processing array 203 may include M groups of second optical processing units 2031, each group of second optical processing units 2031 may include N second optical processing units 2031, each second optical processing unit 2031 may obtain a second optical signal, the second optical signal indicates the product result of the first sub-data and the second sub-data, the first optical processing array 202 may obtain M*N second optical signals, the M*N second optical signals may indicate the product operation result between each first sub-data of the first data and each second sub-data of the second data. For example, the first optical processing array 202 may include four first optical processing units (exemplarily, it may include first optical processing unit 1, first optical processing unit 2, first optical processing unit 3, and first optical processing unit 4), and the second optical processing array 203 may include 16 second optical processing units (exemplarily, it may include second optical processing unit 1, second optical processing unit 2, second optical processing unit 3, second optical processing unit 4, second optical processing unit 5, second optical processing unit 6, second optical processing unit 7, second optical processing unit 8, second optical processing unit 9, second optical processing unit 10, and second optical processing unit 11). The system comprises optical processing unit 11, second optical processing unit 12, second optical processing unit 13, second optical processing unit 14, second optical processing unit 15, and second optical processing unit 16. The first data can be 1101, and the second data can be 1011. Therefore, the first optical signal 1 (indicator "1") can be divided into four first optical signals 1 (indicator "1"). Each first optical signal 1 (indicator "1") can be input into a group of second optical processing units (second optical processing unit 1, second optical processing unit 2, second optical processing unit 3, and second optical processing unit 4). The bit "1" in the second data can be input into the second optical processing unit. In the second optical processing unit 1, a bit "0" in the second data can be input to the second optical processing unit 2, a bit "1" in the second data can be input to the second optical processing unit 3, and a bit "1" in the second data can be input to the second optical processing unit 4. The second optical processing unit 1 can obtain the second optical signal 1 (indicating "1") based on the first optical signal 1 (indicating "1") and the bit "1" in the second data. The second optical processing unit 2 can obtain the second optical signal 2 (indicating "0") based on the first optical signal 2 (indicating "1") and the bit "0" in the second data. 3 can obtain the second optical signal 3 (indicating "0") based on the first optical signal 3 (indicating "0") and the bit "1" in the second data. The second optical processing unit 4 can obtain the second optical signal 4 (indicating "1") based on the first optical signal 4 (indicating "1") and the bit "1" in the second data. And so on, the second optical signals 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16 can be obtained. In one possible implementation, each second sub-data in the second data can be simultaneously loaded into the second optical processing units -1 / 2... / N-1, 1 / 2... / N-2, ..., 1 / 2... / NN, from most significant bit to least significant bit. That is, the most significant bit of the electrical signal coefficient data is loaded into the second optical processing units -1-1, -2-1, ..., -N-1, and the least significant bit is loaded into the second optical processing units -1-N, -2-N, ..., and the optical switch-NN. Through this process, the multiplication of each corresponding bit between the input data (first data) and the coefficient data (second data) is achieved. In one possible implementation, the second sub-optical processing units in the second optical processing array 203 are arranged in an ordered manner, and the input second sub-data is input into each group of the second sub-optical processing units in the order of the high-order bits to the low-order bits of the second data. In one possible implementation, the second optical processing unit 2031 is an optical switch. It should be noted that, since the present invention uses bit operations, the multiplication unit only needs to implement two states, [0] or [1], so an optical switch can be used; while in the prior art, the coefficient multiplication unit needs to implement PAM-N electro-optic modulation, so a modulator is required. The power consumption and cost of the optical switch are less than those of the PAM-N modulator. Furthermore, the second sub-data itself is carried in an electrical signal. The multiplication operation between the first and second sub-data in the optical domain is realized by an optical switch. This is equivalent to using an optical switch to realize electro-optic conversion and multiplication operation, without the need for additional devices to realize electro-optic conversion, thereby reducing the number of required devices. In one possible implementation, the second optical processing unit 2031 is a two-level driven optical device. In this embodiment, each second optical processing unit 2031 only needs to be able to support input of two-level electrical signals and output of two-level optical signals. In this case, on the one hand, the power consumption required for optical modulation itself is low, and on the other hand, there is no need for a DAC to perform digital-to-analog conversion, which greatly saves power consumption, size, and packaging difficulty. In one possible implementation, the driving voltage of the second optical processing unit 2031 is less than 1 kMV, for example, it can be 100 mV, 200 mV, 300 mV, 400 mV, 500 mV, 600 mV, 700 mV, 800 mV, 900 mV, etc. In this embodiment, each second optical processing unit 2031 only needs to be able to support input of two-level electrical signals and output of two-level optical signals. In this case, the optical modulator requires a lower signal driving voltage (that is, there is no need to deploy an amplifier before the optical modulator, and thus no additional devices and corresponding power consumption are required). In one possible implementation, the optical switch could be a silicon photonic integrated electro-optic Mach-Zehnder interferometer, a thermo-optic Mach-Zehnder interferometer, or something else. In one possible implementation, when the second data is coefficient data (weights), the signal input frequency supported by the first optical processing unit 2021 can be greater than the signal input frequency supported by the second optical processing unit 2031. It should be noted that, generally, the refresh frequency of the second data is lower than the calculation frequency; therefore, the second optical processing unit 2031 can be equipped with low-speed devices (compared to the first optical processing unit 2021), thereby reducing the power consumption of the second optical processing unit 2031. To perform a product operation between binary data, it is necessary to perform a product operation between each bit of the objects of the product operation (first data and second data) (specifically between each first sub-data of the first data and each second sub-data of the second data), and then perform an addition operation between the results of the product operation, as shown in Figure 6. In one possible implementation, the second optical processing array 203 is specifically used to output the second optical signal to an optical full adder 205, so that the optical full adder 205 obtains a plurality of third optical signals based on the plurality of second optical signals. Each third optical signal indicates a third sub-data in the third data, wherein the third data is the product of the first data and the second data, and the third sub-data is a bit in the third data. In one possible implementation, the optical full adder 205 can perform pairwise addition and carry on each bit of the multiplication operation to complete the output of each bit of the optical signal output data. It should be understood that the second optical processing array 203 can directly output some data (e.g., the last bit) without passing through the optical full adder 205, and thus use it as the last bit of the product of the first data and the second data. In one possible implementation, the optical full adder 205 can also be in the form of an array, specifically including multiple optical full adders 205, each optical full adder 205 can perform an addition operation on two objects (or may also include the carry result of the previous addition operation). In one possible implementation, the optical full adder 205 (e.g., the optical full adder 205 in the embodiments of this application may be a photonic crystal structure, a coupling structure based on highly nonlinear materials, or others) may be a photonic crystal structure, a coupling structure based on highly nonlinear materials, or others. In one possible implementation, if the optical processing system described above (including the first optical processing array 202, the second optical processing array 203, and the optical full adder 205) processes multiplication operations involving only two data objects (e.g., 2-bit * 2-bit), or the last product operation involving more than two object multiplication operations (e.g., 2-bit * 2-bit * 2-bit, where the first multiplication operation yields 4-bit * 2-bit, and 4-bit * 2-bit is the last product operation), the output of the optical full adder 205 (multiple third optical signals) can represent the final result of the multiplication operation, which needs to be transmitted to the electrical domain. Therefore, the output of the optical full adder 205 can be transmitted to the PD, which can generate an electrical signal indicating the third data (or, in other words, perform photoelectric conversion on the multiple third optical signals) based on the multiple third optical signals. In one possible implementation, referring to Figure 8, the PD can be in the form of an array. The PD can include multiple PD units, and each PD unit can perform photoelectric conversion on one of the multiple third optical signals to generate an electrical signal of a third sub-data (that is, the electrical signal of the third data). In one possible implementation, the PD can output an electrical signal of third data to an electrical domain (e.g., a memory or processor). In one possible implementation, the PD can be a germanium and silicon integrated waveguide photodetector or something else, which is not limited by the embodiments of this application. In one possible implementation, if the optical processing system described above (including the first optical processing array 202, the second optical processing array 203, and the optical full adder 205) is handling a non-final multiplication operation (e.g., 2-bit * 2-bit * 2-bit, where the non-final multiplication operation is the first multiplication operation: 2-bit * 2-bit) involving more than two objects, the output of the optical full adder 205 (multiple third optical signals) can represent the intermediate result of the multiplication operation. This intermediate result needs to be passed to the next-level optical processing array (i.e., the third optical processing array in this embodiment) so that the third optical processing array can perform the next multiplication operation. Therefore, the output of the optical full adder 205 can be passed to the third optical processing array. In one possible implementation, the third data is binary data, and each of the third optical signals indicates a bit of the third data; the third optical processing array includes a plurality of third optical processing units, each of the third optical processing units being configured to output a fourth optical signal based on a third optical signal and a fourth sub-data in the fourth data, the fourth optical signal indicating the product of the bit indicated by the third optical signal and the fourth sub-data. For a detailed description of the third optical processing array, please refer to the description of the third optical processing array in the above embodiments; similarities will not be repeated here. It should be understood that, in one possible implementation, the first data and the second data can be two matrix elements that need to be multiplied in a matrix product (for example, if a product operation of matrix A and matrix B is to be performed, the first data can be an element of matrix A, and the second data can be an element of matrix B). The optical processing system described above (including the first optical processing array 202, the second optical processing array 203, and the optical full adder 205) can perform the product operation between the first data and the second data. The optical processing system can also include multiple subsystems similar to the first optical processing array 202, the second optical processing array 203, and the optical full adder 205. Each subsystem can perform the product operation of two matrix elements that need to be multiplied in a matrix product, and each subsystem can obtain a product result (for example, the subsystem including the first optical processing array 202, the second optical processing array 203, and the optical full adder 205 can obtain multiple third optical signals). The optical processing system can also include an optical full adder 205 for summing the product results obtained by each subsystem to obtain the matrix product result. The specific descriptions of each subsystem can be found in the descriptions of the subsystems including the first optical processing array 202, the second optical processing array 203, and the optical full adder 205 in the above embodiments. The similarities will not be repeated here. The following sections will use three specific examples to illustrate product operations involving only two data objects (elements), product operations involving only three data objects (elements), and product operations involving matrices: I. Includes only product operations between two data objects (elements): Referring to Figure 9, the example shown in Figure 9 is 13 × 11 = 143, and the corresponding principle is shown in Figure 6. The single-wavelength CW laser power of laser 2011 is evenly distributed into 4 inputs to 4 modulators. The input data is 13, that is...

[1101] The high-order bits are loaded onto four modulators respectively, i.e., the highest bit [1] is loaded onto modulator-1, the second bit [1] is loaded onto modulator-2, the third bit [0] is loaded onto modulator-3, and the lowest bit [1] is loaded onto modulator-4. After being modulated by four electro-optic modulators, the optical signals are also [1], [1], [0], [1] respectively from the high-order bits to the low-order bits, and each optical signal is evenly distributed in power and loaded onto four optical switches. The coefficient data is 11, i.e.

[1011] , so each group of four optical switches is loaded with the high-order bits of the coefficients from the low-order bits respectively, i.e., the highest bit [1] is loaded onto optical switches-1, 5, 9, 13, the second bit [0] is loaded onto optical switches-2, 6, 10, 14, the third bit [1] is loaded onto optical switches-3, 7, 11, 15, and the lowest bit [1] is loaded onto optical switches-4, 8, 12, 16. The above structure implements the multiplication of each bit of the 4-bit input data with each bit of the 4-bit coefficient data. The multiplication result is output as the light signal intensity after each optical switch. The corresponding bit results after multiplication need to be calculated by optical domain addition. For example, optical switch-16 outputs the result of multiplying the least significant bit of the input data with the least significant bit of the coefficient data, which is directly converted by the PD and used as the least significant bit of the output data. Optical switch-15 outputs the result of multiplying the least significant bit of the input data with the third bit of the coefficient data, and optical switch-12 outputs the result of multiplying the third bit of the input data with the least significant bit of the coefficient data. These two are used as corresponding bits and added by optical full adder-12. The added result is converted by the PD and used as the seventh bit of the output data. The carry result is output to the next layer optical full adder. Similarly, optical switch-14 outputs the result of multiplying the least significant bit of the input data with the second significant bit of the coefficient data; optical switch-11 outputs the result of multiplying the third significant bit of the input data with the third significant bit of the coefficient data; and optical switch-8 outputs the result of multiplying the second significant bit of the input data with the least significant bit of the coefficient data. These three results, as corresponding bits, need to be added together, and also added to the carry from the previous optical full adder-12. Since the optical full adder adds two inputs and one carry, two full adders are needed to perform the above addition function. That is, optical full adder-11 performs the addition of the results from optical switches-14 and 11 and the carry from optical full adder-12. The addition result is output to optical full adder-10, which is then added to the result from optical switch-8. After photoelectric modulation by the PD, it becomes the sixth bit of the output data. The carry from both optical full adder-11 and optical full adder-10 is output to the next layer of optical full adder. Following this pattern, the corresponding bits after each multiplication operation are added using an optical full adder array, resulting in a total of 8 outputs. These results are then converted into photoelectric values ​​by a PD and output. The final output data is [10001111], which is 143. In the example above, N=4, so the structure has a total of 4 modulators, 16 optical switches, 12 optical full adders and 8 PDs. The above example achieves 4-bit all-optical digital computing, realizing digital output through digital input and digital computation, without requiring a 4-bit DAC, RF amplifier, or 8-bit ADC. The optical devices used are all low-drive-voltage, low-power devices. Compared to existing technologies, namely optoelectronic fusion analog computing schemes, the most outstanding effect is the realization of 4-bit computing, which is impossible with existing solutions. Furthermore, it also offers the advantages of low power consumption, high integration, and independence from advanced manufacturing processes. Although the number of devices used in this example is greater than that in existing technologies, the overall power consumption is about 1 / 10 of that in existing technologies. The specific analysis is shown in Table 1. The power consumption comparison here is estimated based on a computing rate of 50Gb / s. The specific evaluation method is as follows: Currently, there is no 4-bit high-speed DAC and RF driver, so the power consumption here is estimated to be twice that of a 4-channel 2-bit high-speed DAC and RF driver; the power consumption for input data reading is estimated based on a computing rate of 50Gb / s, and the power consumption for coefficient data reading is estimated based on a coefficient refresh rate of 1Gb / s; the power consumption of the input modulator is estimated based on the sum of the dynamic power consumption of the silicon photonic micro-ring modulator (30fJ / bit) and the static power consumption (10mW), where the static power consumption is the thermally adjustable power consumption required to stabilize the modulator operating wavelength to the 2011 wavelength of the laser; the coefficient modulator is estimated based on the static power consumption of the silicon photonic micro-ring modulator (10mW); the low-speed optical switch is estimated based on the dynamic power consumption of the silicon photonic Mach zenger optical switch (5mW); the PD is estimated based on the dynamic power consumption of the germanium-silicon waveguide photodetector (50fJ / bit); the 8-bit ADC power consumption is estimated to be twice that of a 3-bit ADC using a 65nm process; the 1×N power beam splitter and optical full adder in this invention are passive devices with no power consumption, and therefore are not listed in the table. When comparing the power consumption of the two schemes, the power consumption estimates for the same type of devices are the same, and the power consumption estimates for devices used only in existing technologies (such as DACs and RF amplifiers, ADCs, etc.) are more conservative. Table 1 As shown in Table 1, the ADC, DAC, and RF amplifier account for the largest share of power consumption in existing solutions, as shown in Figure 10(a). The total power consumption of existing solutions is 7665mW, of which the 4-bit DAC and RF amplifier account for approximately 44.2%, and the 8-bit ADC accounts for approximately 52.2%. The technical solution of this invention uses bit-based processing, eliminating the need for analog-to-digital conversion, digital-to-analog conversion, or any electrical signal amplifiers, thus achieving approximately a 10-fold power saving. As shown in Figure 10(b), the largest power consumption in this solution is the input data reading power consumption, accounting for approximately 56.2%, the laser 2011 power consumption accounts for approximately 21%, while the optical devices implementing bit-based operations account for only approximately 20% of the power consumption. As described above, DACs, RF amplifiers, and ADCs are all millimeter-sized devices, and higher precision relies heavily on advanced VLSI processes. In contrast, the optical devices used in this solution are at the micrometer level, and can be monolithically integrated using mature silicon photonics 130nm technology. Therefore, this invention offers significant advantages in terms of size and optoelectronic integration, while remaining independent of advanced processes. II. Includes product operations only between three data objects (elements). Referring to Figure 11, the example in Figure 11 is 3×3×3×3=81, and the corresponding principle is shown in Figure 12. The single-wavelength CW laser power of laser 2011 is divided into 2 inputs to 2 modulators. The input data is 3, that is,

[0011] , which is loaded onto the 2 modulators from high bit to low bit, that is, the highest bit [1] is loaded onto modulator-1, and the lowest bit [1] is loaded onto modulator-2. After being modulated by the 2 electro-optic modulators, the optical signal is also [1] and [1] from high bit to low bit respectively. The power of each optical signal is loaded onto 2 optical switches. The coefficient data of the first layer is 3, that is,

[0011] , then each group of 2 optical switches is loaded with the coefficient from high bit to low bit, that is, the highest bit [1] is loaded onto optical switch-1-1 and optical switch-2-1, and the lowest bit [1] is loaded onto optical switch-1-2 and optical switch-2-2 respectively. The above structure implements the multiplication of each bit of the 2-bit input data with each bit of the first-layer 2-bit coefficient data. The multiplication result is output as the light signal intensity after each optical switch. Corresponding to the principle shown in Figure 12, the corresponding bit results after multiplication need to be calculated using optical domain addition. Optical switch-2-2 implements the multiplication of the least significant bit of the input data with the least significant bit of the first-layer coefficient, which is directly output as the least significant bit of the first-layer output to the second-layer multiplication calculation. Optical switch-2-1 implements the multiplication of the least significant bit of the input data with the most significant bit of the first-layer coefficient, and optical switch-1-2 implements the multiplication of the most significant bit of the input data with the least significant bit of the first-layer coefficient. These two are added as corresponding bits through optical full adder-1, and the result is output as the third bit of the first-layer output data to the second-layer multiplication calculation, while the carry result is output to optical full adder-2. Optical switch-1-1 performs the multiplication of the most significant bit of the input data with the most significant bit of the first-layer coefficient. The result is then added to the carry from optical full adder-1 via optical full adder-2. The result and carry are then output as the second and most significant bits of the first-layer output data, respectively, for the second-layer multiplication calculation. The first-layer output result, i.e., the second-layer input data, is 4 bits, with each bit of data having its power divided into two and loaded onto two optical switches. Similar to the first-layer multiplication, the second-layer coefficient data is 3, i.e.,

[0011] . Each of the two optical switches in each group loads the coefficient from the most significant bit to the least significant bit. The above structure implements the multiplication of each bit of the second-layer 4-bit input data with each bit of the second-layer 2-bit coefficient data. The multiplication result is output as the optical signal intensity after each optical switch. Following the principle shown in Figure 10, the corresponding bit result after multiplication needs to be added in the optical domain, with the principle being the same as the first layer. The second-layer output result, i.e., the third-layer input data, is 6 bits, with each bit of data having its power divided into two and loaded onto two optical switches. The coefficient data for the third layer is 3, i.e.,

[0011] . Then, each group of two optical switches loads the high-bit to low-bit coefficients respectively. Similarly, after the optical switches perform optical domain multiplication, the optical full adder array performs optical domain addition, and the third layer output is 8-bit.After 8 photoelectric conversions by PDs, the final output result is [01010001], which is 81. This example implements three-layer 2-bit optical domain arithmetic processing. Since the input is 2-bit, the structure has 2 modulators; and since the coefficients are 2-bit and there are three layers, 24 optical switches, 12 optical full adders, and 8 PDs are required. This example implements 2-bit three-layer all-optical digital computing, and like the first example, it has the advantages of low power consumption, high integration, and no dependence on advanced manufacturing processes. The power consumption comparison between this example and existing technologies is shown in Table 2 below. The specific evaluation method is basically the same as the first example, except that the 2-bit high-speed DAC and RF driver are evaluated according to actual conditions. Table 2 As shown in Figure 13, the power consumption of this example is 11.4% of that of existing solutions. Because it implements 2-bit computation, the power consumption of the input drivers in existing technologies, namely the 2-bit DAC and RF amplifier, is relatively small, accounting for approximately 9%. However, the output requires an 8-bit ADC, which accounts for approximately 85% of the total power consumption. This example solution does not require a high-precision ADC and still saves a significant amount of power consumption even with the use of more optical components; the laser accounts for approximately 28%, and the input data accounts for approximately 37.2%. III. Multiplication operations between matrices Referring to Figure 14, the laser 2011 input is divided into four groups of four 4-bit modulators, each group comprising four modulators to achieve electro-optic modulation of the 4-bit input data. These are then connected to groups of four 4-bit optical switches, each group comprising four low-speed optical switches. It should be noted that the diagram shows four simplified groups of optical switches; in reality, the input data a... 11 Need to complete with b 11 and b 12 Multiplication, input data a 12 Need to complete with b 21 and b 22 The multiplication... that is, each input data needs to be connected to two sets of 4-bit optical switch multiplication units, therefore a total of 8 sets of optical switches are needed, that is, 32 optical switches. After each set completes the optical domain multiplication, the addition is performed by the optical full adder group, the principle of which is the same as the first example. According to the matrix multiplication principle in Figure 4, c 11 =a 11 ×b 11 +a 12 ×b 21 Then an additional set of optical full adders is needed to complete the addition; c 12 c 21 and c 22Similarly, each output is 9-bit, so 4 PD arrays are needed, with 9 PDs in each array. After photoelectric conversion, the final calculation result is output. This example implements a 4-bit 4×4 matrix computing processor in the optical domain. Similar to the first example, compared to existing optoelectronic fusion analog computing solutions, the most significant advantage of this example is the implementation of 4-bit computing, which is impossible with existing solutions. Furthermore, it also offers the benefits of low power consumption, high integration, and independence from advanced manufacturing processes. In addition to optoelectronic fusion computing, the embodiments of this application can also be used for direct computation of optical signals, such as in distributed fiber acoustic sensing (DAS) systems or lidar (Light Detection and Ranging) systems. In this application, there is no need for the first optical processing array 202 to perform electro-optical conversion of the input data; the input data is directly an optical signal. Only the second optical processing array 203 needs to perform coefficient multiplication and optical full adder addition to process the input data. This application provides an optical computing system, comprising: a first optical processing array 202, including a plurality of first optical processing units 2021, each first optical processing unit 2021 being configured to output a first optical signal based on a first sub-data of first data, wherein the first optical signal indicates the first sub-data, wherein the first data is binary data and the first sub-data is one bit of the first data; and a second optical processing array 203, including a plurality of second optical processing units 2031, each second optical processing unit 2031 being configured to output a second optical signal based on a first optical signal and a second sub-data of second data, wherein the second data is binary data, the second sub-data is one bit of the second data, and the second optical signal indicates the product of the first sub-data and the second sub-data. In this application, each optical processing unit only needs to support input of two-level electrical signals and output of two-level optical signals. In this case, on the one hand, the optical modulator requires a lower signal driving voltage (generally, the multi-level driving voltage of analog schemes is as high as several volts, while in this embodiment, achieving two-level electro-optical conversion only requires a few hundred millivolts of driving voltage, necessitating the deployment of an electrical amplifier before the optical modulator; however, this solution eliminates the need for additional components and corresponding power consumption). On the other hand, since the input first data is carried on digital signals through multiple first sub-data, no additional digital-to-analog converters, analog-to-digital converters, or corresponding power consumption are required. Generally, DACs, amplifiers, and ADCs are millimeter-sized devices with watt-level power consumption, and their integration with optical devices increases packaging complexity. The optical devices used in this embodiment are micrometer-sized with milliwatt-level power consumption; therefore, this solution offers significant advantages in both power consumption and size. Using mature processes, such as silicon photonics 130nm technology, monolithic integration of optical devices can be achieved, greatly reducing packaging difficulty. Furthermore, the multi-unit array architecture in this embodiment also has the advantage of scalable precision, that is, by increasing the number of optical processing units, higher precision optical bit operation processing can be achieved. This application also provides an optical computing system, the optical computing system comprising: The second optical processing array 203 includes a plurality of second optical processing units 2031. Each second optical processing unit 2031 is used to output a second optical signal based on a first optical signal and second sub-data carried in an electrical signal. The first optical signal indicates the first sub-data, the first data is binary data, and the first sub-data is one bit of the first data. The second data is binary data, and the second sub-data is one bit of the second data. The second optical signal indicates the product of the first sub-data and the second sub-data. The second optical processing unit 2031 is an optical switch. In one possible implementation, each of the second optical processing units 2031 is specifically used for: Based on the first optical signal and the optical signal corresponding to the second sub-data, perform a product operation on the first sub-data and the second sub-data to output the second optical signal. In one possible implementation, the second optical processing unit 2031 is a two-level driven optical device. In one possible implementation, the driving voltage of the second optical processing unit 2031 is less than 1 kmV. In one possible implementation, each of the second optical processing units 2031 is configured to output a second optical signal based on a first optical signal and second sub-data carried in a digital signal. In one possible implementation, the second data includes N bits, the second optical processing array includes multiple groups of optical processing units, each group of optical processing units includes N second optical processing units, and a beam splitter is used to divide the power of the first optical signal to obtain N first optical signals (for example, the power of the first optical signal can be equally divided into N first optical signals), and each of the N first optical signals is output to a second optical processing unit, wherein the N first optical signals indicate the same first sub-data, and N is an integer greater than 1. In one possible implementation, the second optical processing array is specifically used to output a second optical signal to an optical full adder so that the optical full adder obtains a plurality of third optical signals based on the plurality of second optical signals, each third optical signal indicating a third sub-data in the third data, the third data being the product of the first data and the second data, and the third sub-data being a bit in the third data. In one possible implementation, the optical computing system also includes an optical full adder. In one possible implementation, an optical full adder is used to input multiple third optical signals to a photodetector PD, so that the photodetector PD generates an electrical signal indicating third data based on the multiple third optical signals. In one possible implementation, the optical full adder is a nonlinear adder. In one possible implementation, the third data is binary data, with each third optical signal indicating one bit of the third data; the optical computing system also includes: The third optical processing array includes multiple third optical processing units. Each third optical processing unit is used to output a fourth optical signal based on a third optical signal and a fourth sub-data in the fourth data. The fourth optical signal indicates the product of a bit indicated by a third optical signal and the fourth sub-data. In one possible implementation, the second optical processing unit is an optical switch. This application embodiment also provides an optical computing method applied to an optical computing system, the optical computing system including a first optical processing array 202 and a second optical processing array 203, the first optical processing array 202 including a plurality of first optical processing units 2021, and the second optical processing array 203 including a plurality of second optical processing units 2031; the method includes: Each of the first optical processing units outputs a first optical signal based on a first sub-data of the first data. The first optical signal indicates the first sub-data, wherein the first data is binary data and the first sub-data is one bit of the first data. Each of the second optical processing units outputs a second optical signal based on a first optical signal and a second sub-data carried in an electrical signal, wherein the second data is binary data, the second sub-data is one bit of the second data, the second optical signal indicates the product of the first sub-data and the second sub-data, and the second optical processing unit is an optical switch. In one possible implementation, a second optical signal is output based on a first optical signal and second sub-data carried in an electrical signal, including: Based on the first optical signal and the optical signal corresponding to the second sub-data, perform a product operation on the first sub-data and the second sub-data to output the second optical signal. In one possible implementation, the first optical processing unit is a two-level driven optical device. In one possible implementation, the second optical processing unit is a two-level driven optical device. In one possible implementation, the driving voltage of the first optical processing unit is less than 1 kmV. In one possible implementation, the driving voltage of the second optical processing unit is less than 1 kmV. In one possible implementation, the signal input frequency supported by the first optical processing unit is greater than the signal input frequency supported by the second optical processing unit. In one possible implementation, outputting a first optical signal based on a first sub-data of the first data includes: Based on the first sub-data carried in the digital electrical signal, output the first optical signal; or... Based on a first optical signal and second sub-data carried in an electrical signal, including: Each second optical processing unit is used to output a second optical signal based on a first optical signal and second sub-data carried in a digital electrical signal. In one possible implementation, the first optical processing array includes M first optical processing units, the first data includes M bits, the M first optical processing units are used to output M first optical signals, and the M first optical signals indicate the first data, where M is an integer greater than 1. In one possible implementation, the optical computing system also includes a beam splitter. In one possible implementation, the method also includes: Each first optical processing unit outputs a first optical signal to a beam splitter, which divides the first optical signal into N first optical signals by power, and outputs each of the N first optical signals to a second optical processing unit. The N first optical signals indicate the same first sub-data, where N is an integer greater than 1. In one possible implementation, the second data includes N bits, and the second optical processing array includes multiple sets of optical processing units. Each of the first optical processing units is specifically used to output a first optical signal to a beam splitter. The beam splitter is used to divide the first optical signal into N first optical signals by power, and output each of the N first optical signals to a second optical processing unit. The N first optical signals indicate the same first sub-data, and N is an integer greater than 1. In one possible implementation, the method further includes: a second optical processing array outputting a second optical signal to an optical full adder, so that the optical full adder obtains a plurality of third optical signals based on the plurality of second optical signals, each third optical signal indicating a third sub-data in the third data, the third data being the product of the first data and the second data, and the third sub-data being a bit in the third data. In one possible implementation, the optical computing system also includes an optical full adder. In one possible implementation, the method further includes: an optical full adder inputting multiple third optical signals to a photodetector PD, so that the photodetector PD generates an electrical signal indicating third data based on the multiple third optical signals. In one possible implementation, the third data is binary data, and each third optical signal indicates one bit of the third data; the optical computing system further includes: a third optical processing array, including multiple third optical processing units; the method further includes: each third optical processing unit outputs a fourth optical signal based on a third optical signal and a fourth sub-data in the fourth data, the fourth optical signal indicating the product of the bit indicated by the third optical signal and the fourth sub-data. In one possible implementation, the first optical processing unit is an optical modulator or an optical switch. In one possible implementation, the method further includes: each first optical processing unit modulating first sub-data of the first data onto a laser carrier provided by the light source to output a first optical signal. This application also provides an optical computing method, applied to an optical computing system, the optical computing system including: a second optical processing array including a plurality of second optical processing units; the method including: Based on a first optical signal and second sub-data carried in an electrical signal, a second optical signal is output. The first optical signal indicates the first sub-data, which is binary data and the first sub-data is one bit of the first data. The second data is binary data and the second sub-data is one bit of the second data. The second optical signal indicates the product of the first sub-data and the second sub-data. The second optical processing unit is an optical switch. In one possible implementation, each of the second optical processing units is specifically used for: Based on the first optical signal and the optical signal corresponding to the second sub-data, perform a product operation on the first sub-data and the second sub-data to output the second optical signal. In one possible implementation, the second optical processing unit is a two-level driven optical device. In one possible implementation, the driving voltage of the second optical processing unit is less than 1 kmV. In one possible implementation, each second optical processing unit is used to output a second optical signal based on a first optical signal and second sub-data carried in a digital electrical signal. In one possible implementation, the second data includes N bits, the second optical processing array includes multiple groups of optical processing units, each group of optical processing units includes N second optical processing units, and a beam splitter is used to divide the power of the first optical signal to obtain N first optical signals (for example, the power of the first optical signal can be equally divided into N first optical signals), and each of the N first optical signals is output to a second optical processing unit, wherein the N first optical signals indicate the same first sub-data, and N is an integer greater than 1. In one possible implementation, the second optical processing array is specifically used to output a second optical signal to an optical full adder so that the optical full adder obtains a plurality of third optical signals based on the plurality of second optical signals, each third optical signal indicating a third sub-data in the third data, the third data being the product of the first data and the second data, and the third sub-data being a bit in the third data. In one possible implementation, the optical computing system also includes an optical full adder. In one possible implementation, an optical full adder is used to input multiple third optical signals to a photodetector PD, so that the photodetector PD generates an electrical signal indicating third data based on the multiple third optical signals. In one possible implementation, the optical full adder is a nonlinear adder. In one possible implementation, the third data is binary data, with each third optical signal indicating one bit of the third data; the optical computing system also includes: The third optical processing array includes multiple third optical processing units. Each third optical processing unit is used to output a fourth optical signal based on a third optical signal and a fourth sub-data in the fourth data. The fourth optical signal indicates the product of a bit indicated by a third optical signal and the fourth sub-data. In one possible implementation, the second optical processing unit is an optical switch. Figure 15 is a schematic diagram of an optical computing device provided in an embodiment of this application. The optical computing device 1500 includes a processor 1501 and a chip 1502, wherein the chip 1502 may include the optical processing system described in the above embodiments. The processor 1501 is used to pass the objects of the multiplication operation (such as first data and second data) to the chip 1502, and to receive the product calculation result of the first data and the second data sent by the chip 1502. At this time, the chip 1502 can be integrated with the processor 1501 on the substrate in the form of a system on chip (SoC). The optical calculator and the processor 1501 can realize the advantages of close-range high-speed communication, while giving full play to the advantages of the processor 1501's expertise in logical operations and the chip 1502's high parallelism and light-speed execution. Furthermore, the chip in this embodiment can be placed in a computing device, which can perform AI calculations. In terms of product form, the computing device can be a terminal device or a server. In terms of function, the computing device can be an execution device for a neural network or a training device for a neural network. The following describes an execution device provided in an embodiment of this application. Please refer to Figure 16, which is a schematic diagram of the structure of an execution device provided in an embodiment of this application. The execution device 1600 can specifically be a mobile phone, tablet, laptop, smart wearable device, etc., and is not limited here. Specifically, the execution device 1600 includes: a receiver 1601, a transmitter 1602, a processor 1603, a memory 1604 (the number of processors 1603 in the execution device 1600 can be one or more; Figure 16 shows one processor as an example), and a chip 1502. The processor 1603 may include an application processor 16031 and a communication processor 16032. In some embodiments of this application, the receiver 1601, transmitter 1602, processor 1603, memory 1604, and chip 1502 can be connected via a bus or other means. Memory 1604 may include read-only memory and random access memory, and provides instructions and data to processor 1603. A portion of memory 1604 may also include non-volatile random access memory (NVRAM). Memory 1604 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations. Processor 1603 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram. Processor 1603 can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed through integrated logic circuits in the hardware of processor 1603 or through software instructions. Processor 1603 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor. The software module can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 1604. Processor 1603 reads information from memory 1604 and, in conjunction with its hardware, completes the steps of the method. Receiver 1601 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 1602 can be used to output digital or character information; transmitter 1602 can also be used to send instructions to the disk group to modify the data in the disk group. Chip 1502 can interact with memory 1604 and processor 1603. For example, chip 1502 can obtain the object to be multiplied (e.g., first data and second data) from memory 1604 or processor 1603, perform the multiplication operation on the object, and return the result to memory 1604 or processor 1603. This application embodiment also provides a server. Referring to Figure 17, Figure 17 is a schematic diagram of a server structure provided in this application embodiment. Specifically, server 1700 is implemented by one or more servers. Server 1700 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1717 (e.g., one or more processors) and memory 1732, and one or more storage media 1730 (e.g., one or more mass storage devices) for storing application programs 1742 or data 1744. The memory 1732 and storage media 1730 can be temporary or persistent storage. The program stored in storage media 1730 may include one or more modules (not shown in the figure), each module may include a series of instruction operations on the server. Furthermore, the CPU 1717 may be configured to communicate with storage media 1730 and execute the series of instruction operations in storage media 1730 on server 1700. Server 1700 may also include one or more power supplies 1717, one or more wired or wireless network interfaces 1750, one or more input / output interfaces 1758; or, one or more operating systems 1741, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc. Chip 1502 can interact with memory 1732 and central processing unit 1717. For example, chip 1502 can obtain the object to be multiplied (e.g., first data and second data) from memory 1732 or central processing unit 1717, perform the multiplication operation on the object, and return the operation result to memory 1732 or central processing unit 1717. This application also provides a computer program product including computer-readable instructions, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device. This application also provides a computer-readable storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device. Specifically, please refer to Figure 18, which is a schematic diagram of a system provided in an embodiment of this application. The system may include a neural network processor (NPU) 1800. The NPU 1800 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core of the NPU is the arithmetic circuit 1803, which is controlled by a controller 1804 to extract matrix data from the memory and perform multiplication operations. In some implementations, the arithmetic circuit 1803 internally includes multiple processing engines (PEs). In some implementations, the arithmetic circuit 1803 is a two-dimensional pulsating array. The arithmetic circuit 1803 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1803 is a general-purpose matrix processor. For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 1802 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 1801 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 1808. Unified memory 1806 is used to store input and output data. Weight data is directly transferred to weight memory 1802 via Direct Memory Access Controller (DMAC) 1805. Input data is also transferred to unified memory 1806 via DMAC. BIU stands for Bus Interface Unit, which is used for interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 1809. The Bus Interface Unit (BIU) 1810 is used by the instruction fetch memory 1809 to fetch instructions from external memory, and also by the memory access controller 1805 to fetch the original data of the input matrix A or the weight matrix B from external memory. The DMAC is mainly used to move input data from external memory DDR to unified memory 1806, or to weight data to weight memory 1802, or to input data to input memory 1801. The vector computation unit 1807 includes multiple arithmetic processing units that further process the output of the computation circuit as needed, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as batch normalization, pixel-level summation, and upsampling of feature planes. In some implementations, the vector computation unit 1807 can store the processed output vector in the unified memory 1806. For example, the vector computation unit 1807 can apply a linear function, or a nonlinear function, to the output of the computation circuit 1803, such as performing linear interpolation on feature planes extracted by a convolutional layer, or, for example, accumulating a vector of values ​​to generate activation values. In some implementations, the vector computation unit 1807 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as an activation input to the computation circuit 1803, for example, for use in subsequent layers of the neural network. The instruction fetch buffer 1809 connected to the controller 1804 is used to store the instructions used by the controller 1804; Unified memory 1806, input memory 1801, weighted memory 1802, and instruction fetch memory 1809 are all on-chip memories. External memory is proprietary to this NPU hardware architecture. The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program. Chip 1502 can interact with memory and the main CPU. For example, chip 1502 can obtain the object to be multiplied (such as first data and second data) from memory or the central main CPU, perform the multiplication operation on the object, and return the operation result to memory or the main CPU. It is understood that the device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and other division methods may exist in actual implementation. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the connections between the modules discussed in the above embodiments can be electrical, mechanical, or other forms. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules. Additionally, the functional modules in the various embodiments of the application may exist independently or be integrated into a single processing module. This invention also provides a computer program product for data processing, including a computer-readable storage medium storing program code. The program code includes instructions for executing the method flow described in any of the foregoing method embodiments. Those skilled in the art will understand that the aforementioned storage medium includes various non-transitory machine-readable media capable of storing program code, such as USB flash drives, portable hard drives, magnetic disks, optical disks, random-access memory (RAM), solid-state disks (SSDs), or non-volatile memory. It should be noted that the embodiments provided in this application are merely illustrative. Those skilled in the art will understand that, for the sake of convenience and brevity, the descriptions of each embodiment have different focuses, and parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The features disclosed in the embodiments, claims, and drawings of this invention can exist independently or in combination. Features described in hardware form in the embodiments of this invention can be executed by software, and vice versa. No limitations are imposed here.

Claims

1. An optical computing system, characterized in that... The optical computing system includes: The first optical processing array includes a first optical processing unit, which is used to output a first optical signal based on a first sub-data separated from the first data, wherein the first data is binary data and the first sub-data is one bit of the first data; The second optical processing array includes a second optical processing unit. The second optical processing unit performs a product operation on the first optical signal and second sub-data separated from the second data, and outputs a second optical signal. The second sub-data is one bit of the second data, the second data is binary data carried in an electrical signal, and the second optical signal indicates the product result of the first sub-data and the second data. The second optical processing unit is an optical switch. 。 2. The system according to claim 1, wherein its features The characteristic is that the second light processing unit is specifically used for: Based on the electrical signal, the optical signal corresponding to the second sub-data is obtained; Based on the first optical signal and the optical signal corresponding to the second sub-data, perform a product operation on the first sub-data and the second sub-data to output the second optical signal. Signal.

3. The system according to claim 1 or 2, The characteristic is that the maximum signal input frequency of the first optical processing unit is greater than the maximum signal frequency of the second optical processing unit. Input frequency.

4. The system according to any one of claims 1 to 3 The system is characterized in that the optical computing system further includes: an optical full adder; the second optical processing array includes multiple optical processing units, including the second optical processing unit; The second optical processing array is specifically used to output the second optical signal to the optical full adder; The optical full adder is used to obtain multiple third optical signals based on multiple second optical signals output by the multiple optical processing units. Each third optical signal indicates a third sub-data in the third data. The third data is the product of the first data and the second data. The third data is binary data, and the third sub-data is a subset of the third data. One bit.

5. As described in claim 4 The system, characterized in that the optical full-addition... The device is a nonlinear adder.

6. According to claim 4 or 5 The system is characterized in that the optical full adder is used to input the plurality of third optical signals to the photodetector PD, so that the photodetector PD generates an indication based on the plurality of third optical signals. The electrical signal of the third data.

7. According to claims 1 to 6 The system described in any one of the above is characterized in that the first optical processing array comprises M first optical processing units, the first data comprises M bits, the M first optical processing units are used to output M first optical signals, and the M first optical signals indicate the first data. According to the data, M is an integer greater than 1.

8. According to claim 1 The system according to any one of 7 is characterized in that the system further includes: a beam splitter; Each of the first optical processing units is specifically configured to output a first optical signal to a beam splitter, wherein the beam splitter is configured to divide the first optical signal into N first optical signals by power, and output each of the N first optical signals to a second optical processing unit, wherein the N first optical signals indicate the same first optical signal. Sub-data, where N is an integer greater than 1.

9. According to the right The system according to claim 7 or 8 is characterized in that the second data includes N bits, the second optical processing array includes multiple groups of optical processing units, each group of optical processing units includes N second optical processing units, and the beam splitter is specifically used to output the N first optical signals to the second optical processing unit. The same set of optical processing units in a dual-optical processing array.

10. According to claim 4, 5. and any one of the systems described in 7 to 9, characterized in that the optical computing system further includes: The third optical processing array includes multiple third optical processing units. Each third optical processing unit is configured to output a fourth optical signal based on a third optical signal and fourth sub-data in the fourth data. The fourth optical signal indicates the third optical signal. The product of the indicated bit and the fourth sub-data.

11. The system according to any one of claims 1 to 10, wherein its features The characteristic is that the first optical processing unit is an optical modulator or an optical switch.

12. The system according to any one of claims 1 to 11, wherein the first optical processing unit is specifically used to separate the first sub-data from the first data. The first optical signal is output by modulating the carrier laser provided by the light source. Number.

13. According to claims 1 to 1 2. The system according to any one of the above, characterized in that the system further comprises: The light source.

14. The claims 1 to 13 The system is characterized in that the first optical processing unit comprises two electrical components. Flat-drive optical devices.

15. According to claims 1 to 14 The system described in any one of the above is characterized in that the first optical processing unit... The driving voltage is less than 1 kMV.

16. According to claim 1 The system described in any one of 15 is characterized by The key difference is that the driving voltage of the second optical processing unit is less than 1 kmV.

17. An optical computing chip, characterized in that the chip includes a system, an input interface, and an output interface as described in any one of claims 1-16; The input interface is communicatively connected to the processor or memory, and is used to acquire first data and second data sent from the processor or memory; The output interface is communicatively connected to the processor or the memory. Used to transfer data based on the first data and the... The product result obtained from the second data is transmitted to the processor or the memory.

18. A computing device, characterized in that... The system includes a processor and the optical computing as described in claim 17. chip; The processor and the optical computing chip Communication connection.

19. According to the rights The computing device described in claim 18 is characterized in that the computing device is a terminal device or a server.

20. An optical computing method, characterized in that the method is applied to an optical computing system, the optical computing system comprising a first optical processing array and a second optical processing array, wherein... The first optical processing array The method includes a first optical processing unit, and the second optical processing array includes a second optical processing unit; the second optical processing unit is an optical switch; the method includes: The first optical processing unit, based on the first data separated from the first data, One sub-data, outputting a first optical signal, wherein the first data is binary data, and the first sub-data is one bit of the first data; The second optical processing unit performs a product operation on the first optical signal and the second sub-data separated from the second data, and outputs a second optical signal. The second sub-data is one bit of the second data, and the second data is binary data. The second optical signal is carried in an electrical signal, indicating the product of the first sub-data and the second sub-data, and the second optical processing unit is an optical switch.

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