Infrared focal plane detector chip structure with suspension verification structure and preparation method

Abstract

The invention discloses an infrared focal plane detector chip structure with a suspension verification structure and a preparation method, the infrared focal plane detector chip structure with the suspension verification structure comprises an R0IC wafer, the suspension verification structure, a pixel bridge floor layer and an infrared absorption umbrella layer, the suspension verification structure is arranged on the surface of the R0IC wafer, the pixel bridge floor layer is arranged on the surface of the R0IC wafer, and the infrared absorption umbrella layer is arranged on the surface of the R0IC wafer. The pixel bridge floor layer is arranged on the suspension verification structure, and the infrared absorption umbrella layer is arranged on the pixel bridge floor layer; the suspension verification structure comprises a dielectric layer and a resistance layer, the resistance layer is divided into two parts, one part is a heating resistor of the suspension verification structure, and the other part is a pixel replacement resistor structure. According to the invention, bad problems generated by the R0IC and the MEMS can be verified separately, the response rate of the pixel of the infrared focal plane detector is improved, and the suspension verification structure has no influence on thermal and electrical parameters of the pixel.

Description

Technical Field

[0001] The present invention relates to the field of micro-electromechanical system (MEMS) design and manufacturing technology in semiconductor technology, and in particular to an infrared focal plane detector chip structure with a suspension verification structure and a preparation method thereof. Background Art

[0002] The MEMS uncooled infrared detectors based on CMOS technology have been widely used in military and commercial fields, such as night vision, prospecting, automatic driving, fire prevention and control, etc. The detector chip mainly consists of two parts, one is the MEMS chip with a high response rate, and the other is the ROIC chip directly connected to the MEMS chip. The working principle of the uncooled infrared detector is that the external infrared radiation irradiates the thermistor layer of the chip, causing the temperature of the thermistor layer to rise. Since the thermistor material itself has a certain resistance temperature coefficient, the temperature rise causes the resistance of the thermistor material to change. The ROIC chip can be used to read the resistance change of thermistor material caused by external infrared radiation by applying a certain electrical bias at both ends of the thermistor material. Through certain calibration methods, the resistance change is corresponded to the external temperature change, that is, the infrared temperature measurement and imaging functions are completed.

[0003] The main function of the above-mentioned ROIC chip is to integrate the photocurrent signal generated by the MEMS chip into a voltage signal according to a reasonable timing, and perform signal processing operations such as amplification, sampling, and output drive, thereby realizing the role of a bridge between the detector array photoelectric signal and the system signal processing circuit.

[0004] Generally, the ROIC circuit is processed by standard semiconductor process, and then the MEMS chip is taped again on the ROIC to form a complete IRFPA chip. The final output signal content contains both the external radiation information collected by the MEMS chip and the additional information of the processing process of the ROIC chip. If you need to verify whether the problem of the overall output signal of the IRFPA comes from the MEMS or ROIC, it is generally difficult, and even the source of the problem cannot be determined in the end. A large number of wafers need to be invested in batch experiments to troubleshoot the problem, which generates a lot of money and time. The existing IRFPA chip is not fully designed to achieve the purpose of verifying the source of the chip problem; another existing technology is to tap out the MEMS and ROIC chips on two wafers to verify the source of the problem. The shortcoming of this technical method is that the MEMS chip prepared on the bare wafer will be different from the structure and performance of the subsequent taping on the ROIC. For example, when processing the MEMS chip on the ROIC, the heat generated in the MEMS process will affect the performance of the underlying ROIC. In addition, the thermal conductivity of the ROIC chip wafer and the bare wafer is different, resulting in temperature affecting the MEMS process and then affecting the MEMS performance. Both existing technologies cannot complete the verification work well, but this verification work is very necessary. Differentiating the problems and improving the design or process adjustment for the problematic chips will save engineering time and capital investment. Summary of the invention

[0005] The main purpose of the present invention is to propose an infrared focal plane detector chip structure with a suspended verification structure and a preparation method, aiming to separately verify the adverse problems caused by ROIC and MEMS, improve the response rate of the infrared focal plane detector pixel, and not affect the thermal and electrical parameters of the pixel.

[0006] To achieve the above-mentioned object, the present invention provides an infrared focal plane detector chip structure with a suspension verification structure, wherein the infrared focal plane detector chip structure with a suspension verification structure comprises an ROIC wafer, a suspension verification structure, a pixel bridge deck layer and an infrared absorption umbrella layer, wherein the suspension verification structure is arranged on the surface of the ROIC wafer, the pixel bridge deck layer is arranged on the suspension verification structure, and the infrared absorption umbrella layer is arranged on the pixel bridge deck layer;

[0007] The suspension verification structure includes a dielectric layer and a resistance layer. The resistance layer is divided into two parts, one part is the heating resistor of the suspension verification structure, and the other part is the replacement pixel resistance structure.

[0008] A further technical solution of the present invention is that the pixel bridge deck layer includes a first dielectric insulating layer, a thermal sensitive layer, a second dielectric insulating layer, an electrical conductive layer and a dielectric protective layer which are sequentially arranged from bottom to top.

[0009] A further technical solution of the present invention is that the infrared absorption umbrella layer is composed of a dielectric and a conductive layer with a certain resistance.

[0010] A further technical solution of the present invention is that the resistance layer of the suspension verification structure is a single-layer or multi-layer material with a certain resistance, and the material includes Ti, Al, Cu, W, Cr, Ni, TiN or polycrystalline silicon.

[0011] A further technical solution of the present invention is that the material of the dielectric layer of the suspension verification structure includes Si3N4 or SiO2.

[0012] To achieve the above object, the present invention further proposes a method for preparing an infrared focal plane detector chip structure with a suspended verification structure, the method comprising the following steps:

[0013] Step S10, preparing a suspended PI-O layer on the ROIC wafer, and after the preparation of the suspended PI-O layer is completed, photolithography etching is performed on the suspended PI-O layer to expose the suspended verification structure electrode of the ROIC wafer;

[0014] Step S20, preparing a dielectric layer and a resistor layer on the suspended PI-O layer, and performing photolithography and etching to form a suspended verification structure with a certain resistance, wherein the resistor layer is divided into two parts, one part is a heating resistor of the suspended verification structure, and the other part is a replacement pixel resistor structure;

[0015] Step S30, preparing a PI-1 layer on the suspended verification structure, and photolithographically etching to form a PI-1 hole structure connecting the pixel structure with the ROIC wafer pixel electrode;

[0016] Step S40, preparing a first dielectric insulating layer and a thermal sensitive layer on the PI-1 layer, and performing photolithography and etching on them to form a suitable structure;

[0017] Step S50, preparing a second dielectric insulating layer and an electrical conductive layer on the thermal layer, wherein one end of the electrical conductive layer is connected to the thermal layer, and the other end is connected to the ROIC wafer pixel electrode; preparing a dielectric layer on the electrical conductive layer to form a protective layer, and the first dielectric insulating layer, the thermal layer, the second dielectric insulating layer, the electrical conductive layer and the dielectric protective layer prepared on the PI-1 layer together constitute a pixel bridge layer;

[0018] Step S60, preparing a PI-2 layer on the pixel bridge deck layer, photolithography and etching to form a contact hole penetrating the dielectric protection layer, and preparing an infrared absorption umbrella layer on the PI-2 layer, wherein the infrared absorption umbrella layer is composed of a dielectric and a conductive layer with a certain resistance;

[0019] Step S70: releasing all PI layers through a plasma process to form a pixel structure with a suspended verification structure.

[0020] A further technical solution of the present invention is that in step S10, the step of preparing a suspended PI-0 layer on the ROIC wafer comprises:

[0021] Deep silicon etching is performed on the ROIC wafer to form an inverted trapezoidal etching pit, an infrared reflection layer is prepared on the inner surface of the inverted trapezoidal etching pit, and then a suspended PI-0 layer is prepared on the infrared reflection layer, or a suspended PI-0 layer is directly prepared on the ROIC wafer.

[0022] A further technical solution of the present invention is that before step S10, the following steps are further included:

[0023] The ROIC wafer is cleaned and dried to remove surface impurities and moisture.

[0024] The beneficial effects of the infrared focal plane detector chip structure with a suspension verification structure and the preparation method of the present invention are:

[0025] 1. By sequentially preparing ROIC and MEMS chips on the same ROIC wafer, the MEMS chip has a suspended verification structure, which can verify the defects of ROIC and MEMS separately, saving money and time costs;

[0026] 2. The present invention uses an inverted trapezoidal etched pit to prepare an infrared reflective layer. Compared with a planar reflective layer, the inverted trapezoidal reflective layer has a better light-gathering effect and improves the response rate of the infrared focal plane detector pixel;

[0027] 3. The suspended verification structure prepared by the present invention has no effect on the electrical parameters and thermal parameters of the pixel structure, thereby ensuring that the pixel structure has a high response rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0029] Figure 1 It is a schematic diagram of the overall structure of the infrared focal plane detector chip structure with a suspension verification structure of the present invention with an inverted trapezoidal etched pit;

[0030] Figure 2 yes Figure 8 It is a schematic diagram of the preparation process of the infrared focal plane detector chip structure with a suspended verification structure having an inverted trapezoidal etching pit according to the present invention;

[0031] Fig. 9 It is a schematic diagram of the overall structure of the infrared focal plane detector chip structure with a suspension verification structure without an inverted trapezoidal etching pit of the present invention;

[0032] Figures 10 to 16 It is a schematic diagram of the preparation process of the infrared focal plane detector chip structure with a suspension verification structure without inverted trapezoidal etching pits of the present invention;

[0033] Fig.17 It is a schematic flow chart of a method for preparing an infrared focal plane detector chip structure with a suspension verification structure according to the present invention.

[0034] Description of Figure Numbers:

[0035] ROIC wafer 1; suspended verification structure 2; pixel bridge layer 3; infrared absorption umbrella layer 4; dielectric layer 5; pixel electrode 6; reflective layer 7; heating resistor 8; alternative pixel resistor structure 9; suspended verification structure electrode 10; first dielectric insulating layer 11; thermal sensitive layer 12; second dielectric insulating layer 13; electrical conduction layer 14; dielectric protective layer 15.

[0036] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The present invention proposes an infrared focal plane detector chip structure with a suspension verification structure, please refer to Figures 1 to 16 A preferred embodiment of the infrared focal plane detector chip structure with a suspended verification structure of the present invention includes a ROIC wafer 1, a suspended verification structure 2, a pixel bridge deck layer 3 and an infrared absorption umbrella layer 4, wherein the suspended verification structure 2 is arranged on the surface of the ROIC wafer 1, the pixel bridge deck layer 3 is arranged on the suspended verification structure 2, and the infrared absorption umbrella layer 4 is arranged on the pixel bridge deck layer 3.

[0039] It should be noted that the "suspension" described in this embodiment means that the main part of the structure has no physical connection between the upper and lower parts, and only the electrodes are connected to the ROIC wafer 1 below. After the chip is packaged, the structure is vacuum above and below.

[0040] The suspended verification structure 2 includes a dielectric layer 5 and a resistor layer. The resistor layer is divided into two parts. One part is the heating resistor 8 of the suspended verification structure 2 , and the other part is the replacement pixel resistor structure 9 .

[0041] Specifically, in this embodiment, the pixel bridge deck layer 3 includes a first dielectric insulating layer 11 , a thermal sensitive layer 12 , a second dielectric insulating layer 13 , an electrical conductive layer 14 and a dielectric protective layer 15 which are sequentially arranged from bottom to top.

[0042] The infrared absorption umbrella layer 4 is composed of a dielectric and a conductive layer with a certain resistance.

[0043] The resistance layer of the suspension verification structure 2 is a single-layer or multi-layer material with a certain resistance, and the material includes Ti, Al, Cu, W, Cr, Ni, TiN or polysilicon.

[0044] The material of the dielectric layer 5 of the suspended verification structure 2 includes Si 3 N 4 or SiO 2 .

[0045] The preparation process of conventional IRFPA chips is as follows: after the ROIC chip process is completed, the first sacrificial layer is first prepared on the chip. The sacrificial layer material is generally PI (polyimide), and the bridge pier holes of the microbridge structure are formed on the PI using a photolithography process. Then, other structures such as a support layer, a thermal layer 12, and an electrical connection layer are prepared on the PI layer, and patterned by photolithography, and finally, the PI is removed by release to form a microbridge structure pixel. Before the first layer of PI is removed, the chip using a double-layer or even multi-layer process will continue to prepare a second or more layers of PI and a patterned functional film layer on the first layer of microbridges, and finally release all the PI in one step to form a multi-layer structure pixel.

[0046] In the preparation process of the infrared focal plane detector chip structure with a suspension verification structure in this embodiment, in addition to the above-mentioned conventional IRFPA preparation process, a suspension layer PI-0 is prepared on the ROIC wafer 1; a suspension verification layer is prepared on the suspension layer PI-0, and the suspension verification layer is photolithographically etched to form a suspension verification structure 2 connected to the ROIC electrode.

[0047] In this embodiment, two chips, ROIC and MEMS, are sequentially prepared on the same ROIC wafer 1. The MEMS chip has a suspended verification structure 2, which can verify the adverse problems caused by ROIC and MEMS separately, saving money and time costs; in particular, the suspended verification structure 2 of the present invention includes both a heating resistor 8 structure and a replacement pixel resistor structure 9, eliminating the IRFPA blind pixel problem.

[0048] In this embodiment, the suspension verification structure 2 includes at least one group of heating resistors 8 and one group of replacement pixel resistor structures 9. The working process of the heating resistor 8 structure is that a certain power heat P0 is applied to the two electrodes of the suspension verification structure 2 through the ROIC chip, and the heat is radiated and transferred to the thermosensitive layer 12. The resistance change signal generated by the temperature rise of the thermosensitive layer 12 is processed by the output of the other two electrodes of the ROIC to form a voltage signal V0 corresponding to PO. By comparing different P0 and V0 signals, it can be judged whether the MEMS pixel is normal; the function of the replacement pixel resistor structure 9 is the same as that of the pixel thermosensitive layer 12. When the function of the pixel thermosensitive layer 12 fails, the ROIC control software reads the output signal of the pixels around the failed pixel of the thermosensitive layer 12, interpolates and calculates the output signal of the failed pixel position of the thermosensitive layer 12, and feeds it back to the control end of the ROIC heating resistor 8, so that the output signal of the replacement pixel resistor through the ROIC is the same as the interpolation calculation signal, thereby completing the purpose of replacing the failed pixel. The ROIC chip comes with a set of verification structures isolated from the MEMS, which can complete the ROIC chip verification. In summary, the purpose of first preparing the ROIC chip and then preparing the MEMS chip on the same wafer and then verifying the ROIC and MEMS chips separately is achieved.

[0049] One route of the suspended verification structure 2 is to first perform deep silicon etching technology on the ROIC wafer 1 to form an inverted trapezoidal etched pit, prepare an infrared reflection layer 7 on the inner surface of the inverted trapezoid, and then prepare a suspension layer PI-0, and prepare the suspended verification structure 2 on the suspension layer. The infrared reflection layer 7 is prepared in the inverted trapezoidal etched pit. Compared with the planar reflection layer, the inverted trapezoidal reflection layer 7 has a better focusing effect, which improves the response rate of the infrared focal plane detector pixel.

[0050] In this embodiment, the suspended verification structure 2 can be prepared under the bridge deck layer or above the bridge deck layer. The suspended verification structure 2 has no contact thermal isolation with the pixel structure. The prepared suspended verification structure 2 has no effect on the electrical parameters and thermal parameters of the pixel structure, thereby ensuring that the pixel structure has a high response rate.

[0051] In summary, the beneficial effects of the infrared focal plane detector chip structure with the suspended verification structure 2 of the present invention are:

[0052] 1. By sequentially preparing ROIC and MEMS chips on the same ROIC wafer 1, the MEMS chip has a suspended verification structure 2, which can verify the defects of ROIC and MEMS separately, saving money and time costs;

[0053] 2. The present invention adopts an inverted trapezoidal etched pit to prepare an infrared reflection layer 7. Compared with the plane reflection layer 7, the inverted trapezoidal reflection layer 7 has a better focusing effect, thereby improving the response rate of the infrared focal plane detector pixel;

[0054] 3. The suspended verification structure 2 prepared by the present invention has no influence on the electrical parameters and thermal parameters of the pixel structure, thus ensuring that the pixel structure has a high response rate.

[0055] To achieve the above object, the present invention also proposes a method for preparing an infrared focal plane detector chip structure with a suspension verification structure, please refer to Fig.17 ,as well as Figures 1 to 16 , the method comprises the following steps:

[0056] Step S10, preparing a suspended PI-0 layer on the ROIC wafer 1, and after the preparation of the suspended PI-0 layer is completed, photolithography etching is performed on the suspended PI-O layer to expose the suspended verification structure electrode 10 of the ROIC wafer 1;

[0057] Step S20, preparing a dielectric layer 5 and a resistor layer on the suspended PI-0 layer, and performing photolithography and etching to form a suspended verification structure 2 with a certain resistance, wherein the resistor layer is divided into two parts, one part is the heating resistor 8 of the suspended verification structure 2, and the other part is the replacement pixel resistor structure 9;

[0058] Step S30, preparing a PI-1 layer on the suspended verification structure 2, and photolithographically etching to form a PI-1 hole structure in which the pixel structure is connected to the pixel electrode 6 of the ROIC wafer 1;

[0059] Step S40, preparing a first dielectric insulating layer 11 and a thermosensitive layer 12 on the PI-1 layer, and performing photolithography and etching on them to form a suitable structure;

[0060] Step S50, preparing a second dielectric insulating layer 13 and an electrical conductive layer 14 on the thermal sensitive layer 12, wherein one end of the electrical conductive layer 14 is connected to the thermal sensitive layer 12, and the other end is connected to the pixel electrode 6 of the ROIC wafer 1; preparing a dielectric layer 5 on the electrical conductive layer 14 to form a protective layer, and the first dielectric insulating layer 11, the thermal sensitive layer 12, the second dielectric insulating layer 13, the electrical conductive layer 14 and the dielectric protective layer 15 prepared on the PI-1 layer together constitute the pixel bridge deck layer 3;

[0061] Step S60, preparing a PI-2 layer on the pixel bridge deck layer 3, photolithographically etching a contact hole penetrating the dielectric protection layer 15, and preparing an infrared absorption umbrella layer 4 on the PI-2 layer, wherein the infrared absorption umbrella layer 4 is composed of a dielectric and a conductive layer with a certain resistance;

[0062] Step S70 , releasing all PI layers through a plasma process to form a pixel structure having a suspended verification structure 2 .

[0063] In this embodiment, in step S10, the step of preparing a suspended PI-0 layer on the ROIC wafer 1 includes:

[0064] Deep silicon etching is performed on the ROIC wafer 1 to form an inverted trapezoidal etching pit, an infrared reflection layer 7 is prepared on the inner surface of the inverted trapezoidal etching pit, and then a suspended PI-0 layer is prepared on the infrared reflection layer 7, or a suspended PI-0 layer is directly prepared on the ROIC wafer 1.

[0065] In this embodiment, before step S10, the following steps are also included:

[0066] The ROIC wafer 1 is cleaned and dried to remove surface impurities and moisture.

[0067] The beneficial effects of the method for preparing the infrared focal plane detector chip structure with the suspended verification structure 2 of the present invention are:

[0068] 1. By sequentially preparing ROIC and MEMS chips on the same ROIC wafer 1, the MEMS chip has a suspended verification structure 2, which can verify the defects of ROIC and MEMS separately, saving money and time costs;

[0069] 2. The present invention adopts an inverted trapezoidal etched pit to prepare an infrared reflection layer 7. Compared with the plane reflection layer 7, the inverted trapezoidal reflection layer 7 has a better focusing effect, thereby improving the response rate of the infrared focal plane detector pixel;

[0070] 3. The suspended verification structure 2 prepared by the present invention has no influence on the electrical parameters and thermal parameters of the pixel structure, thus ensuring that the pixel structure has a high response rate.

[0071] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. An infrared focal plane detector chip structure with a suspended verification structure, characterized in that: The infrared focal plane detector chip structure with a suspension verification structure comprises an ROIC wafer, a suspension verification structure, a pixel bridge deck layer and an infrared absorption umbrella layer, wherein the suspension verification structure is arranged on the surface of the ROIC wafer, the pixel bridge deck layer is arranged on the suspension verification structure, and the infrared absorption umbrella layer is arranged on the pixel bridge deck layer; The suspension verification structure includes a dielectric layer and a resistance layer. The resistance layer is divided into two parts, one part is the heating resistor of the suspension verification structure, and the other part is the replacement pixel resistance structure.

2. The infrared focal plane detector chip structure with a suspension verification structure according to claim 1, characterized in that: The pixel bridge deck layer includes a first dielectric insulating layer, a thermal sensitive layer, a second dielectric insulating layer, an electrical conductive layer and a dielectric protective layer which are sequentially arranged from bottom to top.

3. The infrared focal plane detector chip structure with a suspension verification structure according to claim 2, characterized in that: The infrared absorption umbrella layer is composed of a dielectric and a conductive layer with a certain resistance.

4. The infrared focal plane detector chip structure with a suspension verification structure according to claim 3, characterized in that: The resistance layer of the suspension verification structure is a single-layer or multi-layer material with a certain resistance, and the material includes Ti, Al, Cu, W, Cr, Ni, TiN or polysilicon.

5. A method for preparing an infrared focal plane detector chip structure with a suspended verification structure, characterized in that: The method comprises the following steps: Step S10, preparing a suspended PI-0 layer on the ROIC wafer, and after the preparation of the suspended PI-0 layer is completed, photolithography etching is performed on the suspended PI-0 layer to expose the suspended verification structure electrode of the ROIC wafer; Step S20, preparing a dielectric layer and a resistor layer on the suspended PI-0 layer, and performing photolithography and etching to form a suspended verification structure with a certain resistance, wherein the resistor layer is divided into two parts, one part is a heating resistor of the suspended verification structure, and the other part is a replacement pixel resistor structure; Step S30, preparing a PI-1 layer on the suspended verification structure, and photolithographically etching to form a PI-1 hole structure connecting the pixel structure with the ROIC wafer pixel electrode; Step S40, preparing a first dielectric insulating layer and a thermal sensitive layer on the PI-1 layer, and performing photolithography and etching on them to form a suitable structure; Step S50, preparing a second dielectric insulating layer and an electrical conductive layer on the thermal layer, wherein one end of the electrical conductive layer is connected to the thermal layer, and the other end is connected to the ROIC wafer pixel electrode; preparing a dielectric layer on the electrical conductive layer to form a protective layer, and the first dielectric insulating layer, the thermal layer, the second dielectric insulating layer, the electrical conductive layer and the dielectric protective layer prepared on the PI-1 layer together constitute a pixel bridge layer; Step S60, preparing a PI-2 layer on the pixel bridge deck layer, photolithography and etching to form a contact hole penetrating the dielectric protection layer, and preparing an infrared absorption umbrella layer on the PI-2 layer, wherein the infrared absorption umbrella layer is composed of a dielectric and a conductive layer with a certain resistance; Step S70: releasing all PI layers through a plasma process to form a pixel structure with a suspended verification structure.

6. The method for preparing an infrared focal plane detector chip structure with a suspension verification structure according to claim 5, characterized in that: In step S10, the step of preparing a suspended PI-0 layer on the ROIC wafer includes: Deep silicon etching is performed on the ROIC wafer to form an inverted trapezoidal etching pit, an infrared reflection layer is prepared on the inner surface of the inverted trapezoidal etching pit, and then a suspended PI-0 layer is prepared on the infrared reflection layer, or a suspended PI-0 layer is directly prepared on the ROIC wafer.

7. The method for preparing an infrared focal plane detector chip structure with a suspension verification structure according to claim 5, characterized in that: Before step S10, the following steps are also included: The ROIC wafer is cleaned and dried to remove surface impurities and moisture.

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