SiC MOSFET power cycle test grid dynamic bias control method and control terminal

Abstract

The invention provides a SiC MOSFET power cycle test grid dynamic bias control method and a control terminal. The method comprises the steps that in a power cycle test of one cycle, reverse bias voltage is applied to a grid electrode of a target MOSFET in the turn-off period of power cycle, the influence of forward bias voltage in the turn-on period is balanced, and threshold voltage is kept stable; according to the method, the forward bias voltage is applied to the grid electrode of the target MOSFET before the next cycle is started, and meanwhile, the forward bias duration of the current cycle is dynamically adjusted according to the parameters of the previous cycle, so that the gate-oxide charge state is in an approximate level, each cycle test cycle is stable, and the comparability between the measurement results of each test cycle is improved. On the basis, drift of the threshold voltage can be effectively suppressed, so that the threshold voltage is kept relatively stable in the whole test period, and the accuracy of threshold voltage monitoring is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor performance detection, and in particular to a SiC MOSFET power cycle test gate dynamic bias control method and a control terminal. Background Art

[0002] The power cycle test applies electrical stress of cyclic opening and closing to the device under test. A complete test cycle includes the sum of the opening cycle and the closing cycle. The junction temperature of the device increases during the opening cycle and decreases during the closing cycle. The power cycle test occupies an important position in the SiC MOSFET reliability test system. The key test condition is the junction temperature. Accurate detection of the junction temperature is a basic requirement of the power cycle test.

[0003] In the prior art, power cycling tests usually heat the channel and monitor the junction temperature based on the electrothermal relationship of the channel. However, since the stress of the power cycling test will cause a positive drift in the threshold voltage, the electrothermal relationship of the channel will be changed, which will affect the accuracy of the junction temperature detection and further affect the power cycling test results. Summary of the invention

[0004] The embodiment of the present invention provides a SiC MOSFET power cycle test gate dynamic bias control method and control terminal to solve the problem in the prior art that the channel heating junction temperature is inaccurately monitored, which affects the power cycle test results.

[0005] In a first aspect, an embodiment of the present invention provides a method for controlling a gate dynamic bias of a SiC MOSFET power cycle test, comprising:

[0006] Repeatedly perform multiple cycles of power cycling test;

[0007] Obtain the junction temperature of each cycle, and determine the aging condition of the target MOSFET based on the change of junction temperature in each cycle;

[0008] Among them, a cycle of power cycle test includes:

[0009] Applying a forward bias voltage of a first preset duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the temperature of the target MOSFET rises to reach thermal equilibrium;

[0010] Applying a reverse bias voltage of a second preset duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET, so that the temperature of the MOSFET is reduced to reach thermal equilibrium, detecting a threshold voltage when the target MOSFET reaches thermal equilibrium, and recording it as a first threshold voltage;

[0011] Determine the forward bias duration of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle and the first threshold voltage of the current cycle, and use the forward bias duration of the current cycle as the new third duration;

[0012] A forward bias voltage of a third duration is applied to the gate of the target MOSFET, and the drain current of the target MOSFET is turned off. The threshold voltage of the target MOSFET is detected at the end of the third duration and recorded as the second threshold voltage.

[0013] In a second aspect, an embodiment of the present invention provides a control terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the SiC MOSFET power cycle test gate dynamic bias control method provided in the first aspect or any possible implementation of the first aspect are implemented.

[0014] The embodiment of the present invention provides a SiC MOSFET power cycle test gate dynamic bias control method and a control terminal. The method includes: repeatedly performing a multi-cycle power cycle test; obtaining the junction temperature of each cycle, and determining the aging condition of the target MOSFET according to the change of the junction temperature of each cycle; wherein, a cycle of the power cycle test includes: applying a forward bias voltage of a first preset duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the target MOSFET is heated up to reach thermal equilibrium; applying a reverse bias voltage of a second preset duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET, so that the MOSFET is cooled down to reach thermal equilibrium, detecting the threshold voltage when the target MOSFET reaches thermal equilibrium, and recording it as the first threshold voltage; determining the forward bias duration of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle and the first threshold voltage of the current cycle, and using the forward bias duration of the current cycle as a new third duration; applying a forward bias voltage of a third duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET, detecting the threshold voltage of the target MOSFET at the end of the third duration, and recording it as the second threshold voltage. Compared with the traditional test method, the one-cycle test of the present application also includes a turn-on cycle and a turn-off cycle, but a reverse bias voltage is applied to the gate of the target MOSFET during the turn-off cycle to balance the influence of the forward bias voltage during the turn-on cycle, so that the threshold voltage remains stable; and a forward bias voltage is applied to the gate of the target MOSFET before the start of the next cycle. At the same time, the forward bias duration of the current cycle is dynamically adjusted according to the parameters of the previous cycle, so that the gate oxide charge state is at a similar level, each cycle test cycle is stable, and the comparability between the measurement results of each test cycle is improved. Based on the above, the drift of the threshold voltage can be effectively suppressed, so that the threshold voltage remains relatively stable throughout the test cycle, thereby improving the accuracy of threshold voltage monitoring and junction temperature monitoring. More accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 It is a flow chart of an implementation method of a SiC MOSFET power cycle test gate dynamic bias control method provided by an embodiment of the present invention;

[0017] Figure 2is a flow chart of implementing a power cycle test provided by an embodiment of the present invention;

[0018] Figure 3 1 is a schematic structural diagram of a SiC MOSFET power cycle test system provided by an embodiment of the present invention;

[0019] Figure 4 It is a waveform diagram of various parameters during a power cycle test provided by an embodiment of the present invention;

[0020] Figure 5 is a waveform diagram of various parameters during calibration provided by an embodiment of the present invention;

[0021] Figure 6 It is a structural schematic diagram of a gate dynamic bias control device for a SIC MOSFET power cycle test provided by an embodiment of the present invention;

[0022] Figure 7 is a schematic diagram of a control terminal provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0025] See also Figure 1 , which shows a flow chart of a method for controlling a gate dynamic bias of a SiC MOSFET power cycle test provided by an embodiment of the present invention, and at the same time, Figure 2 The following is a flowchart showing the implementation of a power cycle test.

[0026] The above-mentioned SiC MOSFET power cycle test gate dynamic bias control method includes:

[0027] S101: repeatedly performing a multi-cycle power cycle test;

[0028] S102: Obtaining the junction temperature of each cycle, and determining the aging condition of the target MOSFET according to the change of the junction temperature of each cycle;

[0029] A cycle of power cycling test includes:

[0030] S1011: applying a forward bias voltage of a first preset duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the temperature of the target MOSFET rises to reach thermal equilibrium;

[0031] S1012: applying a reverse bias voltage of a second preset duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET, so that the temperature of the MOSFET is reduced to reach thermal equilibrium, detecting a threshold voltage when the target MOSFET reaches thermal equilibrium, and recording it as a first threshold voltage;

[0032] S1013: determining a forward bias duration of a current cycle according to a first threshold voltage of a previous cycle, a second threshold voltage of a previous cycle, and a first threshold voltage of a current cycle, and using the forward bias duration of the current cycle as a new third duration;

[0033] S1014: applying a forward bias voltage of a third duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET, detecting a threshold voltage of the target MOSFET at the end of the third duration, and recording it as a second threshold voltage.

[0034] In the embodiment of the present invention, reference Figure 4 ,A cycle includes: an on-cycle and an off-cycle;

[0035] During the start-up period, a forward bias voltage of a first preset duration is applied to the gate of the target MOSFET, and a thermal heating current (I load ), so that the channel generates electrothermal power, monitors the shell temperature, and within the first preset duration, the device can reach thermal equilibrium at the specified maximum junction temperature. During the shutdown cycle, the drain current of the target MOSFET is turned off, and as the device cools down, a reverse bias voltage is applied to the gate of the target MOSFET, so that the target MOSFET re-reaches thermal equilibrium at the ambient temperature or the heat sink temperature, and the influence of the forward bias voltage during the start-up cycle is balanced to keep the threshold voltage stable; thereafter, a forward bias voltage is applied again during the shutdown cycle, and the forward bias duration of the current cycle is dynamically adjusted according to the parameters of the previous cycle, so that the gate oxide charge state is at a close level, each cycle test cycle is stable, and the comparability between the measurement results of each test cycle is improved. As a result, the drift of the threshold voltage can be effectively suppressed, so that the threshold voltage remains relatively stable throughout the test cycle, thereby improving the accuracy of threshold voltage monitoring and more accurate junction temperature monitoring.

[0036] Specifically, Figure 3 A schematic diagram of the structure of a MOSFET power cycle test system is shown; the MOSFET power cycle test system includes: a shell temperature (T c) monitoring part, gate voltage control and threshold voltage test part, drain voltage control and drain current test part, junction temperature (T j ) monitoring part and control terminal.

[0037] 1. Shell temperature monitoring part

[0038] Including DC power supply (V test ), matching detection instruments and thermistors; the thermistor can be a thermocouple or other thermosensitive electrical element, which converts the temperature into an electrical signal and inputs it into the control terminal through the detection instrument. The setting of the shell temperature collection point is different in different test systems. In the air-cooled system, it is directly installed on the heat dissipation substrate of the target MOSFET shell; in the water-cooled system, because the temperature of the water-cooled plate is basically constant, it is necessary to add appropriate heat sink components between the water-cooled plate and the heat dissipation substrate of the target MOSFET shell, such as silicone pads, high-temperature resistant plastic plates, etc., so that a certain temperature difference can be generated between the heat dissipation substrate and the water-cooled plate. If no additional heat sink components are added, the shell temperature collection point is set at the solder joint, lead-out terminal, etc. on the side away from the water-cooled plate, so that the collected shell temperature changes slightly with the junction temperature fluctuation. The purpose of shell temperature monitoring is to confirm the thermal balance state of the target MOSFET. According to the needs of the test design, the thermal resistance during the test can also be calculated based on the power, junction temperature, and shell temperature monitoring results of the target MOSFET at the highest junction temperature.

[0039] 2. Gate voltage control and threshold voltage test part

[0040] Includes adjustable programmable power supply (V GS ) and matching detection instruments to achieve the following functions: ① Apply the on-gate voltage in the on cycle to control the channel to open. A voltage value lower than the maximum gate voltage can be applied to make the channel incompletely open to increase the thermal power. ② Test the threshold voltage in the off cycle. There are multiple test modes. When the second switch K2 is placed in position 4, V GS The voltage is scanned until the drain current reaches the specified value and the threshold voltage is read. GS Directly apply a constant current to read the threshold voltage; when the second switch K2 is placed in position 3 (or position 3 is always turned on), V DS Apply a constant voltage, and V GS Perform voltage scanning until the drain current reaches the specified value and then read the threshold voltage. ③ Apply reverse bias voltage during the off cycle to keep the threshold voltage stable. ④ Apply gate voltage to open the channel during junction temperature monitoring, and cooperate with the junction temperature monitoring part to complete the corresponding function.

[0041] 3. Leakage voltage control and drain current test part

[0042] Includes a high power supply (V DS) and a matching detection instrument. During the start-up cycle, a heating current (I load ), the threshold voltage test is completed in the off cycle of some modes in conjunction with the gate voltage control and threshold voltage test part.

[0043] 4. Junction temperature (Tj) monitoring part

[0044] Includes: A programmable power supply (i s , which can usually be a small current source) and a matching detection instrument group. Based on the pre-calibrated temperature curve, the gate voltage control and threshold voltage test part of the off-cycle applies a voltage to open the channel, and then applies a mA-level sensing current (I sense ), test the forward conduction voltage drop under small current, and implement electrical junction temperature monitoring as a temperature-sensitive parameter.

[0045] 5. Control Terminal

[0046] The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0047] Collect test data, and execute steps S101 to S102 to control the power cycle test. For example, control each power supply to apply a specified voltage and current, collect case temperature, threshold voltage, and junction temperature monitoring data, and calculate thermal resistance based on the case temperature and junction temperature monitoring data.

[0048] In a possible implementation, S1013 may include:

[0049] 1. Determine the feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle and the third duration of the previous cycle;

[0050] 2. Determine the forward bias duration of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage and the first threshold voltage of the current cycle;

[0051] 3. The forward bias duration of the current cycle is used as the new third duration.

[0052] In the embodiment of the present invention, a feedback coefficient is determined according to the first threshold voltage of the previous cycle and the second threshold voltage of the previous cycle, and is applied to the current cycle. Iterative feedback is introduced during the power cycle process to maintain the threshold voltage in a stable state.

[0053] In a possible implementation, determining the feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the third duration of the previous cycle may include:

[0054] (1) determining a feedback coefficient of a current cycle according to a first threshold voltage of a previous cycle, a second threshold voltage of a previous cycle, and a third duration of a previous cycle in combination with a first formula;

[0055] The first formula can be:

[0056] k i =(V TH2(i-1) -V TH1(i-1) ) / lnt i-1

[0057] Among them, k i is the feedback coefficient of the ith cycle, V TH2(i-1) is the second threshold voltage of the i-1th cycle, V TH1(i-1) is the threshold voltage of the i-1th cycle, t i-1 is the third duration of the i-1th cycle; i=1,2,3,….

[0058] More specifically, since the change in the second threshold voltage relative to the first threshold voltage reflects the drift of the threshold voltage, the present application determines the feedback coefficient based on the difference between the second threshold voltage and the first threshold voltage, and acts on the next cycle, thereby effectively suppressing the drift of the voltage threshold.

[0059] In a possible implementation, determining the forward bias duration of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage, and the first threshold voltage of the current cycle may include:

[0060] (1) determining the forward bias duration of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage and the first threshold voltage of the current cycle in combination with the second formula;

[0061] The second formula may include:

[0062] t i =exp((V TH0 -V TH1i ) / k i )

[0063] Among them, t i is the forward bias duration of the ith cycle, V TH0 is the reference threshold voltage, V TH1i is the first threshold voltage of the ith cycle, k i is the feedback coefficient of the ith cycle.

[0064] In combination with the feedback coefficient determined in the above embodiment, the embodiment of the present invention adjusts the forward bias duration based on the reference threshold voltage, thereby effectively suppressing the drift of the threshold voltage.

[0065] In a possible implementation, before S101, the method may further include:

[0066] S103: Apply a forward bias voltage of a fourth preset duration to the gate of the target MOSFET, and provide a sensing current (I sense ), so that the target MOSFET is heated up to reach thermal equilibrium, and the threshold voltage of the target MOSFET when it reaches thermal equilibrium is detected as the reference threshold voltage.

[0067] refer to Figure 4 The embodiment of the present invention also sets a cycle pre-processing before the cycle starts, applies a forward bias voltage to the gate of the target MOSFET, and provides a sensing current (I sense ), determine the reference threshold voltage.

[0068] Specifically, refer to Figure 3 and Figure 4 , control the first switch K1 to be in position 1, and control the second switch K2 to be in position 3, to provide a sensing current (I sense ), and provide a high value of forward bias voltage for the gate. At the end of the cyclic pretreatment, control the second switch K2 to be placed in position 4, and provide a low value of forward bias voltage for the gate, detect the threshold voltage, and use it as the reference threshold voltage.

[0069] In a possible implementation manner, before S101 and after S103, the method may further include:

[0070] S104: Determine a value of a second preset time length according to the reference threshold voltage.

[0071] In a possible implementation manner, the absolute value of the reverse bias voltage may be greater than the absolute value of the forward bias voltage.

[0072] The reverse bias stress should be slightly stronger than the forward bias stress in the turn-on cycle, that is, the reverse drift of the threshold voltage should be greater. Therefore, the reverse bias duration in the turn-off cycle can be adjusted according to the reference threshold voltage to make the control more reasonable.

[0073] Specifically, in a possible implementation, S104 may include:

[0074] S1041: Setting the initial value of the fifth duration;

[0075] S1042: applying a forward bias voltage of a first preset duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the temperature of the target MOSFET rises to reach thermal equilibrium;

[0076] S1043: applying a reverse bias voltage of a fifth duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET, so that the temperature of the MOSFET is reduced to reach thermal equilibrium, detecting a threshold voltage when the target MOSFET reaches thermal equilibrium, and recording the threshold voltage as a third threshold voltage;

[0077] S1044: applying a forward bias voltage of a sixth preset duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET; wherein the sixth preset duration is the initial value of the third duration

[0078] S1045: If the third threshold voltage is less than the reference threshold voltage, the current fifth time duration is used as the second preset time duration, and a step of repeatedly performing a multi-cycle power cycle test is performed;

[0079] S1046: If the third threshold voltage is not less than the reference threshold voltage, the fifth time duration is increased, and the process jumps to applying a forward bias voltage of a first preset time duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the step of heating the target MOSFET to reach thermal equilibrium continues.

[0080] The steps in the same power cycle test are first set to the initial value of the reverse bias duration, and then the threshold voltage after reverse bias, that is, the third threshold voltage, is monitored; if the third threshold voltage is not less than the reference threshold voltage, it means that the reverse bias stress is less than the forward bias stress in the turn-on cycle, and the reverse bias duration needs to be increased. Thus, after multiple cycles of trial and error, a reasonable reverse bias duration is obtained, which is applied to subsequent power cycle tests as the reverse bias duration in the turn-off cycle.

[0081] It should be noted that the above steps do not describe in detail the electrical states of the gate and drain of the target MOSFET during the threshold voltage test. Figure 4 The waveform diagram of each parameter in the complete cycle including the cycle pre-processing is shown; Figure 4 When measuring the threshold voltage, a low forward bias voltage is applied to the gate of the target MOSFET, the drain current of the target MOSFET is turned off, and the threshold voltage is measured. When the device is heated, a high forward bias voltage is applied to the gate of the target MOSFET.

[0082] At the same time, the above steps also include junction temperature monitoring. Figure 4 , at the beginning and end of the shutdown cycle, the junction temperature is monitored, a high value of forward bias voltage is applied to the gate of the target MOSFET, and a sense current (I sense ).

[0083] In a possible implementation, the forward bias voltage is less than a channel conduction voltage value of the target MOSFET and greater than a preset voltage.

[0084] The forward bias voltage can be slightly smaller than the channel conduction voltage of the target MOSFET, so that the channel of the target MOSFET is not fully opened, increasing the thermal power; at the same time, the forward bias voltage cannot be too low so that the channel cannot be completely opened.

[0085] In a possible implementation, the above method may further include:

[0086] S105: Calibrate the target MOSFET;

[0087] Specifically, refer to Figure 5 ,The calibration process specifically includes: calibration pretreatment and temperature calibration.

[0088] 1. Calibration Preprocessing

[0089] The purpose of calibration pretreatment is to apply bias stress to the gate of the target MOSFET for a period of time to keep the threshold voltage at a high value within the short-term variation range; calibration pretreatment is to apply a forward bias voltage to the gate of the target MOSFET and a sensing current (I sense ), during which the junction temperature is continuously monitored and the case temperature of the target MOSFET is controlled to rise by a hot plate or other temperature control equipment. The junction temperature also rises accordingly and is maintained for a period of time after reaching the maximum temperature required for the test.

[0090] refer to Figure 3 and Figure 5 , the first switch K1 can be controlled to be in position 1, and the second switch K2 can be controlled to be in position 3. s Apply a constant sensing current (I sense ), and through V GS A constant high value forward bias voltage is applied to the gate. Specifically, at this time V GS It can be 9V~15V.

[0091] 2. Temperature calibration;

[0092] Keep the electrical state of the gate and drain of the target MOSFET unchanged, gradually reduce the temperature at certain intervals, monitor the on-voltage that reaches thermal equilibrium at each temperature, and establish an on-voltage-temperature relationship curve until the lowest test temperature (normal temperature or the temperature of the heat sink used in the test) is reached and thermal equilibrium is achieved.

[0093] For details, please refer to Figure 3 and Figure 5, continue to control the first switch K1 to position 1, the second switch K2 to position 3, keep the electrical state of the gate and drain of the target MOSFET unchanged, and s Apply a constant sensing current (I sense ), and through V GS Apply a constant forward bias voltage to the gate of the target MOSFET.

[0094] It should be noted that the thermal resistance of the target MOSFET can be calculated by the power when the target MOSFET is heated and the junction temperature and case temperature (or other reference point temperature) at the highest temperature point in the thermal equilibrium state, or it can be determined by the inflection point of the thermal resistance-heat capacity cooling curve fitted by real-time monitoring data of the cooling process.

[0095] refer to Figure 4 , applying a sense current (I sense ) and heating current (I load ) when the gate bias voltage (V GS ) can be the same or different. For example, applying a heating current (I load ) with a lower gate bias voltage and a sense current (I sense ) is used with a higher gate bias voltage in order to apply a heating current (I load ) increases the on-resistance of the channel, making the smaller heating current (I load ) can generate sufficient temperature rise; and applying the sensing current (I sense ) when a higher gate bias voltage is used. At this time, the on-voltage needs to be tested. The on-voltage is affected by the difference between the gate bias voltage and the threshold voltage. When the gate bias voltage is higher, the absolute value of the difference also increases. When the threshold voltage fluctuation value is constant, the relative amount of its change will decrease, which is beneficial to further reduce the influence of the on-voltage on the threshold voltage fluctuation.

[0096] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0097] The following is an embodiment of the device of the present invention. For details not described in detail therein, reference may be made to the corresponding method embodiment described above.

[0098] Figure 6 The structure diagram of the SiC MOSFET power cycle test gate dynamic bias control device provided by the embodiment of the present invention is shown. For the convenience of explanation, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0099] like Figure 6 As shown, the SiC MOSFET power cycle test gate dynamic bias control device includes:

[0100] A cycle test module 21, used for repeatedly performing a multi-cycle power cycle test;

[0101] The aging status output module 22 is used to obtain the junction temperature of each cycle and determine the aging status of the target MOSFET according to the change of the junction temperature of each cycle.

[0102] The cycle test module 21 may include:

[0103] A first start-up unit is used to apply a forward bias voltage of a first preset duration to the gate of the target MOSFET and provide a thermal heating current to the drain of the target MOSFET so that the temperature of the target MOSFET rises to reach thermal equilibrium;

[0104] A first shutdown reverse bias unit is used to apply a reverse bias voltage of a second preset duration to the gate of the target MOSFET and shut off the drain current of the target MOSFET so that the MOSFET is cooled down to reach thermal equilibrium, and a threshold voltage when the target MOSFET reaches thermal equilibrium is detected and recorded as a first threshold voltage;

[0105] A bias time updating unit, used to determine the forward bias duration of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle and the first threshold voltage of the current cycle, and use the forward bias duration of the current cycle as a new third duration;

[0106] The first shutdown forward bias unit is used to apply a forward bias voltage of a third duration to the gate of the target MOSFET and shut off the drain current of the target MOSFET, and detect the threshold voltage of the target MOSFET at the end of the third duration and record it as the second threshold voltage.

[0107] In a possible implementation, the offset time updating unit may include:

[0108] A feedback coefficient determination subunit, used to determine the feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle and the third duration of the previous cycle;

[0109] A bias duration determination subunit, used to determine the forward bias duration of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage and the first threshold voltage of the current cycle;

[0110] The parameter updating subunit is used to take the forward bias duration of the current cycle as the new third duration.

[0111] In a possible implementation manner, the feedback coefficient determination subunit may be specifically used to: determine the feedback coefficient of the current cycle in combination with the first formula according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the third duration of the previous cycle;

[0112] The first formula can be:

[0113] k i =(V TH2(i-1) -V TH1(i-1) ) / lnt i-1

[0114] Among them, k i is the feedback coefficient of the ith cycle, V TH2(i-1) is the second threshold voltage of the i-1th cycle, V TH1(i-1) is the threshold voltage of the i-1th cycle, t i-1 is the third duration of the i-1th cycle; i=1,2,3,….

[0115] In a possible implementation manner, the bias duration determination subunit may be specifically used to: determine the forward bias duration of the current cycle in combination with the second formula according to the feedback coefficient of the current cycle, the reference threshold voltage and the first threshold voltage of the current cycle;

[0116] The second formula may include:

[0117] t i =exp((V TH0 -V TH1i ) / k i )

[0118] Among them, t i is the forward bias duration of the ith cycle, V TH0 is the reference threshold voltage, V TH1i is the first threshold voltage of the ith cycle, k i is the feedback coefficient of the ith cycle.

[0119] In a possible implementation manner, the above device may further include:

[0120] A reference threshold voltage determination module is used to apply a forward bias voltage of a fourth preset duration to the gate of the target MOSFET and provide a sensing current to the drain of the target MOSFET so that the temperature of the target MOSFET rises to reach thermal equilibrium, and detect the threshold voltage of the target MOSFET when it reaches thermal equilibrium as the reference threshold voltage.

[0121] In a possible implementation manner, the above device may further include:

[0122] The second preset time length determination module is used to determine the value of the second preset time length according to the reference threshold voltage.

[0123] In a possible implementation, the second preset duration determining module may include:

[0124] An initialization unit, used to set an initial value of the fifth duration;

[0125] A second start-up unit is used to apply a forward bias voltage of a first preset duration to the gate of the target MOSFET and provide a thermal heating current to the drain of the target MOSFET so that the temperature of the target MOSFET rises to reach thermal equilibrium;

[0126] A first closing reverse bias unit is used to apply a reverse bias voltage of a fifth duration to the gate of the target MOSFET and to shut off the drain current of the target MOSFET so that the MOSFET is cooled down to reach thermal equilibrium, and a threshold voltage when the target MOSFET reaches thermal equilibrium is detected and recorded as a third threshold voltage;

[0127] The second shutdown forward bias unit is used to apply a forward bias voltage of a sixth preset duration to the gate of the target MOSFET and shut down the drain current of the target MOSFET; wherein the sixth preset duration is the initial value of the third duration

[0128] A first judgment unit, configured to use the current fifth time duration as a second preset time duration if the third threshold voltage is less than the reference threshold voltage, and to perform a step of repeatedly performing a multi-cycle power cycle test;

[0129] The second judgment unit is used to increase the fifth time duration if the third threshold voltage is not less than the reference threshold voltage, and jump to apply a forward bias voltage of a first preset time duration to the gate of the target MOSFET, and provide a thermal heating current to the drain of the target MOSFET, so that the step of heating the target MOSFET to reach thermal equilibrium continues to be executed.

[0130] In a possible implementation manner, the absolute value of the reverse bias voltage may be greater than the absolute value of the forward bias voltage.

[0131] In a possible implementation, the forward bias voltage is less than a channel conduction voltage value of the target MOSFET and greater than a preset voltage.

[0132] Figure 7 Schematic diagram of the control terminal 3 provided in the embodiment of the present invention. Figure 7As shown, the control terminal 3 of this embodiment includes: a processor 30 and a memory 31. The memory 31 is used to store a computer program 32, and the processor 30 is used to call and run the computer program 32 stored in the memory 31 to execute the steps in the above-mentioned embodiments of the gate dynamic bias control method for SiC MOSFET power cycle test, for example Figure 1 Alternatively, the processor 30 is used to call and run the computer program 32 stored in the memory 31 to implement the functions of each module / unit in the above-mentioned device embodiments, such as Figure 6 The functions of modules 21 to 22 are shown.

[0133] Exemplarily, the computer program 32 may be divided into one or more modules / units, one or more modules / units are stored in the memory 31 and executed by the processor 30 to implement the present invention. One or more modules / units may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments are used to describe the execution process of the computer program 32 in the control terminal 3. For example, the computer program 32 may be divided into Figure 6 Modules / units 21 to 23 are shown.

[0134] The control terminal 3 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The control terminal 3 may include, but is not limited to, a processor 30 and a memory 31. Those skilled in the art will appreciate that Figure 7 It is only an example of the control terminal 3 and does not constitute a limitation on the control terminal 3. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the terminal may also include input and output devices, network access devices, buses, etc.

[0135] The processor 30 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0136] The memory 31 may be an internal storage unit of the control terminal 3, such as a hard disk or memory of the control terminal 3. The memory 31 may also be an external storage device of the control terminal 3, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the control terminal 3. Further, the memory 31 may also include both an internal storage unit of the control terminal 3 and an external storage device. The memory 31 is used to store computer programs and other programs and data required by the terminal. The memory 31 may also be used to temporarily store data that has been output or is to be output.

[0137] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0138] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0139] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0140] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0141] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0142] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0143] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. Computer-readable media may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0144] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A method for controlling gate dynamic bias of a SiC MOSFET power cycle test, characterized in that: include: Repeatedly perform multiple cycles of power cycling test; Obtaining the junction temperature of each cycle, and determining the aging condition of the target MOSFET according to the change of the junction temperature of each cycle; Among them, a cycle of power cycle test includes: Applying a forward bias voltage of a first preset duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the temperature of the target MOSFET rises to reach thermal equilibrium; Applying a reverse bias voltage of a second preset duration to the gate of the target MOSFET, and shutting off the drain current of the target MOSFET, so that the temperature of the MOSFET is reduced to reach thermal equilibrium, detecting a threshold voltage when the target MOSFET reaches thermal equilibrium, and recording it as a first threshold voltage; Determine the forward bias duration of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the first threshold voltage of the current cycle, and use the forward bias duration of the current cycle as the new third duration; A forward bias voltage of the third duration is applied to the gate of the target MOSFET, and the drain current of the target MOSFET is turned off. The threshold voltage of the target MOSFET is detected at the end of the third duration and recorded as the second threshold voltage.

2. The SiC MOSFET power cycle test gate dynamic bias control method according to claim 1, characterized in that: The step of determining the forward bias duration of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the first threshold voltage of the current cycle, and taking the forward bias duration of the current cycle as the new third duration, comprises: Determining a feedback coefficient of a current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the third duration of the previous cycle; Determining a forward bias duration of the current cycle according to a feedback coefficient of the current cycle, a reference threshold voltage, and a first threshold voltage of the current cycle; The forward bias duration of the current cycle is used as the new third duration.

3. The SiC MOSFET power cycle test gate dynamic bias control method according to claim 2, characterized in that: The step of determining the feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the third duration of the previous cycle includes: Determining a feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the third duration of the previous cycle in combination with a first formula; The first formula is: to i =(V TH2(i-1) -V TH1(i-1) ) / int i-1 Among them, k i is the feedback coefficient of the ith cycle, V TH2(i-1) is the second threshold voltage of the i-1th cycle, V TH1(i-1) is the threshold voltage of the i-1th cycle, t i-1 is the third duration of the i-1th cycle; i=1,2,3,….

4. The SiC MOSFET power cycle test gate dynamic bias control method according to claim 3, characterized in that: Determining the forward bias duration of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage and the first threshold voltage of the current cycle includes: Determining the forward bias duration of the current cycle in combination with a second formula according to the feedback coefficient of the current cycle, the reference threshold voltage and the first threshold voltage of the current cycle; The second formula includes: t i =exp((V TH0 -V TH1i ) / k i ) Among them, t i is the forward bias duration of the ith cycle, V TH0 is the reference threshold voltage, V TH1i is the first threshold voltage of the ith cycle, k i is the feedback coefficient of the ith cycle.

5. The SiC MOSFET power cycle test gate dynamic bias control method according to claim 2, characterized in that: Before repeatedly performing the multi-cycle power cycle test, the method further includes: A forward bias voltage of a fourth preset duration is applied to the gate of the target MOSFET, and a sensing current is provided to the drain of the target MOSFET, so that the temperature of the target MOSFET rises to reach thermal equilibrium, and a threshold voltage of the target MOSFET when reaching thermal equilibrium is detected as the reference threshold voltage.

6. The SiC MOSFET power cycle test gate dynamic bias control method according to claim 5, characterized in that: Before repeatedly performing the multi-cycle power cycle test, and applying a forward bias voltage of a fourth preset duration to the gate of the target MOSFET, and providing a sensing current to the drain of the target MOSFET so that the temperature of the target MOSFET rises to reach thermal equilibrium, and detecting a threshold voltage of the target MOSFET when the target MOSFET reaches thermal equilibrium as the reference threshold voltage, the method further includes: The value of the second preset time duration is determined according to the reference threshold voltage.

7. The SiC MOSFET power cycle test gate dynamic bias control method according to claim 6, characterized in that: The determining the value of the second preset time length according to the reference threshold voltage includes: Set the initial value of the fifth duration; Applying a forward bias voltage of the first preset duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the temperature of the target MOSFET rises to reach thermal equilibrium; Applying the reverse bias voltage of the fifth duration to the gate of the target MOSFET, and turning off the drain current of the target MOSFET, so that the temperature of the MOSFET is reduced to reach thermal equilibrium, detecting a threshold voltage when the target MOSFET reaches thermal equilibrium, and recording it as a third threshold voltage; Apply a forward bias voltage of a sixth preset duration to the gate of the target MOSFET and turn off the drain current of the target MOSFET; wherein the sixth preset duration is the initial value of the third duration If the third threshold voltage is less than the reference threshold voltage, the current value of the fifth time duration is used as the second preset time duration, and the step of repeatedly performing the multi-cycle power cycle test is performed; If the third threshold voltage is not less than the reference threshold voltage, the fifth duration is increased, and the process jumps to applying the forward bias voltage of the first preset duration to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the step of heating the target MOSFET to reach thermal equilibrium continues.

8. The SiC MOSFET power cycle test gate dynamic bias control method according to any one of claims 1 to 7, characterized in that: An absolute value of the reverse bias voltage is greater than an absolute value of the forward bias voltage.

9. The SiC MOSFET power cycle test gate dynamic bias control method according to any one of claims 1 to 7, characterized in that: The forward bias voltage is less than a channel conduction voltage value of the target MOSFET and greater than a preset voltage.

10. A control terminal, characterized in that: The invention comprises a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory, and when executed, the steps of the method for controlling the gate dynamic bias of the SiC MOSFET power cycle test are implemented as described in any one of claims 1 to 9 above.

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