SiC MOSFET power cycle test gate dynamic bias control method and control terminal

Abstract

The application provides a SiC MOSFET power cycle test gate dynamic bias control method and a control terminal. The method comprises the following steps: in a power cycle test of one cycle, a reverse bias voltage is applied to the gate of a target MOSFET in the off period of the power cycle, the influence of the forward bias voltage in the on period is balanced, the threshold voltage is kept stable, and a forward bias voltage is applied to the gate of the target MOSFET before the next cycle starts, and meanwhile, the forward bias duration of the current cycle is dynamically adjusted according to the parameters of the last cycle, so that the gate oxide charge state is close to the level, each cycle test period is stable, and the comparability between the measurement results of each test period is improved. Based on the above, the drift of the threshold voltage can be effectively inhibited, the threshold voltage is kept relatively stable in the whole test period, and the accuracy of the threshold voltage monitoring is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor performance detection, and particularly relates to a SiC MOSFET power cycle test gate dynamic bias control method and a control terminal. BACKGROUND

[0002] The power cycle test applies a cycle of turn-on and turn-off electrical stress to the measured device. A complete test cycle includes the sum of the turn-on period and the turn-off period, and the device junction temperature rises in the turn-on period and drops in the turn-off period. The power cycle test plays an important role in the SiC MOSFET reliability test system, and the key test condition is the junction temperature. Accurate detection of the junction temperature is a basic requirement of the power cycle test.

[0003] In the prior art, the power cycle test is usually performed by channel heating, and the junction temperature is monitored according to the electrical-thermal relationship of the channel. However, the power cycle test stress will cause a positive shift of the threshold voltage, thereby changing the electrical-thermal relationship of the channel and affecting the accuracy of the junction temperature detection, and further affecting the power cycle test result. SUMMARY

[0004] Embodiments of the present application provide a SiC MOSFET power cycle test gate dynamic bias control method and a control terminal to solve the problem in the prior art that the channel heating junction temperature monitoring is inaccurate and affects the power cycle test result.

[0005] In a first aspect, embodiments of the present application provide a SiC MOSFET power cycle test gate dynamic bias control method, comprising:

[0006] repeating the power cycle test of multiple cycles;

[0007] obtaining the junction temperature of each cycle, and determining the aging condition of the target MOSFET according to the junction temperature change of each cycle;

[0008] The power cycle test of one cycle includes:

[0009] applying a first preset duration of forward bias voltage to the gate of the target MOSFET, and providing a heat heating current to the drain of the target MOSFET, so that the target MOSFET warms up to thermal equilibrium;

[0010] applying a second preset duration of reverse bias voltage to the gate of the target MOSFET, and turning off the drain current of the target MOSFET, so that the MOSFET cools down to thermal equilibrium, detecting the threshold voltage of the target MOSFET when it reaches thermal equilibrium, and recording it as the first threshold voltage;

[0011] determining the forward bias duration of the current period according to the first threshold voltage of the last period, the second threshold voltage of the last period and the first threshold voltage of the current period, and taking the forward bias duration of the current period as a new third duration;

[0012] applying a forward bias voltage of the third duration to the gate of the target MOSFET and turning off the drain current of the target MOSFET, detecting the threshold voltage of the target MOSFET at the moment when the third duration ends and recording the threshold voltage as a second threshold voltage.

[0013] In a second aspect, an embodiment of the present application provides a control terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the steps of the SiC MOSFET power cycle test gate dynamic bias control method provided in the first aspect or any possible implementation manner of the first aspect are implemented.

[0014] The embodiment of the present application provides a SiC MOSFET power cycle test gate dynamic bias control method and a control terminal. The method comprises the following steps: repeatedly performing power cycle tests for multiple periods; obtaining the junction temperature of each period, and determining the aging condition of the target MOSFET according to the junction temperature change of each period; wherein the power cycle test of one period comprises the following steps: applying a first preset duration of forward bias voltage to the gate of the target MOSFET, and providing a hot heating current to the drain of the target MOSFET, so that the target MOSFET is heated to thermal equilibrium; applying a second preset duration of reverse bias voltage to the gate of the target MOSFET, and turning off the drain current of the target MOSFET, so that the MOSFET is cooled to thermal equilibrium, the threshold voltage of the target MOSFET when reaching thermal equilibrium is detected and recorded as the first threshold voltage; determining the forward bias duration of the current period according to the first threshold voltage of the last period, the second threshold voltage of the last period and the first threshold voltage of the current period, and taking the forward bias duration of the current period as a new third duration; applying a third duration of forward bias voltage to the gate of the target MOSFET, and turning off the drain current of the target MOSFET, detecting the threshold voltage of the target MOSFET at the end of the third duration, and recording it as the second threshold voltage. Compared with the traditional test method, the one-cycle test also includes an on period and an off period, but a reverse bias voltage is applied to the gate of the target MOSFET in the off period, the influence of the forward bias voltage in the on period is balanced, the threshold voltage is kept stable, and the gate oxide charge state is close to the level. The measurement results of each test period are stable, and the comparability between the measurement results of each test period is improved. Based on the above, the drift of the threshold voltage can be effectively suppressed, so that the threshold voltage remains relatively stable in the whole test period, thereby improving the accuracy of threshold voltage monitoring and the accuracy of junction temperature monitoring. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 It is an implementation flowchart of the SiC MOSFET power cycle test gate dynamic bias control method provided by the embodiment of the present application;

[0017] Figure 2is an implementation flowchart of the one power cycle test provided by the embodiment of the present application;

[0018] Figure 3 is a structural schematic diagram of the SiC MOSFET power cycle test system provided by the embodiment of the present application;

[0019] Figure 4 is a waveform diagram of various parameters in the one power cycle test provided by the embodiment of the present application;

[0020] Figure 5 is a waveform diagram of various parameters in the calibration provided by the embodiment of the present application;

[0021] Figure 6 is a structural schematic diagram of the SIC MOSFET power cycle test gate dynamic bias control device provided by the embodiment of the present application;

[0022] Figure 7 is a schematic diagram of the control terminal provided by the embodiment of the present application. DETAILED DESCRIPTION

[0023] In the following description, for the purpose of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0024] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be described by specific embodiments in conjunction with the accompanying drawings.

[0025] Referring to Figure 1 , which shows an implementation flowchart of a SiC MOSFET power cycle test gate dynamic bias control method provided by the embodiment of the present application, and Figure 2 , which shows an implementation flowchart of one cycle of power cycle test. The specific details are as follows:

[0026] The above-mentioned SiC MOSFET power cycle test gate dynamic bias control method includes:

[0027] S101: repeatedly performing power cycle test of multiple cycles;

[0028] S102: obtaining the junction temperature of each cycle, and determining the aging condition of the target MOSFET according to the change of the junction temperature of each cycle;

[0029] One cycle of power cycle test includes:

[0030] S1011: a first preset duration of the gate of the target MOSFET is applied to the positive bias voltage, and the drain of the target MOSFET is provided with a hot heating current, so that the target MOSFET is heated to thermal equilibrium;

[0031] S1012: a second preset duration of the gate of the target MOSFET is applied to the reverse bias voltage, and the drain current of the target MOSFET is turned off, so that the MOSFET is cooled to thermal equilibrium, the threshold voltage of the target MOSFET when reaching thermal equilibrium is detected, and is recorded as the first threshold voltage;

[0032] S1013: according to the first threshold voltage of the last cycle, the second threshold voltage of the last cycle and the first threshold voltage of the current cycle, the forward bias duration of the current cycle is determined, and the forward bias duration of the current cycle is taken as a new third duration;

[0033] S1014: a third duration of the gate of the target MOSFET is applied to the positive bias voltage, and the drain current of the target MOSFET is turned off, and the threshold voltage of the target MOSFET at the end of the third duration is detected and recorded as the second threshold voltage.

[0034] In the embodiment of the application, the reference Figure 4 , one cycle includes: an on period and an off period;

[0035] In the on period, a first preset duration of the gate of the target MOSFET is applied to the positive bias voltage, and the drain of the target MOSFET is provided with a hot heating current (I load ), so that the channel generates electric heating power, and the shell temperature is monitored. In the first preset duration, the device can reach thermal equilibrium at the specified maximum junction temperature. In the off period, the drain current of the target MOSFET is turned off, a reverse bias voltage is applied to the gate of the target MOSFET as the device cools down, so that the target MOSFET re-reaches thermal equilibrium at the ambient temperature or the heat sink temperature, balances the influence of the positive bias voltage in the on period, and keeps the threshold voltage stable; then, in the off period, the positive bias voltage is applied again, and the forward bias duration of the current cycle is dynamically adjusted according to the parameters of the last cycle, so that the gate oxide charge state is close to a level, each cycle test period is stable, and the comparability between the measurement results of each test period is improved. Therefore, the drift of the threshold voltage can be effectively inhibited, so that the threshold voltage remains relatively stable in the entire test period, thereby improving the accuracy of threshold voltage monitoring and the accuracy of junction temperature monitoring.

[0036] Specifically, Figure 3 A structure schematic diagram of a MOSFET power cycle test system is shown; the MOSFET power cycle test system comprises: a shell temperature (T c) monitoring section, gate voltage control and threshold voltage test section, drain voltage control and drain current test section, junction temperature (T j ) monitoring section and control terminal composition.

[0037] I. Shell temperature monitoring section

[0038] Including DC power supply (V test ), supporting detection instrument and thermosensitive element composition; thermosensitive element can be thermocouple or other thermosensitive electrical element, which converts temperature into electrical signal and inputs control terminal through detection instrument. Shell temperature collection point is set differently in different test systems, which is directly installed on the heat dissipation base plate of target MOSFET shell in air cooling system; in water cooling system, because the temperature of water cooling plate is basically constant, appropriate heat sink components such as silica gel pad and high-temperature resistant plastic plate need to be added between water cooling plate and heat dissipation base plate of target MOSFET shell, so that a certain temperature difference can be generated between the heat dissipation base plate and the water cooling plate. If no additional heat sink components are added, the shell temperature collection point is set at the welding point and lead-out end away from the water cooling plate, so that the collected shell temperature changes slightly with the junction temperature fluctuation. The purpose of shell temperature monitoring is to confirm the thermal equilibrium state of target MOSFET, and according to the test design needs, the thermal resistance in the test process can also be calculated according to the power, junction temperature and shell temperature monitoring results of target MOSFET at the highest junction temperature.

[0039] II. Gate voltage control and threshold voltage test section

[0040] Including adjustable program-controlled power supply (V GS ) and supporting detection instrument composition, realizing the following functions: ① applying opening gate voltage in opening period to control the opening of channel, which can apply voltage value lower than maximum gate voltage to make the channel not completely open to increase thermal power. ② testing threshold voltage in off period, there are multiple test modes, when the second switch K2 is placed at position 4, V GS can be used for voltage scanning, and the threshold voltage is read out when the drain current reaches the specified value, or V GS can be used to directly apply constant current to read out threshold voltage; when the second switch K2 is placed at position 3 (or makes position 3 always conduct), V DS can be used to apply constant voltage, and V GS can be used for voltage scanning, and the threshold voltage is read out when the drain current reaches the specified value. ③ applying reverse bias voltage in off period to keep threshold voltage stable. ④ applying gate voltage to open channel when monitoring junction temperature, which completes the corresponding functions with junction temperature monitoring section.

[0041] III. Drain voltage control and drain current test section

[0042] Including a power supply (V DS) and a matching detection instrument, in the opening period, a heating current (I load ) is applied to the drain, in the off period, the threshold voltage test is completed by cooperating with the gate voltage control and the threshold voltage test part in the partial mode.

[0043] IV. Junction temperature (Tj) monitoring part

[0044] It comprises a program-controlled power supply (i s , which can usually be a small current source) and a matching detection instrument, on the basis of the pre-calibrated temperature curve, after the channel is opened by the voltage applied by the off period gate voltage control and the threshold voltage test part, a mA-level sensing current (I sense ) is applied, the forward on-voltage drop under small current is tested as the temperature-sensitive parameter to implement electrical junction temperature monitoring.

[0045] V. Control terminal

[0046] It comprises a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0047] Test data is collected, and the steps of S101 to S102 are executed to control the implementation of the power cycle test. For example, the control of each power supply to apply a specified voltage and current, the collection of shell temperature, threshold voltage, and junction temperature monitoring data, and the calculation of thermal resistance according to the shell temperature and junction temperature monitoring data.

[0048] In one possible implementation, S1013 can include:

[0049] 1. Determine the feedback coefficient of the current period according to the first threshold voltage of the last period, the second threshold voltage of the last period, and the third duration of the last period.

[0050] 2. Determine the forward bias duration of the current period according to the feedback coefficient of the current period, the reference threshold voltage, and the first threshold voltage of the current period.

[0051] 3. Take the forward bias duration of the current period as the new third duration.

[0052] In the embodiment of the application, the feedback coefficient is determined according to the first threshold voltage of the last period and the second threshold voltage of the last period, and acts on the current period. An iterative-based feedback is introduced in the power cycle process, so that the threshold voltage is maintained in a stable state.

[0053] In one possible implementation, determining the feedback coefficient of the current period according to the first threshold voltage of the last period, the second threshold voltage of the last period, and the third duration of the last period can include:

[0054] (1) determining the feedback coefficient of the current period according to the first threshold voltage of the last period, the second threshold voltage of the last period and the third time length of the last period, in combination with the first formula;

[0055] The first formula can be:

[0056] k i =(V TH2(i-1) -V TH1(i-1) ) / lnt i-1

[0057] wherein k i is the feedback coefficient of the i-th period, V TH2(i-1) is the second threshold voltage of the (i-1)-th period, V TH1(i-1) is the first threshold voltage of the (i-1)-th period, t i-1 is the third time length of the (i-1)-th period; i=1, 2, 3, ….

[0058] More specifically, since the change of the second threshold voltage relative to the first threshold voltage reflects the drift of the threshold voltage, the present application determines the feedback coefficient based on the difference between the second threshold voltage and the first threshold voltage, and applies the feedback coefficient to the next period, thereby effectively inhibiting the drift of the threshold voltage.

[0059] In a possible implementation, determining the forward bias time length of the current period according to the feedback coefficient of the current period, the reference threshold voltage and the first threshold voltage of the current period can comprise:

[0060] (1) determining the forward bias time length of the current period according to the feedback coefficient of the current period, the reference threshold voltage and the first threshold voltage of the current period, in combination with the second formula;

[0061] The second formula can comprise:

[0062] t i =exp((V TH0 -V TH1i ) / k i )

[0063] wherein t i is the forward bias time length of the i-th period, V TH0 is the reference threshold voltage, V TH1i is the first threshold voltage of the i-th period, and k i is the feedback coefficient of the i-th period.

[0064] In combination with the feedback coefficient determined according to the above embodiment, the present embodiment adjusts the forward bias time length based on the reference threshold voltage, thereby effectively inhibiting the drift of the threshold voltage.

[0065] In a possible implementation, before S101, the method can further include:

[0066] S103: applying a fourth preset duration of forward bias voltage to the gate of the target MOSFET, and providing a sensing current (I sense ) to the drain of the target MOSFET, so that the target MOSFET is warmed up to thermal equilibrium, and detecting the threshold voltage of the target MOSFET when the target MOSFET reaches the thermal equilibrium as a reference threshold voltage.

[0067] With reference to Figure 4 , the embodiment of the present application further sets a cycle pretreatment before the cycle starts, applies a forward bias voltage to the gate of the target MOSFET, and provides a sensing current (I sense ) to the drain of the target MOSFET, to determine the reference threshold voltage.

[0068] Specifically, with reference to Figure 3 and Figure 4 , the first switch K1 is controlled to be in position 1, and the second switch K2 is controlled to be in position 3, to provide the sensing current (I sense ) to the drain of the target MOSFET, and provide a high value of forward bias voltage to the gate of the target MOSFET. When the cycle pretreatment ends, the second switch K2 is controlled to be in position 4, and a low value of forward bias voltage is provided to the gate of the target MOSFET, to detect the threshold voltage as the reference threshold voltage.

[0069] In a possible implementation, before S101, and after S103, the method can further include:

[0070] S104: determining the value of the second preset duration according to the reference threshold voltage.

[0071] In a possible implementation, the absolute value of the reverse bias voltage can be greater than the absolute value of the forward bias voltage.

[0072] The reverse bias stress should be slightly stronger than the forward bias stress in the on period, that is, the threshold voltage reverse drift should be more, and therefore, the reverse bias duration in the off period can be adjusted according to the reference threshold voltage, so that the control is more reasonable.

[0073] Specifically, in a possible implementation, S104 can include:

[0074] S1041: setting an initial value of a fifth duration;

[0075] S1042: applying a first preset duration of forward bias voltage to the gate of the target MOSFET, and providing a thermal heating current to the drain of the target MOSFET, so that the target MOSFET is warmed up to thermal equilibrium;

[0076] S1043: apply a fifth duration of reverse bias voltage to the gate of the target MOSFET, and turn off the drain current of the target MOSFET, so that the MOSFET cools down to thermal equilibrium, detect the threshold voltage of the target MOSFET when it reaches thermal equilibrium, and record it as the third threshold voltage;

[0077] S1044: apply a sixth preset duration of forward bias voltage to the gate of the target MOSFET, and turn off the drain current of the target MOSFET; wherein the sixth preset duration is the initial value of the third duration

[0078] S1045: if the third threshold voltage is less than the reference threshold voltage, then take the current fifth duration as the second preset duration, and execute the steps of repeating the power cycle test for multiple cycles;

[0079] S1046: if the third threshold voltage is not less than the reference threshold voltage, then increase the fifth duration, and jump to the step of applying a first preset duration of forward bias voltage to the gate of the target MOSFET, and providing a hot heating current to the drain of the target MOSFET, so that the target MOSFET warms up to thermal equilibrium.

[0080] As in the steps of the power cycle test, first set the duration of reverse bias to the initial value, then monitor the threshold voltage after reverse bias, that is, the third threshold voltage; if the third threshold voltage is not less than the reference threshold voltage, it means that the reverse bias stress is less than the forward bias stress of the on period, and the duration of reverse bias needs to be increased. Thus, through multiple trial and error cycles, a reasonable reverse bias duration is obtained, which is applied to the subsequent power cycle test as the duration of reverse bias in the off period.

[0081] It should be noted that the above steps do not describe the electrical state of the gate and drain of the target MOSFET in detail during threshold voltage testing. Figure 4 The waveform diagram of each parameter in the complete cycle period including the cycle pretreatment is shown; refer to Figure 4 When measuring the threshold voltage, a low value of forward bias voltage is applied to the gate of the target MOSFET, and the drain current of the target MOSFET is turned off for threshold voltage measurement. When the device is heated, a high value of forward bias voltage is applied to the gate of the target MOSFET.

[0082] At the same time, the above steps also include junction temperature monitoring. Refer to Figure 4 At the beginning of the off period and at the end of the off period, junction temperature monitoring is performed, a high value of forward bias voltage is applied to the gate of the target MOSFET, and a sensing current (I sense ) is provided to the drain of the target MOSFET.

[0083] In one possible implementation, the forward bias voltage is less than the channel turn-on voltage of the target MOSFET, but greater than a preset voltage.

[0084] The forward bias voltage can be slightly less than the channel turn-on voltage of the target MOSFET, so that the channel of the target MOSFET is not fully open, increasing the heat power; at the same time, the forward bias voltage cannot be too low so that the channel cannot be turned on at all.

[0085] In one possible implementation, the above method may further include:

[0086] S105: Calibrate the target MOSFET;

[0087] For details, please refer to Figure 5 The calibration process specifically includes: calibration pretreatment and temperature calibration.

[0088] I. Calibration Preprocessing

[0089] The purpose of calibration preprocessing is to apply bias stress to the gate of the target MOSFET for a period of time, so that the threshold voltage is kept at a high value within a short-term variation range; calibration preprocessing involves applying a forward bias voltage to the gate of the target MOSFET and applying a sensing current (I0) to the drain of the target MOSFET. sense During the test, the junction temperature is continuously monitored, and the case temperature of the target MOSFET is increased by controlling the temperature through a hot plate or other temperature control equipment. The junction temperature also increases accordingly. After reaching the highest temperature required for the test, it is maintained for a period of time.

[0090] refer to Figure 3 and Figure 5 It can control the first switch K1 to position 1 and the second switch K2 to position 3, through i s Apply a constant sensing current (I) sense ), and through V GS A constant high forward bias voltage is applied to the gate. Specifically, V GS It can be 9V to 15V.

[0091] II. Temperature Calibration;

[0092] Keeping the gate and drain electrical states of the target MOSFET unchanged, the temperature is gradually reduced at certain intervals. The turn-on voltage at which thermal equilibrium is reached is monitored at each temperature, and a turn-on voltage-temperature relationship curve is established until the lowest test temperature (room temperature or the temperature of the heat sink used in the test) is reached and thermal equilibrium is achieved.

[0093] For specific details, please refer to the following: Figure 3 and Figure 5, continue to control the first switch K1 to be in position 1, the second switch K2 to be in position 3, keep the electrical state of the gate and the drain of the target MOSFET unchanged, pass i s A constant sensing current (I sense ) is applied, and a V GS is applied to the gate of the target MOSFET.

[0094] It should be noted that the thermal resistance of the target MOSFET can be calculated by the power generated by the target MOSFET when generating electrical power, and the junction temperature and the shell temperature (or other reference point temperature) at the highest temperature point in the thermal equilibrium state, or can be determined by the inflection point of the thermal resistance-thermal capacity cooling curve fitted by the real-time monitoring data in the cooling process.

[0095] Referring to Figure 4 , the gate bias voltage (V GS ) applied when the sensing current (I sense ) and the heating current (I load ) are applied to the target MOSFET can be the same or different. For example, a lower gate bias voltage is used when the heating current (I load ) is applied, and a higher gate bias voltage is used when the sensing current (I sense ) is applied, so as to increase the on-resistance of the channel when the heating current (I load ) is applied, so that sufficient temperature rise can be generated under a smaller heating current (I load ); and a higher gate bias voltage is used when the sensing current (I sense ) is applied, at which time the on-voltage is to be tested, and the on-voltage is affected by the difference between the gate bias voltage and the threshold voltage, when the gate bias voltage is higher, the absolute value of the difference is also increased, and when the threshold voltage fluctuation value is constant, the relative amount of change is reduced, which is beneficial to further reduce the influence of the threshold voltage fluctuation on the on-voltage.

[0096] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0097] The following is a device embodiment of the present application, and for details not described in detail, reference can be made to the corresponding method embodiments described above.

[0098] Figure 6 A structure diagram of a SiC MOSFET power cycle test gate dynamic bias control device provided by an embodiment of the present application is shown, only the parts related to the embodiment of the present application are shown for the convenience of description, and the details are as follows:

[0099] AsFigure 6 As shown, the SiC MOSFET power cycle test gate dynamic bias control device comprises:

[0100] The cycle test module 21 is configured to repeatedly perform a plurality of cycles of power cycle tests.

[0101] The aging condition output module 22 is configured to obtain the junction temperature of each cycle, and determine the aging condition of the target MOSFET according to the change of the junction temperature of each cycle.

[0102] The cycle test module 21 can comprise:

[0103] The first opening unit is configured to apply a first preset duration of forward bias voltage to the gate of the target MOSFET, and provide a hot heating current to the drain of the target MOSFET, so that the target MOSFET is heated to thermal equilibrium.

[0104] The first closing reverse bias unit is configured to apply a second preset duration of reverse bias voltage to the gate of the target MOSFET, and turn off the drain current of the target MOSFET, so that the MOSFET is cooled to thermal equilibrium, and the threshold voltage of the target MOSFET when reaching thermal equilibrium is detected and recorded as the first threshold voltage.

[0105] The bias time updating unit is configured to determine the forward bias duration of the current cycle according to the first threshold voltage of the last cycle, the second threshold voltage of the last cycle, and the first threshold voltage of the current cycle, and take the forward bias duration of the current cycle as a new third duration.

[0106] The first closing forward bias unit is configured to apply a third duration of forward bias voltage to the gate of the target MOSFET, and turn off the drain current of the target MOSFET, and detect the threshold voltage of the target MOSFET at the end of the third duration and record it as the second threshold voltage.

[0107] In a possible implementation, the bias time updating unit can comprise:

[0108] The feedback coefficient determination subunit is configured to determine the feedback coefficient of the current cycle according to the first threshold voltage of the last cycle, the second threshold voltage of the last cycle, and the third duration of the last cycle.

[0109] The bias duration determination subunit is configured to determine the forward bias duration of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage, and the first threshold voltage of the current cycle.

[0110] The parameter updating subunit is configured to take the forward bias duration of the current cycle as a new third duration.

[0111] In a possible implementation, the feedback coefficient determination sub-unit can be specifically configured to determine the feedback coefficient of the current period according to the first threshold voltage of the last period, the second threshold voltage of the last period, and the third time length of the last period, in combination with a first formula.

[0112] The first formula can be:

[0113] k i = (V TH2(i-1) -V TH1(i-1) ) / Int i-1

[0114] wherein k i is the feedback coefficient of the i-th period, V TH2(i-1) is the second threshold voltage of the (i-1)-th period, V TH1(i-1) is the first threshold voltage of the (i-1)-th period, t i-1 is the third time length of the (i-1)-th period; i = 1, 2, 3, ….

[0115] In a possible implementation, the bias time length determination sub-unit can be specifically configured to determine the forward bias time length of the current period according to the feedback coefficient of the current period, the reference threshold voltage, and the first threshold voltage of the current period, in combination with a second formula.

[0116] The second formula can include:

[0117] t i = exp ((V TH0 -V TH1i ) / k i )

[0118] wherein t i is the forward bias time length of the i-th period, V TH0 is the reference threshold voltage, V TH1i is the first threshold voltage of the i-th period, and k i is the feedback coefficient of the i-th period.

[0119] In a possible implementation, the apparatus can further include:

[0120] a reference threshold voltage determination module configured to apply a forward bias voltage to the gate of the target MOSFET for a fourth preset time length, and provide a sensing current to the drain of the target MOSFET, so that the target MOSFET is heated to thermal equilibrium, and detect the threshold voltage of the target MOSFET when the target MOSFET reaches the thermal equilibrium as the reference threshold voltage.

[0121] In a possible implementation, the apparatus can further include:

[0122] The second preset time length determination module is configured to determine a value of the second preset time length according to the reference threshold voltage.

[0123] In a possible implementation, the second preset time length determination module can include:

[0124] The initialization unit is configured to set an initial value of the fifth time length.

[0125] The second opening unit is configured to apply a forward bias voltage of the first preset time length to the gate of the target MOSFET, and provide a hot heating current to the drain of the target MOSFET, so that the target MOSFET is heated to thermal equilibrium.

[0126] The first closing reverse bias unit is configured to apply a reverse bias voltage of the fifth time length to the gate of the target MOSFET, and turn off the drain current of the target MOSFET, so that the MOSFET is cooled to thermal equilibrium, and the threshold voltage when the target MOSFET reaches thermal equilibrium is detected and recorded as the third threshold voltage.

[0127] The second closing forward bias unit is configured to apply a forward bias voltage of the sixth preset time length to the gate of the target MOSFET, and turn off the drain current of the target MOSFET; wherein the sixth preset time length is the initial value of the third time length.

[0128] The first judging unit is configured to, if the third threshold voltage is less than the reference threshold voltage, take the current value of the fifth time length as the second preset time length, and execute the step of repeatedly performing the multi-cycle power cycle test.

[0129] The second judging unit is configured to, if the third threshold voltage is not less than the reference threshold voltage, increase the fifth time length, and jump to the step of applying a forward bias voltage of the first preset time length to the gate of the target MOSFET, and providing a hot heating current to the drain of the target MOSFET, so that the target MOSFET is heated to thermal equilibrium.

[0130] In a possible implementation, the absolute value of the reverse bias voltage can be greater than the absolute value of the forward bias voltage.

[0131] In a possible implementation, the forward bias voltage is less than the channel on-voltage value of the target MOSFET, and greater than the preset voltage.

[0132] Figure 7 is a schematic diagram of the control terminal 3 provided by the embodiment of the present application. As shown in Figure 7As shown, the control terminal 3 of this embodiment includes a processor 30 and a memory 31. The memory 31 is configured to store a computer program 32, and the processor 30 is configured to invoke and run the computer program 32 stored in the memory 31 to perform the steps in each of the above-mentioned SiC MOSFET power cycle test gate dynamic bias control method embodiments, such as Figure 1 As shown in steps S101-S102. Alternatively, the processor 30 is configured to invoke and run the computer program 32 stored in the memory 31 to implement the functions of each module / unit in each of the above-mentioned device embodiments, such as Figure 6 As shown in the functions of modules 21-22.

[0133] For example, the computer program 32 can be divided into one or more modules / units, one or more modules / units are stored in the memory 31 and executed by the processor 30 to complete the present application. One or more modules / units can be a series of computer program instruction segments capable of completing a specific function, which is used to describe the execution process of the computer program 32 in the control terminal 3. For example, the computer program 32 can be divided into Figure 6 As shown in modules / units 21-23.

[0134] The control terminal 3 can be a desktop computer, a notebook, a palm computer, and a cloud server, etc. The control terminal 3 can include, but is not limited to, a processor 30, a memory 31. Those skilled in the art can understand that Figure 7 The control terminal 3 is only an example and does not constitute a limitation on the control terminal 3, and can include more or fewer components than shown, or combine certain components, or different components, for example, the terminal can also include input / output devices, network access devices, buses, etc.

[0135] The processor 30 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0136] The memory 31 can be an internal storage unit of the terminal 3, for example, a hard disk or a memory of the terminal 3. The memory 31 can also be an external storage device of the terminal 3, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal 3. Further, the memory 31 can also include both the internal storage unit and the external storage device of the terminal 3. The memory 31 is used to store computer programs and other programs and data required by the terminal. The memory 31 can also be used to temporarily store data that has been output or will be output.

[0137] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit, and the integrated unit can be realized in the form of hardware or software. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the above system can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0138] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can refer to the relevant description of other embodiments.

[0139] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0140] In the embodiments of the present application, it should be understood that the disclosed apparatus / terminal and method can be implemented in other manners. For example, the apparatus / terminal embodiments described above are merely schematic, and the division of the modules or units can be different, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0141] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0142] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically independent unit, or two or more units can be integrated into a unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0143] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, all or part of the flow of the above-mentioned embodiment methods can be implemented by a computer program instructing related hardware to complete, and the computer program can be stored in a computer readable storage medium, and when the processor executes the computer program, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable file or some intermediate form. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0144] The above examples are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing examples, those ordinarily skilled in the art should understand: the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A SiC MOSFET power cycling test gate dynamic bias control method, characterized by, The method comprises: repeatedly performing a plurality of cycles of power cycle tests; obtaining a junction temperature of each cycle, and determining an aging condition of a target MOSFET according to a change in the junction temperature of each cycle; wherein a cycle of the power cycle test comprises: applying a forward bias voltage to a gate of the target MOSFET for a first preset time length, and providing a hot heating current to a drain of the target MOSFET, so that the target MOSFET is warmed up to thermal equilibrium; applying a reverse bias voltage to the gate of the target MOSFET for a second preset time length, and turning off the drain current of the target MOSFET, so that the target MOSFET is cooled down to thermal equilibrium, detecting a threshold voltage of the target MOSFET when the target MOSFET reaches thermal equilibrium, and recording the threshold voltage as a first threshold voltage; determining a forward bias time length of a current cycle according to the first threshold voltage of a previous cycle, a second threshold voltage of the previous cycle, and the first threshold voltage of the current cycle, and taking the forward bias time length of the current cycle as a new third time length; applying the forward bias voltage to the gate of the target MOSFET for the third time length, and turning off the drain current of the target MOSFET, detecting a threshold voltage of the target MOSFET at the end of the third time length, and recording the threshold voltage as a second threshold voltage; the determining of the forward bias time length of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the first threshold voltage of the current cycle, and taking the forward bias time length of the current cycle as a new third time length, comprises: determining a feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and a third time length of the previous cycle; determining the forward bias time length of the current cycle according to the feedback coefficient of the current cycle, a reference threshold voltage, and the first threshold voltage of the current cycle; taking the forward bias time length of the current cycle as a new third time length; the determining of the feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the third time length of the previous cycle, comprises: determining the feedback coefficient of the current cycle according to the first threshold voltage of the previous cycle, the second threshold voltage of the previous cycle, and the third time length of the previous cycle, in combination with a first formula; the first formula is: in, For the first The feedback coefficient for each cycle, For the first The second threshold voltage for each cycle, For the first The threshold voltage of the first cycle, For the first The third duration of the cycle; ; the determining of the forward bias time length of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage, and the first threshold voltage of the current cycle, comprises: determining the forward bias time length of the current cycle according to the feedback coefficient of the current cycle, the reference threshold voltage, and the first threshold voltage of the current cycle, in combination with a second formula; the second formula comprises: wherein, is a length of a forward bias of a first cycle, is a length of a forward bias of a second cycle, is the reference threshold voltage, is a first threshold voltage of a first cycle, is a first threshold voltage of a second cycle, is a feedback coefficient of a first cycle, and is a feedback coefficient of a second cycle.

2. The SiC MOSFET power cycling test gate dynamic bias control method of claim 1, wherein, before the repeatedly performing of the plurality of cycles of power cycle tests, the method further comprises: applying a fourth preset duration of forward bias voltage to the gate of the target MOSFET and providing a sensing current to the drain of the target MOSFET so that the target MOSFET is heated to thermal equilibrium, and detecting the threshold voltage of the target MOSFET when the target MOSFET reaches thermal equilibrium as the reference threshold voltage.

3. The SiC MOSFET power cycling test gate dynamic bias control method of claim 2, wherein, Before the repeatedly performing the multi-cycle power cycle test and after the applying a fourth preset duration of forward bias voltage to the gate of the target MOSFET and providing a sensing current to the drain of the target MOSFET so that the target MOSFET is heated to thermal equilibrium, and detecting the threshold voltage of the target MOSFET when the target MOSFET reaches thermal equilibrium as the reference threshold voltage, the method further comprises: determining the value of the second preset duration according to the reference threshold voltage.

4. The SiC MOSFET power cycling test gate dynamic bias control method of claim 3, wherein, The determining the value of the second preset duration according to the reference threshold voltage comprises: setting an initial value of a fifth duration; applying the first preset duration of forward bias voltage to the gate of the target MOSFET and providing a hot heating current to the drain of the target MOSFET so that the target MOSFET is heated to thermal equilibrium; applying the fifth duration of reverse bias voltage to the gate of the target MOSFET and turning off the drain current of the target MOSFET so that the target MOSFET is cooled to thermal equilibrium, detecting the threshold voltage of the target MOSFET when the target MOSFET reaches thermal equilibrium as a third threshold voltage; applying a sixth preset duration of forward bias voltage to the gate of the target MOSFET and turning off the drain current of the target MOSFET; wherein the sixth preset duration is the initial value of the third duration if the third threshold voltage is less than the reference threshold voltage, taking the current value of the fifth duration as the second preset duration, and performing the repeatedly performing the multi-cycle power cycle test; if the third threshold voltage is not less than the reference threshold voltage, increasing the fifth duration, and jumping to the applying the first preset duration of forward bias voltage to the gate of the target MOSFET and providing a hot heating current to the drain of the target MOSFET so that the target MOSFET is heated to thermal equilibrium step to continue to be performed.

5. The SiC MOSFET power cycling test gate dynamic bias control method according to any one of claims 1 to 4, characterized in that, The absolute value of the reverse bias voltage is greater than the absolute value of the forward bias voltage.

6. The SiC MOSFET power cycling test gate dynamic bias control method according to any one of claims 1 to 4, characterized in that, The forward bias voltage is less than the channel on voltage value of the target MOSFET and greater than a preset voltage.

7. A control terminal, characterized by comprising: The apparatus comprises a processor and a memory, the memory is used to store a computer program, and the processor is used to invoke and run the computer program stored in the memory, and when executed, the steps of the SiC MOSFET power cycle test gate dynamic bias control method according to any one of claims 1 to 6 are implemented.

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