Wiring anomaly detection method and device for positioning copper-exposed gold wire in PCB (Printed Circuit Board)

Abstract

The invention provides a method and a device for detecting wiring abnormity on a positioning copper-exposed gold wire in a PCB (Printed Circuit Board), and relates to the technical field of circuit board design. The method comprises the following steps: in response to a generated wiring abnormity detection instruction for the PCB, grabbing a positioning copper-exposed gold wire of a copper-exposed layer of the PCB, determining whether a non-grounding circuit exists in a circuit in an area range where the positioning copper-exposed gold wire is located, and if the non-grounding circuit exists, determining that wiring on the positioning copper-exposed gold wire in the PCB is abnormal. According to the method, the positioning copper-exposed gold wires of the copper-exposed layer of the PCB are automatically grabbed, whether the non-grounding lines exist in the lines in the area range where the positioning copper-exposed gold wires are located or not is detected, so that the detection efficiency is greatly improved, the detection process can be systemized and standardized through automatic detection, the area range where all the positioning copper-exposed gold wires in the PCB are located is comprehensively covered, and the detection efficiency is improved. Therefore, the problems of missing detection and false detection possibly occurring in manual detection are reduced, and the accuracy and reliability of wiring anomaly detection are improved.

Description

Technical Field

[0001] The present application relates to the technical field of circuit board design, and in particular to a method and device for detecting wiring anomalies on exposed copper and gold wires in a PCB. Background Art

[0002] In the manufacturing process of electronic products, the design and production of printed circuit boards (PCBs) are a crucial link, and their design quality directly affects the performance, reliability and production efficiency of the products. In the PCB design process, the key chips and / or structural parts located on the top or bottom layer of the PCB usually need to be designed with exposed copper and gold wires, so that after the surface mount technology (SMT) is used to produce the patch, the automatic optical inspection (AOI) equipment can check whether the components that constitute the key chips or structural parts are offset based on the exposed copper and gold wires. However, in the actual wiring process, designers often mistakenly place non-grounded (GND) network signals on these exposed copper and gold wires, resulting in the exposed live signals being exposed in the air. When the PCB contacts the metal shell, it is very easy to cause a short circuit, and the exposed live signals are also prone to corrosion in test environments such as humidity and salt spray. Therefore, before the PCB is put into production, it is necessary to perform abnormal detection on the wiring on the exposed copper and gold wires in the PCB.

[0003] In the related art, abnormal detection of wiring on exposed copper and gold wires in PCB is usually performed manually, but manual detection is inefficient and there is a problem of missed detection. Summary of the invention

[0004] The present application provides a method and device for detecting wiring anomalies on exposed copper and gold wires in a PCB, so as to reduce the problem of low efficiency and missed detection when manually detecting wiring anomalies on exposed copper and gold wires in a PCB in the related art.

[0005] In a first aspect, the present application provides a wiring anomaly detection method for locating exposed copper-gold wires in a PCB, comprising:

[0006] In response to a wiring anomaly detection instruction for the generated PCB, grab the exposed copper layer of the PCB and locate the exposed copper gold wire;

[0007] Determine whether there is a non-grounded line in the area where the exposed copper-gold wire is located;

[0008] If there is a non-grounded circuit in the area where the exposed copper-gold wire is located, it is determined that there is an abnormality in the wiring on the exposed copper-gold wire located in the PCB.

[0009] In a possible implementation, grabbing the exposed copper layer of the PCB and positioning the exposed copper gold wire includes: identifying the exposed copper layer in the top layer and the bottom layer in the PCB; and grabbing the positioned exposed copper gold wire in the exposed copper layer based on a frame selection instruction.

[0010] In a possible implementation, determining whether there is a non-grounded line in the line within the area where the exposed copper-gold line is located includes: obtaining the endpoint coordinates of the exposed copper-gold line; generating the area where the exposed copper-gold line is located according to the endpoint coordinates; selecting the line within the area; grabbing the line name of the line; and determining whether there is a non-grounded line in the line within the area where the exposed copper-gold line is located based on the line name.

[0011] In a possible implementation, the method for detecting wiring anomalies on exposed copper-gold wires in a PCB further includes: if there are non-grounded wires in the area where the exposed copper-gold wires are located, adding an abnormal warning mark for the non-grounded wires.

[0012] In a possible implementation, adding an abnormal warning mark for the non-grounded line includes: adding an abnormal warning mark for the non-grounded line in an area where the non-grounded line crosses and locates exposed copper-gold wires.

[0013] In a possible implementation, the method for detecting wiring anomalies on exposed copper-gold wires in a PCB further includes: if there is no non-grounded circuit in the circuit within the area where the exposed copper-gold wires are located, outputting a prompt message indicating that the detection of the PCB has passed, and the prompt message indicates that the wiring on the exposed copper-gold wires in the PCB is normal.

[0014] In a possible implementation, the wiring anomaly detection method for locating exposed copper-gold wires in a PCB also includes: if there is a non-grounded line in the line within the area where the exposed copper-gold wire is located, outputting an anomaly detection report for the PCB, the anomaly detection report including the key point coordinates of the non-grounded line and the name of the non-grounded line.

[0015] In a second aspect, the present application provides a wiring anomaly detection device for locating exposed copper-gold wires in a PCB, comprising:

[0016] A grabbing module, used to respond to a wiring anomaly detection instruction for the generated PCB, and grab the exposed copper and gold wires of the exposed copper layer of the PCB;

[0017] A determination module is used to determine whether there is a non-grounded line in the line within the area where the exposed copper-gold wire is located;

[0018] The processing module is used to determine that there is an abnormality in the wiring on the exposed copper-gold wire located in the PCB when there is a non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located.

[0019] In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor;

[0020] Memory for storing computer-executable instructions;

[0021] A processor, configured to execute computer-executable instructions stored in a memory to implement any one of the methods described in the first aspect.

[0022] In a fourth aspect, the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed, they are used to implement any of the methods in the first aspect.

[0023] In a fifth aspect, the present application provides a computer program product, including a computer program, which implements any method in the first aspect when executed.

[0024] The present application provides a wiring anomaly detection method and device for positioning exposed copper and gold wires in a PCB, which responds to a wiring anomaly detection instruction for a generated PCB, grabs the positioning exposed copper and gold wires of the exposed copper layer of the PCB, and determines whether there are non-grounded circuits in the circuits within the area where the positioning exposed copper and gold wires are located. If there are non-grounded circuits in the circuits within the area where the positioning exposed copper and gold wires are located, it is determined that there is an abnormality in the wiring on the positioning exposed copper and gold wires in the PCB. In this process, by responding to the wiring anomaly detection instruction for the generated PCB, the positioning exposed copper and gold wires of the exposed copper layer of the PCB are automatically grabbed, and whether there are non-grounded circuits in the circuits within the area where they are located, thereby greatly improving the detection efficiency, reducing the problem of low manual detection efficiency, and reducing the cost of manpower input. In addition, the automated detection method can systematize and standardize the detection process, and comprehensively cover the area where all positioning exposed copper and gold wires are located in the PCB, thereby reducing the problems of missed detection and false detection that may occur in manual detection, and thus improving the accuracy and reliability of wiring anomaly detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0026] Figure 1 A schematic diagram of an application scenario of a wiring anomaly detection method for locating exposed copper and gold wires in a PCB provided by an exemplary embodiment of the present application;

[0027] Figure 2 A schematic diagram of a process of a wiring anomaly detection method for locating exposed copper-gold wires in a PCB provided by an exemplary embodiment of the present application;

[0028] Figure 3A schematic diagram of generating a region where a positioning exposed copper-gold wire is located according to a positioning exposed copper-gold wire provided by an exemplary embodiment of the present application;

[0029] Figure 4 A schematic diagram of the area range corresponding to the minimum rectangle containing the positioning exposed copper-gold wire, the first rotation line and the second rotation line provided by the exemplary embodiment of the present application after being enlarged 1.2 times;

[0030] Figure 5 A comparison diagram before and after adding an abnormal warning mark for a non-grounded line provided in an exemplary embodiment of the present application;

[0031] Figure 6 Another schematic diagram of a process for detecting wiring anomalies on exposed copper and gold wires in a PCB provided by an exemplary embodiment of the present application;

[0032] Figure 7 A schematic diagram of a structure of a wiring anomaly detection device for locating exposed copper-gold wires in a PCB provided by an exemplary embodiment of the present application;

[0033] Figure 8 A schematic diagram of the structure of an electronic device provided for an exemplary embodiment of the present application.

[0034] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0035] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0036] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, products or equipment.

[0037] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0038] In the related art, when relying on manual abnormal detection of wiring on the exposed copper and gold wires in the PCB, the inspector usually checks the top and bottom layers of the PCB one by one by eye against the PCB design drawings to determine whether there is non-GND network signal wiring on the exposed copper and gold wires, and another inspector or senior engineer reviews the preliminary inspection results to ensure the accuracy of the inspection results. However, since manual inspection requires checking each exposed copper and gold wire of the PCB one by one, the process is cumbersome and time-consuming, especially in mass production, the efficiency is extremely low and the manpower investment cost is high; due to the different experience and skill levels of different inspectors during manual inspection, and the large amount of repetitive workload of manual inspection, it is easy to cause fatigue and decreased attention of the inspectors, making manual inspection prone to missed inspections, resulting in some abnormal wiring not being discovered, which in turn affects the performance and reliability of the product; in addition, manual inspection relies on the subjective judgment of the inspectors, and there may be differences in the inspection results, which makes it difficult to ensure the consistency and reliability of the inspection results, and as the complexity of PCB design increases, the difficulty of manual inspection also increases, further reducing the inspection efficiency and the accuracy of the inspection results.

[0039] In order to solve the above problems, the embodiment of the present application provides a wiring anomaly detection solution for positioning exposed copper and gold wires in PCBs. By designing an automated detection tool or automated detection program for one-click inspection of wiring anomalies on positioning exposed copper and gold wires in PCBs, in response to wiring anomaly detection instructions for the generated PCB, the positioning exposed copper and gold wires of the exposed copper layer of the PCB are automatically captured, and whether there are non-grounded lines in the lines within the area where they are located is detected, thereby realizing automated detection of wiring anomalies on positioning exposed copper and gold wires in PCBs, thereby greatly improving detection efficiency, reducing the problem of low manual detection efficiency, and reducing manpower input costs. In addition, automated detection can systematize and standardize the detection process, and comprehensively cover the area range where all positioning exposed copper and gold wires in the PCB are located, thereby reducing the problems of missed detection and false detection that may occur during manual detection, and thus improving the accuracy and reliability of wiring anomaly detection.

[0040] Figure 1 A schematic diagram of an application scenario of a wiring anomaly detection method for locating exposed copper and gold wires in a PCB provided by an exemplary embodiment of the present application. Figure 1 As shown, the application scenario includes a client 11 and a server 12, wherein the number of the client 11 may be at least one, and a PCB design tool such as Cadence is deployed in the server 12. In practical applications, when the server 12 detects a wiring anomaly detection instruction for the generated PCB submitted by the client 11, the server 12 executes the wiring anomaly detection method for locating exposed copper and gold wires in the PCB provided in the present application to determine whether there is an abnormality in the wiring located on the exposed copper and gold wires in the PCB.

[0041] It should be noted that the server 12 may also be replaced by a server cluster or other computing devices with certain computing power. The client 11 may be a computer or a notebook.

[0042] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0043] Figure 2 A schematic diagram of a process flow of a wiring anomaly detection method for locating exposed copper and gold wires in a PCB provided by an exemplary embodiment of the present application. Figure 2 As shown, the wiring abnormality detection method for locating exposed copper-gold wires in the PCB includes the following steps:

[0044] S201, responding to a wiring anomaly detection instruction for a generated PCB, grabbing the exposed copper gold wire of the exposed copper layer of the PCB.

[0045] For example, in one implementation, Figure 1 As shown, a pre-designed one-click check for wiring anomalies on the exposed copper and gold wires in the PCB, such as a Skill program, is installed under the pcbenv path of the PCB design tool. Further, a new menu item such as Check Gold Line Issues is added under the MANUFACTURE menu of the PCB design tool, and Check Gold Line Issues is used to start the Skill program. Correspondingly, the user submits a wiring anomaly detection instruction for the generated PCB through the client 11, and the server 12 responds to the wiring anomaly detection instruction for the generated PCB, clicks the Check Gold Line Issues menu, starts the Skill program, and automatically captures the exposed copper and gold wires of the exposed copper layer of the PCB based on the preset judgment logic in the Skill program. Among them, the Skill program refers to a program written in the Skill language, which is a scripting language specifically used for electronic design automation tools and is widely used in PCB design tools. It should be noted that the Skill program here is only an example of an automated detection program. In actual applications, it can also be a program written in other programming languages. The type of automated detection program is not limited here.

[0046] In another implementation, still refer to Figure 1 , a pre-designed one-click automatic detection tool for locating wiring anomalies on exposed copper and gold wires in PCB is deployed on server 12. Correspondingly, Figure 1 As shown, the user submits a wiring anomaly detection instruction for the generated PCB through the client 11, and the server 12 responds to the wiring anomaly detection instruction for the generated PCB, runs the automatic detection tool, and automatically captures the exposed copper layer of the PCB and locates the exposed copper and gold wire based on the preset judgment logic in the automatic detection tool.

[0047] It should be noted that the above-mentioned positioning exposed copper-gold wires can be the positioning exposed copper-gold wires of the exposed copper layer in the target area, or can be all the positioning exposed copper-gold wires of all exposed copper layers of the generated PCB. The number of positioning exposed copper-gold wires is not limited here.

[0048] S202: Determine whether there is a non-grounded line in the area where the exposed copper-gold wire is located.

[0049] Among them, non-grounded lines refer to all electrical lines that are not directly connected to the ground, including signal lines, power lines, data lines and control lines. The wiring and processing of non-grounded lines require special attention to signal integrity, electromagnetic interference, thermal management and safety and reliability to ensure the normal operation and reliability of the circuit.

[0050] For example, Figure 3 A schematic diagram of generating a region where a copper-gold wire is located according to a positioning copper-gold wire provided by an exemplary embodiment of the present application. Figure 3 As shown, with one end point of the positioning copper-gold exposed wire as the rotation center, the positioning copper-gold exposed wire is rotated to the left by a first angle to obtain a first rotation line; and with the end point as the rotation center, the positioning copper-gold exposed wire is rotated to the right by a second angle to obtain a second rotation line. The first angle and the second angle can be the same, for example, both are 25 degrees, 30 degrees or 35 degrees, etc., which meet the requirements, or they can be different, for example, the first angle is 30 degrees and the second angle is 35 degrees. The sizes of the first angle and the second angle are not limited here.

[0051] Furthermore, the area where the exposed copper-gold line is located is determined based on the exposed copper-gold line, the first rotation line, and the second rotation line. For example, a minimum outer polygon containing the exposed copper-gold line, the first rotation line, and the second rotation line is generated, and the area corresponding to the minimum outer polygon after being magnified by, for example, 1.2 times is used as the area where the exposed copper-gold line is located. Among them, the minimum outer polygon includes a circle, a triangle, a rectangle, and a hexagon, etc., and the type of the minimum outer polygon is not limited here, as long as it meets the accuracy requirements of the business. For example, Figure 4 This is a schematic diagram of the area range corresponding to the minimum rectangle containing the positioning copper-gold exposed wire, the first rotation line and the second rotation line provided by the exemplary embodiment of the present application after being enlarged 1.2 times. Figure 4 As shown, the enclosed area corresponding to the bold dashed rectangle is the area where the exposed copper-gold wire is located. It should be noted that the above 1.2 times magnification is only an example. In actual applications, the magnification can also be 1, 1.3, 1.5 and other values ​​that meet the requirements, which are not limited here.

[0052] Furthermore, all the lines in the area are identified, and according to a preset judgment logic, it is determined whether there is a non-grounded line in the lines.

[0053] S203. If there is a non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located, it is determined that there is an abnormality in the wiring on the exposed copper-gold wire located in the PCB.

[0054] For example, if there is a non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located, an alarm or prompt information is generated to facilitate designers or engineers to perform further inspection and correction based on the alarm or prompt information. For example, the PCB design file can be modified or corrections can be made during the manufacturing process to ensure that there is a non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located, thereby reducing potential electrical problems.

[0055] The wiring anomaly detection method for locating exposed copper and gold wires in a PCB provided in an embodiment of the present application responds to wiring anomaly detection instructions for the generated PCB, automatically grabs the exposed copper and gold wires located in the exposed copper layer of the PCB, and detects whether there are non-grounded lines in the lines within the area where they are located, thereby greatly improving the detection efficiency, reducing the problem of low efficiency of manual detection, and also reducing the cost of manpower input. In addition, the automated detection method can systematize and standardize the detection process, reduce the influence and limitation of factors such as the complexity of PCB design, the experience, skill level, subjective judgment, human eye fatigue and attention of the detection personnel, and comprehensively cover the area range where all the exposed copper and gold wires are located in the PCB, thereby reducing the problems of missed detection and false detection that may occur in manual detection, and thus improving the accuracy and reliability of wiring anomaly detection.

[0056] In some embodiments, grabbing the exposed copper layer of the PCB and positioning the exposed copper gold wire includes: identifying the exposed copper layer in the top layer and the bottom layer in the PCB; and grabbing the positioned exposed copper gold wire in the exposed copper layer based on a frame selection instruction.

[0057] For example, the top layer (i.e., TOP layer) and the bottom layer (i.e., BOTTOM layer) of the PCB are scanned to identify the exposed copper layer (i.e., Golden layer) in the top layer and the bottom layer. Based on a box selection instruction such as axlSingleSelectBox, a box selection is performed on the positioning exposed copper and gold wire in the exposed copper layer. All objects in the box selection area are further obtained. Among all the obtained objects, each object is traversed in turn to check whether each object has a shape attribute. If so, it is further checked whether the object is a positioning exposed copper and gold wire, and the qualified object is added to the list, thereby obtaining all the positioning exposed copper and gold wires with shape attributes.

[0058] In some embodiments, determining whether there is a non-grounded line in the line within the area where the exposed copper-gold line is located includes: obtaining the endpoint coordinates of the exposed copper-gold line; generating the area where the exposed copper-gold line is located according to the endpoint coordinates; selecting the line within the area; grabbing the line name of the line; and determining whether there is a non-grounded line in the line within the area where the exposed copper-gold line is located based on the line name.

[0059] For example, a grab instruction such as axlGetSelSet is used to grab and locate the endpoint coordinates of the exposed copper-gold wire, and a Figure 4The area range shown in the figure is selected, and the lines in the area range are selected based on the box selection instructions such as axlSingleSelectBox. The line names of the lines are grabbed using the grabbing instructions such as axlGetSelSet. It is further determined whether there is a line name of a non-grounded line in the line name. For example, the line name of the grounded line is "GND". If the line name of a line is "UFSO_TXO_M", the line name can be used to determine that the line is a non-grounded line.

[0060] In the embodiment of the present application, the endpoint coordinates of the exposed copper-gold wire are obtained and the area range is generated, so as to accurately locate the position of the exposed copper-gold wire and obtain the line name, thereby improving the accuracy of the detection result; in addition, by automatically capturing the line name and analyzing it, the problem area can be quickly identified, which is convenient for timely repair or adjustment, thereby preventing potential electrical failures or safety hazards, and further improving the stability and safety of PCB design.

[0061] Considering that in the related technology, when the wiring on the exposed copper and gold wires in the PCB is manually detected for abnormality, if an abnormality is detected, the abnormal wiring position needs to be manually recorded without relevant warning signs, which is not conducive to discovering and handling problems. This manual recording method is not only inefficient, but also prone to omissions or errors, resulting in potential electrical failures or safety hazards that cannot be eliminated in time, thereby affecting the stability and safety of the PCB design. In addition, the repetitive workload of manual inspection is large, which can easily lead to fatigue and decreased attention of the inspectors, further increasing the unreliability of the inspection results.

[0062] Therefore, based on the above embodiments, in some embodiments, the wiring anomaly detection method for locating exposed copper-gold wires in a PCB further includes: if there are non-grounded lines in the lines within the area where the exposed copper-gold wires are located, an abnormal warning mark is added for the non-grounded lines.

[0063] For example, if there is a non-grounded line "UFSO_TXO_M" in the area where the exposed copper-gold wire is located, an abnormal warning mark is added to "UFSO_TXO_M". Optionally, the abnormal warning mark can be a visual mark, such as red highlight, or a warning icon is added near "UFSO_TXO_M".

[0064] In some embodiments, adding an abnormal warning mark for the non-grounded line includes: adding an abnormal warning mark for the non-grounded line in an area where the non-grounded line crosses and exposes the copper-gold wire.

[0065] For example, Figure 5 The following is a comparison diagram of the exemplary embodiment of the present application before and after adding an abnormal warning mark for a non-grounded line. Figure 5(a) is a schematic diagram before adding abnormal warning marks for non-grounded lines. Figure 5 (a) in the figure cannot visually determine whether the wiring in this area is abnormal; Figure 5 (b) in FIG. 1 is a schematic diagram after adding an abnormal warning mark for a non-grounded line, such as Figure 5 As shown in (b), in the area where the non-grounded line crosses the exposed copper-gold wire, an abnormal warning mark for the non-grounded line is added, and the wiring abnormality in the area can be intuitively identified through the abnormal warning mark.

[0066] In the embodiment of the present application, by adding abnormal warning marks to the wiring abnormalities on the exposed copper and gold wires in the PCB, designers can be reminded of potential problems in a timely manner, which facilitates rapid repair measures, thereby effectively preventing potential electrical failures and safety hazards, and further improving the stability and safety of PCB design. In addition, the automated marking method is not affected or limited by factors such as the complexity of the PCB design, the experience, skill level, subjective judgment, human eye fatigue and attention of the inspection personnel, further increasing the reliability of the inspection results.

[0067] In some embodiments, the method for detecting wiring abnormalities on the exposed copper-gold wires in the PCB further includes: if there is no non-grounded circuit in the circuit within the area where the exposed copper-gold wires are located, outputting a prompt message indicating that the PCB detection has passed, and the prompt message indicates that the wiring on the exposed copper-gold wires in the PCB is normal.

[0068] For example, still refer to Figure 4 If, in the designed PCB, there are no non-grounded circuits in the circuits within the area where the exposed copper-gold wires are located, that is, all the circuits within the area where the exposed copper-gold wires are located are grounded circuits, then the PCB detection pass prompt information is output through an output command such as axlUIWPrint, and the inspector can determine that the wiring on the exposed copper-gold wires in the PCB is normal through the prompt information.

[0069] In the embodiment of the present application, by outputting a detection pass prompt message for the PCB that has passed the detection, the detection result can be fed back in time, so that the designer can confirm the correctness of the PCB design in time.

[0070] In some embodiments, the wiring anomaly detection method for locating exposed copper-gold wires in a PCB also includes: if there is a non-grounded line in the line within the area where the exposed copper-gold wire is located, outputting an anomaly detection report for the PCB, the anomaly detection report including the key point coordinates of the non-grounded line and the name of the non-grounded line.

[0071] For example, if there are non-grounded lines "UFSO_TXO_M", "UFSO_TXO_N" and "UFSO_TXO_K" in the area where the exposed copper-gold wire is located, an abnormal detection report of the PCB is automatically generated. The abnormal detection report includes the key points of each non-grounded line, such as the starting point coordinates and the end point coordinates, the name of the line and the type of the line, and combined with the PCB design drawings, modification suggestions for each non-grounded line are given. Furthermore, the detection report is stored in the target path or sent to the target device, which is convenient for designers to view and analyze problems; and the detection report is used as a process management file for PCB design.

[0072] In the embodiment of the present application, through the relevant information recorded in the anomaly detection report, the designer can quickly and accurately identify and process the non-grounded lines on the exposed copper and gold wires in the PCB design, thereby improving the processing efficiency of wiring anomalies and further improving the reliability and safety of the PCB design.

[0073] Figure 6 Another schematic diagram of the process of detecting wiring anomalies on exposed copper and gold wires in a PCB provided by an exemplary embodiment of the present application. Figure 6 As shown, the wiring abnormality detection method for locating exposed copper-gold wires in the PCB includes the following steps:

[0074] S601. In response to a wiring anomaly detection instruction for a generated PCB, the exposed copper layers in the top layer and the bottom layer in the PCB are identified.

[0075] S602, grab the exposed copper gold wire in the exposed copper layer.

[0076] For example, based on a selection instruction such as axlSingleSelectBox, a selection is performed on the positioning exposed copper-gold wire in the exposed copper layer, and all objects in the selection area are further obtained. Among all the obtained objects, each object is traversed in turn to check whether each object has a shape attribute. If so, it is further checked whether the object is a positioning exposed copper-gold wire, and the objects that meet the conditions are added to the list, thereby obtaining all the positioning exposed copper-gold wires with shape attributes.

[0077] S603, obtaining the coordinates of the endpoints of the exposed copper-gold wire.

[0078] For example, the starting and ending coordinates.

[0079] S604: Generate a region range where the exposed copper-gold wire is located according to the endpoint coordinates.

[0080] For example, based on the endpoint coordinates, Figure 4 The area shown.

[0081] S605: Capture the route names of the routes within the area.

[0082] For example, the line name of the line is fetched using a fetch instruction such as axlGetSelSet.

[0083] S606: Determine whether there is a non-grounding line name in the line names.

[0084] For example, if the line name of a grounding line is "GND", if the line name of a certain line is "UFSO_TXO_M", it can be determined that the line is a non-grounding line through the line name, and then it is determined that there is a non-grounding line name in the line name.

[0085] If yes, execute S607;

[0086] If not, execute S608.

[0087] S607. Add an abnormal warning mark for non-grounded lines.

[0088] For example, in the area where the non-grounded line crosses the exposed copper-gold wire, an abnormal warning mark for the non-grounded line is added, and the abnormal warning mark is as follows: Figure 5 As shown in (b) in .

[0089] S608, outputting a prompt message indicating that the PCB has passed the inspection.

[0090] For example, by outputting a prompt message indicating that the PCB has passed the inspection through an output command such as axlUIWPrint, the inspector can determine through the prompt message that the wiring on the exposed copper-gold wire in the PCB is normal.

[0091] In summary, this application has at least the following advantages:

[0092] 1. By responding to the wiring anomaly detection instructions for the generated PCB, the exposed copper layer of the PCB is automatically captured to locate the exposed copper and gold wires, and whether there are non-grounded lines in the lines within the area where they are located, thereby greatly improving the detection efficiency, reducing the problem of low efficiency of manual detection, and reducing the cost of manpower input. In addition, the automated detection method can systematize and standardize the detection process, reduce the influence and limitations of factors such as the complexity of PCB design, the experience, skill level, subjective judgment, human eye fatigue and attention of the detection personnel, and comprehensively cover the area where all the exposed copper and gold wires are located in the PCB, thereby reducing the problems of missed detection and false detection that may occur in manual detection, and thus improving the accuracy and reliability of wiring anomaly detection.

[0093] Second, by adding abnormal warning marks to the wiring anomalies on the exposed copper and gold wires in the PCB, designers can be reminded of potential problems in a timely manner, which facilitates rapid repair measures, thereby effectively preventing potential electrical failures and safety hazards, and further improving the stability and safety of PCB design. In addition, the automated marking method is not affected or limited by factors such as the complexity of the PCB design, the experience, skill level, subjective judgment, human eye fatigue and attention of the inspectors, further increasing the reliability of the inspection results.

[0094] Figure 7 A schematic diagram of a wiring anomaly detection device for locating exposed copper and gold wires in a PCB provided by an exemplary embodiment of the present application. Figure 7 As shown, the wiring anomaly detection device 70 for locating exposed copper-gold wires in the PCB includes a capture module 71, a determination module 72 and a processing module 73, wherein:

[0095] A capture module 71 is used to respond to a wiring anomaly detection instruction for the generated PCB and capture the exposed copper and gold wires of the exposed copper layer of the PCB;

[0096] A determination module 72 is used to determine whether there is a non-grounded line in the line within the area where the exposed copper-gold wire is located;

[0097] The processing module 73 is used to determine that there is an abnormality in the wiring on the exposed copper-gold wire located in the PCB when there is a non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located.

[0098] In a possible implementation, the capture module 71 may be specifically used to: identify exposed copper layers in the top layer and the bottom layer in the PCB; and capture the located exposed copper gold wires in the exposed copper layers based on the frame selection instruction.

[0099] In one possible implementation, the determination module 72 can be specifically used to: obtain the endpoint coordinates of the exposed copper-gold wire; generate the area range where the exposed copper-gold wire is located based on the endpoint coordinates; select the line within the area range; grab the line name of the line; and determine whether there is a non-grounded line in the line within the area range where the exposed copper-gold wire is located based on the line name.

[0100] In a possible implementation manner, the processing module 73 may be specifically configured to: if there is a non-grounded line in the line within the area where the exposed copper-gold wire is located, add an abnormal warning mark for the non-grounded line.

[0101] In a possible implementation manner, the processing module 73 may also be used to add an abnormal warning mark for the non-grounded line in an area where the non-grounded line crosses the exposed copper-gold wire.

[0102] In a possible implementation, the processing module 73 can also be used to output a prompt message indicating that the PCB detection has passed if there is no non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located, and the prompt message indicates that the wiring on the exposed copper-gold wire located in the PCB is normal.

[0103] In a possible implementation, the processing module 73 can also be used to output an abnormal detection report of the PCB if there is a non-grounded circuit in the area where the exposed copper-gold wire is located, and the abnormal detection report includes the key point coordinates of the non-grounded circuit and the name of the non-grounded circuit.

[0104] The wiring anomaly detection device for locating exposed copper and gold wires in a PCB provided in an embodiment of the present application can execute the technical solution shown in the embodiment of the wiring anomaly detection method for locating exposed copper and gold wires in the above-mentioned PCB, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0105] It should be noted that it should be understood that the division of the various modules of the above device is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. And these modules can all be implemented in the form of software called by processing elements; they can also be all implemented in the form of hardware; some modules can also be implemented in the form of software called by processing elements, and some modules can be implemented in the form of hardware. For example, the processing module can be a separately established processing element, or it can be integrated in a chip of the above device. In addition, it can also be stored in the memory of the above device in the form of program code, and called and executed by a processing element of the above device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each module above can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

[0106] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more microprocessors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0107] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer instructions on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, referred to as DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. Available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, Digital Video Discs (DVDs)), or semiconductor media (eg, solid state disks (SSDs)).

[0108] Figure 8 The schematic diagram of the structure of the electronic device provided by the exemplary embodiment of the present application. Figure 8 As shown, the electronic device 80 of this embodiment includes:

[0109] At least one processor 81; and a memory 82 communicatively connected to the at least one processor;

[0110] The memory 82 stores instructions that can be executed by the at least one processor 81, and the instructions are executed by the at least one processor 81 to enable the electronic device to execute the method described in any of the above embodiments.

[0111] Optionally, the memory 82 may be independent or integrated with the processor 81 .

[0112] The memory 82 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0113] The processor 81 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. Specifically, when implementing the wiring anomaly detection method for locating exposed copper-gold wires in a PCB described in the aforementioned method embodiment, the electronic device may be, for example, an electronic device with processing functions such as a server.

[0114] Optionally, the electronic device may further include a communication interface 83. In a specific implementation, if the communication interface 83, the memory 82 and the processor 81 are implemented independently, the communication interface 83, the memory 82 and the processor 81 may be interconnected through a bus and communicate with each other. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc., but it does not mean that there is only one bus or one type of bus.

[0115] Optionally, in a specific implementation, if the communication interface 83, the memory 82 and the processor 81 are integrated on a chip, the communication interface 83, the memory 82 and the processor 81 can communicate through an internal interface.

[0116] The implementation principle and technical effects of the electronic device provided in this embodiment can be found in the aforementioned embodiments and will not be described in detail here.

[0117] An embodiment of the present application also provides a computer-readable storage medium, in which computer execution instructions are stored. When the computer execution instructions are executed, they are used to implement the method steps in the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0118] The above-mentioned computer readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0119] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in a dedicated integrated circuit. Of course, the processor and the readable storage medium can also be present as discrete components in a wiring anomaly detection device for positioning exposed copper and gold wires in a PCB.

[0120] The embodiment of the present application also provides a computer program product, including a computer program. When the computer program is executed, the method steps in the above method embodiment are implemented. The specific implementation method and technical effect are similar and will not be repeated here.

[0121] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0122] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for detecting wiring anomalies on exposed copper and gold wires in a PCB, characterized in that: include: In response to a wiring anomaly detection instruction for the generated PCB, grabbing the copper-exposed gold wire located on the copper-exposed layer of the PCB; Determine whether there is a non-grounded line in the line within the area where the exposed copper-gold wire is located; If there is a non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located, it is determined that there is an abnormality in the wiring on the exposed copper-gold wire located in the PCB.

2. The wiring anomaly detection method according to claim 1, characterized in that: The method of grabbing the exposed copper layer of the PCB and positioning the exposed copper gold wire comprises: Identifying exposed copper layers in a top layer and a bottom layer in the PCB; Based on the frame selection instruction, the positioned exposed copper gold wire in the exposed copper layer is grabbed.

3. The wiring anomaly detection method according to claim 1, characterized in that: The step of determining whether there is a non-grounded line in the area where the exposed copper-gold wire is located includes: Obtaining the endpoint coordinates of the positioning exposed copper-gold wire; According to the endpoint coordinates, generating the area range where the exposed copper-gold wire is located; Select the lines within the area; Get the line name of the line; Based on the line name, determine whether there is a non-grounded line in the line within the area where the exposed copper-gold wire is located.

4. The wiring anomaly detection method according to any one of claims 1 to 3, characterized in that: Also includes: If there is a non-grounded line in the area where the exposed copper-gold wire is located, an abnormal warning mark is added to the non-grounded line.

5. The wiring anomaly detection method according to claim 4, characterized in that: The adding of an abnormal warning mark to the non-grounded line includes: In the area where the non-grounding line crosses and locates the exposed copper-gold wire, an abnormal warning mark for the non-grounding line is added.

6. The wiring anomaly detection method according to any one of claims 1 to 3, characterized in that: Also includes: If there is no non-grounded circuit in the area where the exposed copper-gold wire is located, a prompt message indicating that the PCB has passed the detection is output, and the prompt message indicates that the wiring on the exposed copper-gold wire located in the PCB is normal.

7. The wiring anomaly detection method according to any one of claims 1 to 3, characterized in that: Also includes: If there is a non-grounded circuit in the area where the exposed copper-gold wire is located, an abnormal detection report of the PCB is output, and the abnormal detection report includes the key point coordinates of the non-grounded circuit and the name of the non-grounded circuit.

8. A wiring anomaly detection device for locating exposed copper and gold wires in a PCB, characterized in that: include: A grabbing module, used for responding to a wiring anomaly detection instruction for the generated PCB, and grabbing the positioning copper-exposed gold wire of the copper-exposed layer of the PCB; A determination module, used to determine whether there is a non-grounded line in the line within the area where the exposed copper-gold wire is located; The processing module is used to determine that there is an abnormality in the wiring on the exposed copper-gold wire located in the PCB when there is a non-grounded circuit in the circuit within the area where the exposed copper-gold wire is located.

9. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory is used to store computer-executable instructions; The processor is used to execute the computer-executable instructions to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed, the method according to any one of claims 1 to 7 is implemented.

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