Low dropout linear regulator with low power consumption and fast transient response and microprocessor

Abstract

The invention provides a low dropout linear regulator with low power consumption and fast transient response and a microprocessor. A main loop circuit is configured to receive a reference voltage and a feedback voltage and adjust an output voltage to enable the output voltage to be constant at an expected value; the first loop circuit is configured to be connected with the main loop in parallel, receive the reference voltage and the feedback voltage and are used for adjusting the transient condition that the output load current is changed from small to large; the second loop circuit is configured to be connected in parallel with the main loop and receive the feedback voltage for adjusting the transient condition of the output load current from large to small. When the output is stable, the first loop circuit and the second loop circuit are in a closed state, the first loop circuit enhances the adjustment of the system on the suddenly dropped output voltage, and the second loop circuit enhances the adjustment of the system on the suddenly raised output voltage. The first loop circuit and the second loop circuit work together, opening or closing of the loop is selected according to the condition of the load, and energy consumption is saved.

Description

Technical Field

[0001] The invention relates to the field of voltage stabilizers, and in particular to a low-voltage difference linear voltage stabilizer with low power consumption and fast transient response and a microprocessor. Background Art

[0002] LDO (Low Dropout Regulator) is a low-dropout linear regulator, which is widely used in electronic devices that require low voltage difference, low power consumption and high stability. As electronic products develop towards miniaturization, high integration and low power consumption, the demand for LDO continues to grow. Compared with traditional voltage regulators, LDO can still provide stable voltage output when the output voltage is close to the input voltage. At present, LDO has been widely used in mobile communications, portable devices, medical electronics, automotive electronics and other fields. With the development of technology, modern LDO products are becoming more and more excellent in performance, such as lower quiescent current (to reduce power consumption), higher voltage regulation accuracy, faster transient response, and greater output current capability.

[0003] The transient research of LDO linear regulator mainly focuses on its transient response, which refers to the transient pulse phenomenon of output voltage caused by step changes in input voltage and output load and the time it takes for the output voltage to return to stability. LDO linear regulators usually power low-voltage digital circuits, which often have switching conversions between various working modes. Therefore, when a step change occurs, the output voltage change range of LDO must be within the nominal range to ensure the normal operation of the circuit. At the same time, since the response speed of LDO determines the ability of the load circuit to resume normal operation, the designed LDO linear regulator should have good transient characteristics. In view of the different changes in transient response, two auxiliary circuits are designed to increase the speed of transient response and reduce the drastic changes in output voltage. Summary of the invention

[0004] In order to solve the problems existing in the background technology, the present invention proposes a low-voltage dropout linear regulator and a microprocessor with low power consumption and fast transient response.

[0005] A low-power, fast-transient-response, low-dropout linear regulator comprising:

[0006] The main loop circuit includes a first error amplifier and a feedback circuit, wherein the first error amplifier receives a reference voltage and receives a feedback voltage via the feedback circuit, and the first error amplifier adjusts the output voltage via a first MOS tube;

[0007] The first loop circuit includes a second error amplifier and a two-stage inverter, the second error amplifier receives a reference voltage and a feedback voltage, and adjusts the first MOS tube through the two-stage inverter and the second MOS tube output;

[0008] The second loop circuit includes a Schmitt trigger and a third MOS tube. The Schmitt trigger receives a feedback voltage and adjusts a load current through the third MOS tube.

[0009] Based on the above, the second loop circuit further includes an auxiliary loop circuit, which receives the intermediate processed signal of the second loop circuit and assists the first loop circuit in adjusting the output voltage of the main loop circuit according to the intermediate processed signal.

[0010] Based on the above, the main loop circuit includes an error amplifier EA1 and a MOS tube PMOS_3, the non-inverting input terminal of the error amplifier FA1 is connected to the reference voltage Vref, the inverting input terminal of the error amplifier FA1 is connected to the drain of the MOS tube PMOS_3 through the resistor R1 to connect to the feedback voltage Vfb, the output terminal of the error amplifier FA1 is connected to the gate of the MOS tube PMOS_3, the source of the MOS tube PMOS_3 is connected to the power supply VDD, the drain of the MOS tube PMOS_3 serves as the output terminal Vout of the regulator and is grounded through the resistor R1 and the resistor R2 in sequence, and the drain of the MOS tube PMOS_3 is also grounded through the resistor R3 and the capacitor C1.

[0011] Based on the above, in the first loop circuit, the non-inverting input terminal of the error amplifier EA2 is connected to the reference voltage Vref, the inverting input terminal of the error amplifier EA2 is connected to the feedback voltage Vfb, the output terminal of the error amplifier EA2 is respectively connected to the gate of the MOS tube PMOS_1 and the gate of the MOS tube NMOS_1, the source of the MOS tube PMOS_1 is connected to the power supply VDD, the drain of the MOS tube PMOS_1 is respectively connected to the drain of the MOS tube NMOS_1, the gate of the MOS tube PMOS_2 and the gate of the MOS tube NMOS_2, the source of the MOS tube NMOS_1 and the source of the MOS tube NMOS_2 are respectively grounded, the source of the MOS tube PMOS_2 is connected to the power supply VDD, the drain of the MOS tube PMOS_2 is respectively connected to the drain of the MOS tube NMOS_2 and the gate of the MOS tube NMOS_3, the drain of the MOS tube NMOS_3 is connected to the gate of the MOS tube PMOS_3 in the main loop circuit, and the source of the MOS tube NMOS_3 is grounded.

[0012] Based on the above, in the second loop circuit, the gate of the MOS tube PMOS_4 and the gate of the MOS tube NMOS_4 are respectively connected to the feedback voltage Vfb through the resistor R4, the source of the MOS tube PMOS_4 is connected to the power supply VDD, the drain of the MOS tube PMOS_4 is respectively connected to the drain of the MOS tube NMOS_4, the gate of the MOS tube PMOS_5 and the gate of the MOS tube NMOS_5, the source of the MOS tube NMOS_4 and the source of the MOS tube NMOS_5 are respectively grounded, the source of the MOS tube PMOS_5 is connected to the power supply VDD, the drain of the MOS tube PMOS_5 is respectively connected to the drain of the MOS tube NMOS_5 and the gate of the MOS tube NMOS_6, and the drain of the MOS tube PMOS_5 is also connected to the gate of the MOS tube PMOS_4 through the resistor R5; the drain of the MOS tube NMOS_6 is connected to the output end of the main loop circuit, and the source of the MOS tube NMOS_6 is grounded.

[0013] Based on the above, a MOS transistor PMOS_6 is also included, the gate of the MOS transistor PMOS_6 is connected to the drain of the MOS transistor PMOS_4, the source of the MOS transistor PMOS_6 is connected to the power supply VDD, and the drain of the MOS transistor PMOS_6 is connected to the output end of the main loop circuit.

[0014] A microprocessor comprises a low voltage dropout linear regulator, wherein the low voltage dropout linear regulator is the low voltage dropout linear regulator with low power consumption and fast transient response as claimed in any one of claims 1 to 4.

[0015] The present invention has outstanding substantive features and significant progress compared to the prior art. Specifically, the first loop circuit and the second loop circuit of the present invention are in a closed state when the output is stable. The first loop circuit enhances the regulation of the system's transient response to the output load current changing from small to large, and the second loop circuit enhances the regulation of the system's transient response to the output load current changing from large to small. The first loop circuit and the second loop circuit work together, and the loop is opened or closed according to the change of the load current, saving dynamic power consumption; the auxiliary loop circuit enhances the speed of the first loop circuit to the transient response. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the circuit structure of the voltage stabilizer of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] Example 1

[0019] like Figure 1 As shown, a low-power, fast-transient-response low-voltage-difference linear regulator comprises a main loop circuit, a first error amplifier, namely, an error amplifier FA1, and a feedback circuit. The error amplifier FA1 receives a reference voltage Vref and receives a feedback voltage Vfb via the feedback circuit. The error amplifier FA1 adjusts the output voltage via a first MOS tube, namely, PMOS_3; a first loop circuit comprises a second error amplifier, namely, an error amplifier EA2, and a two-stage inverter. The error amplifier EA2 receives a reference voltage Vref and a feedback voltage Vfb, and outputs and adjusts the first MOS tube, namely, PMOS_3, via the two-stage inverter and the second MOS tube, namely, NMOS_3; a second loop circuit comprises a Schmitt trigger and a third MOS tube, namely, NMOS_6. The Schmitt trigger receives the feedback voltage Vfb and adjusts the load current via the MOS tube NMOS_6.

[0020] Under normal working conditions, the output voltage Vout is adjusted by the main loop circuit. Due to the large gain of the loop circuit, the output voltage is constant at the expected value, keeping Vref and Vfb equal. The first loop circuit and the second loop circuit are respectively connected in parallel to the main loop circuit and work together. The first loop circuit is mainly aimed at when the load current jumps from zero to the maximum value allowed by the circuit, the load needs to immediately draw a large amount of current from the LDO. If the current provided by the LDO is not enough to maintain the load current, the output voltage Vout will decrease. When the output voltage undershoots (the voltage decreases instantaneously), the feedback voltage Vfb also decreases instantaneously. The first loop circuit amplifies the difference between the impact amount and the reference voltage, and outputs a voltage with a large range of changes, so that the NMOS_3 tube is turned on, which can quickly provide a discharge loop for the gate capacitance of the adjustment tube PMOS_3, so as to reduce the gate voltage of the adjustment tube PMOS_3 as soon as possible, so that the adjustment tube PMOS_3 quickly flows a larger current to supplement the suddenly increased load current. The second loop circuit mainly targets the process of the output voltage Vout at the output end increasing. When the output voltage surges (the voltage increases instantaneously), it discharges and lowers the feedback voltage to enhance the transient response speed. The first loop circuit enhances the system's regulation function for the sudden drop in the output voltage Vout, while the second loop circuit enhances the system's regulation function for the sudden rise in the output voltage Vout. When the output is stable, the first loop circuit and the second loop circuit are in the closed state, which enhances the transient response while not increasing the system's power consumption.

[0021] Specifically, the main loop circuit includes an error amplifier FA1 and a MOS tube PMOS_3, the non-inverting input terminal of the error amplifier FA1 is connected to the reference voltage Vref, the inverting input terminal of the error amplifier FA1 is connected to the drain of the MOS tube PMOS_3 through a resistor R1 to connect to the feedback voltage Vfb, the output terminal of the error amplifier FA1 is connected to the gate of the MOS tube PMOS_3, the source of the MOS tube PMOS_3 is connected to the power supply VDD, the drain of the MOS tube PMOS_3 is used as the output terminal Vout of the voltage regulator and is grounded through resistors R1 and R2 in turn, and the drain of the MOS tube PMOS_3 is also grounded through resistors R3 and capacitor C1. The main loop circuit is used to adjust the output voltage under normal working conditions. The reference voltage and the feedback voltage are input to FA1 of the main loop circuit. FA1 compares the two signals and generates a control signal, which is transmitted to PMOS_3 through FA1. When the voltage is stable, that is, Vfb=Vref, FA1 outputs a low level, PMOS_3 is turned on, and current is allowed to flow from the power supply through PMOS_3 to the load.

[0022] In the first loop circuit, the non-inverting input terminal of the error amplifier EA2 is connected to the reference voltage Vref, the inverting input terminal of the error amplifier EA2 is connected to the feedback voltage Vfb, the output terminal of the error amplifier EA2 is respectively connected to the gate of the MOS tube PMOS_1 and the gate of the MOS tube NMOS_1, the source of the MOS tube PMOS_1 is connected to the power supply VDD, the drain of the MOS tube PMOS_1 is respectively connected to the drain of the MOS tube NMOS_1, the gate of the MOS tube PMOS_2 and the gate of the MOS tube NMOS_2, the source of the MOS tube NMOS_1 and the source of the MOS tube NMOS_2 are respectively grounded, the source of the MOS tube PMOS_2 is connected to the power supply VDD, the drain of the MOS tube PMOS_2 is respectively connected to the drain of the MOS tube NMOS_2 and the gate of the MOS tube NMOS_3, the drain of the MOS tube NMOS_3 is connected to the gate of the MOS tube PMOS_3 in the main loop circuit, and the source of the MOS tube NMOS_3 is grounded. The first loop circuit is used for performing transient response when the output voltage Vout at the output terminal undershoots. EA2 of the first loop circuit has similar functions to FA1 of the main loop circuit. When undershooting, that is, Vfb<Vref, the reference voltage and feedback voltage are also input to EA2 of the first loop circuit, and a high level is generated. After being processed by the first inverter composed of PMOS_1 and NMOS_1, a low level is output. After being processed by the second inverter composed of PMOS_2 and NMOS_2, a high level is output. The output high-level signal is input to NMOS_3 of the first loop circuit, NMOS_3 is turned on, forming a low-resistance path, and PMOS_3 is turned on, so that the circuit can discharge quickly and raise Vfb.

[0023] In the second loop circuit, the gate of the MOS tube PMOS_4 and the gate of the MOS tube NMOS_4 are respectively connected to the feedback voltage Vfb through the resistor R4, the source of the MOS tube PMOS_4 is connected to the power supply VDD, the drain of the MOS tube PMOS_4 is respectively connected to the drain of the MOS tube NMOS_4, the gate of the MOS tube PMOS_5 and the gate of the MOS tube NMOS_5, the source of the MOS tube NMOS_4 and the source of the MOS tube NMOS_5 are respectively grounded, the source of the MOS tube PMOS_5 is connected to the power supply VDD, the drain of the MOS tube PMOS_5 is respectively connected to the drain of the MOS tube NMOS_5 and the gate of the MOS tube NMOS_6, and the drain of the MOS tube PMOS_5 is also connected to the gate of the MOS tube PMOS_4 through the resistor R5; the drain of the MOS tube NMOS_6 is connected to the output end of the main loop circuit, and the source of the MOS tube NMOS_6 is grounded. Resistor R4, resistor R5, MOS tube PMOS_4, MOS tube PMOS_5, MOS tube NMOS_4 and MOS tube NMOS_5 constitute a Schmitt trigger. The second loop circuit is used to perform a transient response when the output voltage Vout at the output end overshoots. When the overshoot, that is, Vfb>Vref, the high level of the feedback voltage is processed by the first inverter and a low level is output. After being processed by the second inverter, a high level is output. The output high level signal is input to NMOS_6 of the second loop circuit, and NMOS_6 is turned on to form a low resistance path, which pulls down the output voltage Vout and also pulls down the feedback voltage Vfb.

[0024] Example 2

[0025] The difference between this embodiment and embodiment 1 is that the second loop circuit further includes an auxiliary loop circuit, which receives the intermediate processing signal of the second loop circuit and assists the first loop circuit in adjusting the output voltage of the main loop circuit according to the intermediate processing signal.

[0026] Specifically, the auxiliary loop circuit includes a MOS transistor PMOS_6, a gate of the MOS transistor PMOS_6 is connected to a drain of the MOS transistor PMOS_4, a source of the MOS transistor PMOS_6 is connected to a power supply VDD, and a drain of the MOS transistor PMOS_6 is connected to an output end of the main loop circuit.

[0027] As the load current suddenly decreases, the output voltage increases, and the second loop receives the feedback voltage. When , Vth is the gate circuit threshold voltage, the gate voltage of NMOS_6 jumps from low level to high level, providing a low-resistance discharge path for the output point. With the sudden increase of load current, the output voltage decreases, and the second loop receives the feedback voltage. When the gate voltage of PMOS_7 changes from a high level to a low level, current is provided to the output point, thereby assisting the first loop circuit in regulating the output voltage when it undershoots.

[0028] Example 3

[0029] A microprocessor comprises a low voltage drop linear regulator. The low voltage drop linear regulator uses the low voltage drop linear regulator with low power consumption and fast transient response described in Embodiment 1 and Embodiment 2.

[0030] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A low-power, fast transient response low-dropout linear regulator, characterized in that: include The main loop circuit includes a first error amplifier and a feedback circuit, wherein the first error amplifier receives a reference voltage and receives a feedback voltage via the feedback circuit, and the first error amplifier adjusts the output voltage via a first MOS tube; The first loop circuit includes a second error amplifier and a two-stage inverter, the second error amplifier receives a reference voltage and a feedback voltage, and adjusts the first MOS tube through the two-stage inverter and the second MOS tube output; The second loop circuit includes a Schmitt trigger and a third MOS tube. The Schmitt trigger receives a feedback voltage and adjusts a load current through the third MOS tube.

2. The low-power, fast transient response low-dropout linear regulator according to claim 1, characterized in that: The second loop circuit also includes an auxiliary loop circuit, which receives the intermediate processed signal of the second loop circuit and assists the first loop circuit in adjusting the output voltage of the main loop circuit according to the intermediate processed signal.

3. The low-power, fast transient response low-dropout linear regulator according to claim 1, characterized in that: The main loop circuit includes an error amplifier EA1 and a MOS tube PMOS_3, wherein the non-inverting input terminal of the error amplifier EA1 is connected to a reference voltage Vref, the inverting input terminal of the error amplifier EA1 is connected to the drain of the MOS tube PMOS_3 through a resistor R1 to connect to a feedback voltage Vfb, the output terminal of the error amplifier EA1 is connected to the gate of the MOS tube PMOS_3, the source of the MOS tube PMOS_3 is connected to a power supply VDD, the drain of the MOS tube PMOS_3 serves as an output terminal Vout of a voltage regulator and is grounded through resistors R1 and R2 in sequence, and the drain of the MOS tube PMOS_3 is also grounded through resistor R3 and capacitor C1.

4. The low-power, fast transient response low-dropout linear regulator according to claim 1, characterized in that: In the first loop circuit, the non-inverting input terminal of the error amplifier EA2 is connected to the reference voltage Vref, the inverting input terminal of the error amplifier EA2 is connected to the feedback voltage Vfb, the output terminal of the error amplifier EA2 is respectively connected to the gate of the MOS tube PMOS_1 and the gate of the MOS tube NMOS_1, the source of the MOS tube PMOS_1 is connected to the power supply VDD, the drain of the MOS tube PMOS_1 is respectively connected to the drain of the MOS tube NMOS_1, the gate of the MOS tube PMOS_2 and the gate of the MOS tube NMOS_2, the source of the MOS tube NMOS_1 and the source of the MOS tube NMOS_2 are respectively grounded, the source of the MOS tube PMOS_2 is connected to the power supply VDD, the drain of the MOS tube PMOS_2 is respectively connected to the drain of the MOS tube NMOS_2 and the gate of the MOS tube NMOS_3, the drain of the MOS tube NMOS_3 is connected to the gate of the MOS tube PMOS_3 in the main loop circuit, and the source of the MOS tube NMOS_3 is grounded.

5. The low-power, fast transient response low-dropout linear regulator according to claim 1, characterized in that: In the second loop circuit, the gate of the MOS tube PMOS_4 and the gate of the MOS tube NMOS_4 are respectively connected to the feedback voltage Vfb through the resistor R4, the source of the MOS tube PMOS_4 is connected to the power supply VDD, the drain of the MOS tube PMOS_4 is respectively connected to the drain of the MOS tube NMOS_4, the gate of the MOS tube PMOS_5 and the gate of the MOS tube NMOS_5, the source of the MOS tube NMOS_4 and the source of the MOS tube NMOS_5 are respectively grounded, the source of the MOS tube PMOS_5 is connected to the power supply VDD, the drain of the MOS tube PMOS_5 is respectively connected to the drain of the MOS tube NMOS_5 and the gate of the MOS tube NMOS_6, and the drain of the MOS tube PMOS_5 is also connected to the gate of the MOS tube PMOS_4 through the resistor R5; the drain of the MOS tube NMOS_6 is connected to the output end of the main loop circuit, and the source of the MOS tube NMOS_6 is grounded.

6. The low-power, fast transient response low-dropout linear regulator according to claim 5, characterized in that: It also includes a MOS tube PMOS_6, a gate of the MOS tube PMOS_6 is connected to the drain of the MOS tube PMOS_4, a source of the MOS tube PMOS_6 is connected to the power supply VDD, and a drain of the MOS tube PMOS_6 is connected to the output end of the main loop circuit.

7. A microprocessor, comprising a low dropout linear regulator, characterized in that: The low voltage dropout linear regulator is a low voltage dropout linear regulator with low power consumption and fast transient response as described in any one of claims 1 to 4.

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