Memory training method and device, electronic equipment and storage medium

Abstract

The invention provides a memory training method and device, electronic equipment and a storage medium, and the method comprises the steps: dividing a memory training code in a BIOS starting process of a server based on a plurality of memory modules in the server, and obtaining a memory training code corresponding to each memory module; allocating the memory training codes corresponding to the memory modules to each kernel of a processor in the server, so that each kernel executes the memory training process of the corresponding memory module based on the allocated codes in the BIOS starting process; and determining that the memory training of the server is completed based on the read value of the memory training flag bit of each kernel. In the BIOS starting process of each kernel, the memory training process of the multiple memory modules in the server is executed in parallel, and the memory training process is rapidly completed. By starting multiple cores to execute memory training in parallel, the memory training time is shortened, and then the BIOS starting duration is shortened.

Description

Technical Field

[0001] The present invention relates to the field of server technology, and in particular to a memory training method, device, electronic equipment and storage medium. Background Art

[0002] When the server starts the Basic Input Output System (BIOS), especially when it is cold started, memory training is required.

[0003] The server memory training process involves a large number of test algorithms and test scenarios, which account for a large proportion of the total time spent in the entire BIOS boot process. How to enable the memory to complete memory training quickly to shorten the BIOS boot time is an important issue that the industry needs to solve urgently. Summary of the invention

[0004] The present invention provides a memory training method, device, electronic equipment and storage medium, which are used to quickly complete memory training, thereby shortening the BIOS startup time.

[0005] The present invention provides a memory training method, comprising the following steps: Based on multiple memory modules in the server, memory training codes in a basic input and output system BIOS startup process of the server are divided to obtain memory training codes corresponding to each memory module; Allocating memory training codes corresponding to each memory module to each core of a processor in the server, so that each core executes a memory training process of the corresponding memory module based on the allocated code during BIOS startup; Based on reading the value of the memory training flag of each core, it is determined that the memory training of the server is completed. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0006] According to a memory training method provided by the present invention, based on multiple memory modules in a server, memory training codes in a basic input and output system BIOS startup process of the server are divided to obtain memory training codes corresponding to each memory module, including: Based on the multiple memory modules in the server, searching in the memory training code in the BIOS startup process to determine the starting position code for performing memory training on each memory module; Based on the starting position code, the memory training code in the BIOS startup process is divided to obtain the memory training code corresponding to each memory module.

[0007] According to a memory training method provided by the present invention, the memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process, including: Based on the starting position code of the memory training of each memory module, a starting code address is allocated in the reset address register of each core of the processor, and the starting code address is used to determine the address corresponding to the code to be executed by jump; De-resetting each core so that the core can execute the memory training process of the corresponding memory module after the de-resetting is completed; The kernel executes a memory training process of a corresponding memory module, including: Read the kernel number stored in the register of the kernel, and based on the kernel number and the start code address stored in the reset address register in the kernel, determine the execution position of the memory training code in the BIOS startup process to jump to, and determine the allocated execution code based on the execution position to execute the memory training process of the corresponding memory module.

[0008] According to a memory training method provided by the present invention, before allocating the memory training code corresponding to each memory module to each core of the processor in the server, the method further includes: The code of the BIOS startup process is divided to obtain a BIOS early initialization code and a memory training code during the BIOS startup process, wherein the BIOS early initialization code is used to execute an initialization process before memory training; Determine that the early initialization code is executed to completion.

[0009] According to a memory training method provided by the present invention, the determination of completion of the memory training of the server based on reading the value of the memory training flag bit of each core includes: The value of the memory training flag of each core is read cyclically, and when it is determined that the training of the memory module corresponding to each core is completed based on the value of the memory training flag of all cores of the server, it is determined that the memory training of the server is completed.

[0010] According to a memory training method provided by the present invention,

[0011] The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: Obtaining a NUMA topology correspondence relationship of the processor; Based on the NUMA topology correspondence, the correspondence between the core and the memory in the processor is determined, and based on the correspondence between the core and the memory, the memory training code corresponding to each memory module is allocated to each core of the processor in the server.

[0012] According to a memory training method provided by the present invention, after determining that the memory training of the server is completed, the method further includes: A master core is determined from multiple cores in the processor, a subsequent BIOS startup process is executed based on the master core, and all slave cores are stopped until the BIOS startup is completed. The slave cores are cores in the processor other than the master core.

[0013] The present invention also provides a memory training device, comprising the following modules: A partitioning module, for partitioning the memory training code in the basic input and output system BIOS startup process of the server based on multiple memory modules in the server, to obtain the memory training code corresponding to each memory module; An allocation module, used to allocate the memory training code corresponding to each memory module to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process; A memory training module is used to determine whether the memory training of the server is completed based on reading the value of the memory training flag of each core. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any of the memory training methods described above is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the memory training method described in any one of the above is implemented.

[0016] The memory training method, device, electronic device and storage medium provided by the present invention divide the memory training code in the BIOS startup process, and distribute the memory training code corresponding to each memory module to each core of the processor, so that each core can execute the memory training process of multiple memory modules in the server in parallel based on the distributed code during the BIOS startup process, so as to quickly complete the memory training process. By enabling multi-core parallel execution of memory training, the memory training time is shortened, thereby shortening the BIOS startup time, and improving the user experience and work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the BIOS startup process in the related method.

[0019] Figure 2 It is a flowchart of the memory training method provided by the present invention.

[0020] Figure 3 It is a schematic diagram of the structure of the BIOS startup code provided by the present invention in a storage medium.

[0021] Figure 4 It is a schematic diagram of the memory training execution flow of the multi-core processor provided by the present invention.

[0022] Figure 5 It is a structural schematic diagram of the memory training device provided by the present invention.

[0023] Figure 6 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] When the server starts the BIOS, especially when it is cold started (cold start means powering on after power off), memory training is required. The reasons are as follows: Different memory modules (even with the same specifications and models) may have subtle differences in physical characteristics. Memory training helps ensure that the memory controller can communicate with the memory modules in an optimal manner, thereby improving system stability and compatibility; memory training fine-tunes various parameters of the memory controller (such as timing and voltage) to achieve optimal performance of the memory subsystem; memory training helps ensure the integrity and accuracy of data during transmission from the memory controller to the memory module; the time at which control signals, command signals, and clocks arrive at the dual-inline memory modules (Dual-Inline-Memory-Modules, DIMMs) is inconsistent, and memory training is to align these signals; the memory access link consists of multiple parts, and each part may introduce problems of clock asynchrony and sampling delay. Memory training can align each part separately to make the hundreds of connections of the memory DIMMs uniform.

[0026] The server memory training process involves a large number of test algorithms and test scenarios, which accounts for a large proportion of the total time spent in the entire BIOS startup process. However, memory training is usually an inevitable and omitted process. For customers who have requirements for server startup time, memory training takes a long time and is an obvious time-consuming bottleneck.

[0027] Unified Extensible Firmware Interface (UEFI) is a single-core, single-threaded framework. In the related methods, the server BIOS adopts the UEFI framework, and the entire BIOS boot process of the server, including the memory training process, is completed by a single CPU core. Here, this CPU core is recorded as CORE 0; Figure 1 This is a schematic diagram of the BIOS startup process in the relevant method. Figure 1 The middle left side is the BIOS startup process. Figure 1 On the right is the structure of the BIOS code in the storage medium; After CORE 0 starts, it starts to execute BIOS instruction codes from Address A, the starting position code of the BIOS initialization process, and BIOS starts to start. At this time, the CPU is still in an uninitialized state, and the CPU can only execute some simple basic instructions. CORE 0 cannot directly start memory training. CORE 0 needs to perform some initialization of the CPU internal bus and internal links before the CPU can run normally and fully function; BIOS is implemented based on the UEFI framework, and CORE 0 also needs to prepare the UEFI usage environment. After UEFI is initialized, UEFI can be used normally; before memory training, CORE 0 needs to execute these processes, which are collectively referred to as BIOS early initialization. BIOS early initialization is completed by CORE 0 alone; After CORE 0 completes the BIOS initialization, CORE 0 fetches the code from the memory initialization code Address B and starts to perform memory training until CORE 0 completes the training of all memories. The entire process from CORE 0 starting to complete memory training is completed by CORE 0 alone.

[0028] After completing the memory training, CORE 0 continues to execute BIOS until the BIOS boot is completed.

[0029] The disadvantages of the related methods are: Since UEFI is a single-core, single-threaded framework, the server BIOS uses the UEFI architecture, so the entire BIOS startup process, including memory training, can only be executed sequentially by CORE 0 alone. Since memory training itself takes a long time, this causes the BIOS startup to take a long time; Since the memory training process takes a long time, the BIOS startup time is longer. Some customers are sensitive to the server startup time, and they will greatly discount their satisfaction with the company's products, which in turn leads to a reduction in the company's product competitiveness in the market, which has a negative impact on the company's benefits.

[0030] In view of the defects in the related methods, the present invention provides a memory training method. Figure 2 is a flow chart of the memory training method provided by the present invention, such as Figure 2 As shown, the method includes the following: Step 210, based on multiple memory modules in the server, dividing the memory training code in the basic input and output system BIOS startup process of the server to obtain the memory training code corresponding to each memory module; Step 220, assigning the memory training code corresponding to each memory module to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the assigned code during the BIOS startup process; Step 230, based on reading the value of the memory training flag of each core, determine that the memory training of the server is completed, the memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0031] The following takes the execution of the memory training method provided by the present invention by a core of a processor in a server as an example to describe in detail the technical solution of the present invention.

[0032] In step 210, based on multiple memory modules in the server, the memory training code in the basic input and output system BIOS startup process of the server is divided to obtain the memory training code corresponding to each memory module.

[0033] The server contains multiple memory modules. Memory modules, also known as memory bars or memory boards, are an important form of computer memory, specifically used to store and read data and instructions. It is an important part of computer memory. Through memory modules, the CPU can quickly access data in the memory, thereby increasing the operating speed of the system.

[0034] All codes in the BIOS startup process of the server are obtained, and memory training codes in all codes are obtained. The memory training code is used to complete the memory training process for each memory module in the server during the BIOS startup process of the server.

[0035] According to the memory modules of the server, the memory training code in the BIOS startup process is divided to obtain the memory training code corresponding to each memory module. It should be noted that the memory training process of the memory module can be completed by executing the memory training code corresponding to each memory module.

[0036] In step 220, the memory training code corresponding to each memory module is distributed to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the distributed code during the BIOS startup process.

[0037] After the memory training code in the entire BIOS startup process is divided, the memory training code corresponding to each memory module is allocated to each core of the processor in the server. The processor of the server includes multiple cores.

[0038] Optionally, the allocation process can be implemented based on the Non-Uniform Memory Access (NUMA) topological correspondence of the processor cores. Topological correspondence is a core concept in the NUMA architecture, which describes the organization between the processor (CPU) cores and the memory modules. In the NUMA architecture, the system is divided into multiple nodes, each of which contains a memory module and a set of CPU cores associated with it.

[0039] In the NUMA architecture, each processor core directly accesses the memory module of the NUMA node where it is located. During the allocation process, based on the correspondence between memory and cores in the NUMA architecture, the memory training code corresponding to each memory module is allocated to each core of the processor in the server.

[0040] After the allocation is completed, each core executes the allocated code during the BIOS startup process to implement the memory training process of the corresponding memory module.

[0041] It is understandable that completing the memory training process of multiple memory modules in the server in parallel based on multiple cores can greatly improve the efficiency of memory training of the entire server during the BIOS startup process and shorten the BIOS startup time.

[0042] In step 230, based on reading the value of the memory training flag of each core, it is determined that the memory training of the server is completed. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0043] Optionally, a memory training flag can be set in the register of each core. For the memory training flag, the initial value is 0.

[0044] After the kernel executes the training code, the value 0 in the memory training flag of the kernel is changed to 1. By traversing the memory training flags in the registers of all kernels, it can be determined whether all memory modules of the server have completed memory training, thereby determining whether the memory training process in the server BIOS startup process has been completed.

[0045] Optionally, the cores in the server's processor can be divided into CORE 0-CORE n. CORE 0 is the master core and CORE 1-CORE n are slave cores. Memory training for the BIOS boot process can be implemented based on the master core CORE 0. The storage structure of the BIOS boot code in the storage medium can be divided into three parts, such as Figure 3The structural diagram of the BIOS startup code provided by the present invention in the storage medium is shown as follows. It is mainly divided into three parts: BIOS starting position code, the address is recorded as Address_A; BIOS early initialization code; BIOS memory training code, where the memory training code is divided into n parts, recorded as part(1,n), and the addresses of these n parts of code in the storage medium are respectively Address_B(1,n), and these n parts of training code (1,n) are executed separately by n CPU COREs in the processor.

[0046] Specifically, the specific execution process can be as follows Figure 4 The memory training execution flow diagram of the multi-core processor provided by the present invention is shown in FIG.

[0047] Each CPU CORE has an MPID register, which stores the core number of the CORE. The MPID register value of CORE 0 is 0, and the MPID register value of CORE 1 is 1. Similarly, the MPID register value of CORE n is n. The CPU CORE determines which CORE is currently running and executing the code by reading the value of its own MPID register. Figure 3 The BIOS start code Address_A is a judgment and jump address code. The function of this code is: CPUCORE reads the value of the MPID register, and the CPU CORE determines which CPU core is executing the current code based on the value of MPID; if it is CORE 0, CORE does not jump and continues to execute the code sequentially; if it is CORE 1, CORE 1 directly jumps to Figure 3 Memory training code part 1, the code starts executing at the address Address_B1; similarly, if it is CORE n, CORE n jumps directly to Figure 3 Memory training code part n, code execution starts at the address Address_Bn; Each CPU CORE has a reset address register, which specifies the starting address of the code to be executed after the CPU CORE is reset. The reset address register of CORE 0 stores the starting address of the BIOS code, Address_A. CORE 0 starts to execute the code from the starting address_A of the BIOS. CORE 0 reads the MPID register, and the MPID value is 0, so CORE 0 confirms that it is currently executing the code. CORE 0 continues to execute the early initialization code of BIOS. This part of the code is executed by CORE 0 alone. After CORE 0 completes the initialization of BIOS, CORE 0 will not start memory training immediately. After core 0 sets the reset address registers of CORE (1,n) to Address_A, CORE 0 resets the n slave cores CORE (1,n); taking CORE1 as an example, CORE 1 starts to start, CORE 1 starts to fetch instructions from the BIOS starting position Address_A, CORE 1 reads the MPID register, CORE 1 confirms that it is currently CORE 1 that is fetching instructions and executing the code, CORE 1 directly jumps to the memory training code part 1 to fetch instructions and execute, after CORE 1 executes the memory training code part 1, CORE 1 sets Finish_Flag_1 to 1 (the default value of Finish_Flag_1 is 0) to mark that CORE 1 has completed the execution of the memory training code part 1; similar to CORE 1, all slave cores CORE (1,n) execute the memory training part (1,n) code in parallel; that is, CORE 2 executes part 2, and CORE n executes part n; CORE 0 loops to check the value of Finish_Flag_(1,n) until all flags are 1, which means that all slave cores have completed the function code of their respective memory training parts; only when all flags are 1, CORE 0 will continue to execute, otherwise CORE 0 continues to wait; CORE 0 resets CORE (1,n), and all slave cores stop running; CORE 0 continues to run until BIOS boot is completed.

[0048] The memory training method provided by the present invention divides the memory training code in the BIOS startup process, and distributes the memory training code corresponding to each memory module to each core of the processor, so that each core can execute the memory training process of multiple memory modules in the server in parallel based on the distributed code during the BIOS startup process, thereby quickly completing the memory training process. By enabling multi-core parallel execution of memory training, the memory training time is shortened, thereby shortening the BIOS startup time, and improving user experience and work efficiency.

[0049] In one embodiment, based on multiple memory modules in a server, memory training codes in a basic input and output system BIOS startup process of the server are divided to obtain memory training codes corresponding to each memory module, including: based on multiple memory modules in the server, searching in the memory training codes in the BIOS startup process to determine a starting position code for memory training of each memory module; based on the starting position code, dividing the memory training codes in the BIOS startup process to obtain memory training codes corresponding to each memory module.

[0050] Obtain all codes of the server's BIOS startup process, and determine the memory training code in all codes. After determining the memory training code in the system BIOS startup process, since each memory module will be trained during the server BIOS startup process, the memory training code of each memory module can be determined from the memory training code in the BIOS startup process.

[0051] Search the memory training code during the BIOS startup process to determine the starting position code for memory training of each memory module.

[0052] After determining the starting position code for memory training of each memory model, the memory training code in the BIOS startup process is divided based on the multiple starting position codes to obtain the memory training code corresponding to each memory module.

[0053] In one embodiment, the memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process, including: based on the starting position code for memory training of each memory module, a starting code address is allocated in the reset address register of each core of the processor, and the starting code address is used to determine the address corresponding to the code for jump execution; each core is reset, so that the core executes the memory training process of the corresponding memory module after the reset is completed; the core executes the memory training process of the corresponding memory module, including: reading the core number stored in the register of the core, and based on the core number and the starting code address stored in the reset address register of the kernel, determining the execution position of the memory training code in the BIOS startup process to jump to, and determining the allocated execution code based on the execution position to execute the memory training process of the corresponding memory module.

[0054] According to the memory training start position code of each memory module determined previously, a corresponding start code address is assigned to each core.

[0055] Configure the reset address registers of each core. These registers store the starting address of the code that the core should jump to after reset. For memory training, this starting address is a pointer to the code segment for memory training during BIOS startup.

[0056] Write the start code address of each core into its reset address register. In this way, when the core is released from reset, it will jump to the corresponding memory training code according to this address.

[0057] After configuration is complete, the cores in the processor are reset one by one. The reset operation causes the core to start executing the code stored in the reset address register.

[0058] Each core can read its MPID register or other similar identifier at boot time to determine its own core number or location. This core number is then used to determine which memory module's memory training code should be executed.

[0059] Among them, the MPID register (Multiprocessor ID Register) is an important register used to identify the processor core in a multiprocessor system. It is usually used in a multi-core or multi-processor architecture to ensure that each processor can uniquely identify and communicate.

[0060] The core calculates the execution location of the specific memory training code to jump to based on its core number and the starting code address in the reset address register.

[0061] Once the kernel jumps to the correct execution location, it will start executing the memory training code for its corresponding memory module. These codes will perform a series of memory read, write and test operations to verify the reliability and stability of the memory module.

[0062] In one embodiment, before allocating the memory training code corresponding to each memory module to each core of the processor in the server, it also includes: dividing the code of the BIOS startup process to obtain a BIOS early initialization code and a memory training code during the BIOS startup process, wherein the BIOS early initialization code is used to execute the initialization process before memory training; and determining that the early initialization code has been executed.

[0063] It is understandable that before the BIOS is trained for memory, a series of initialization operations must be performed.

[0064] The codes of the BIOS startup process are divided to obtain the BIOS early initialization code and the memory training code in the BIOS startup process. First, the BIOS early initialization code is executed to complete the BIOS early initialization process.

[0065] After the BIOS completes the early initialization process, the memory training process of the BIOS is completed based on the memory training code obtained during the BIOS startup process.

[0066] In one embodiment, based on reading the value of the memory training flag of each core, determining that the memory training of the server is completed includes: cyclically reading the value of the memory training flag of each core, and determining that the memory training of the server is completed when it is determined that the training of the memory modules corresponding to each core is completed based on the values ​​of the memory training flag of all cores of the server.

[0067] Based on the value of the memory training flag of all the cores of the server, it is determined that the training of the memory modules corresponding to each core is completed, including: when it is determined that the memory training flag of all the cores of the server is 1, it is determined that the memory training of the server is completed; the memory training flag of each core is initialized to 0, and after the core completes the memory training of the corresponding memory module, the memory training flag in the register of the core is changed from 0 to 1.

[0068] During the memory training process, each core has a specific memory training flag to indicate whether the core has completed memory training. The functions of this flag include: The value of the flag (usually 0 or 1) indicates the status of memory training. 0 means not completed, and 1 means completed.

[0069] First, the memory training flags of all cores are initialized to 0, indicating that the memory training has not been completed. After each core completes the memory training of its corresponding memory module, it updates its own memory training flag from 0 to 1. The memory training flags of each core are read periodically to check their status.

[0070] By looping and reading the memory training flag of each core, you can determine whether all cores have completed memory training. When the flags of all cores are 1, it can be confirmed that the server's memory training has been successfully completed. If the flag of a core is still 0, the system needs to continue looping and reading until all cores have completed memory training.

[0071] In one embodiment, the memory training codes corresponding to each memory module are allocated to each core of the processor in the server, including: obtaining the non-uniform memory access NUMA topology correspondence of the processor; based on the NUMA topology correspondence, determining the correspondence between the core and the memory in the processor, and based on the correspondence between the core and the memory, allocating the memory training codes corresponding to each memory module to each core of the processor in the server.

[0072] The allocation process is implemented based on the Non-Uniform Memory Access (NUMA) topological correspondence of the processor cores. Topological correspondence is a core concept in the NUMA architecture, which describes the organization between the processor (CPU) cores and the memory modules. In the NUMA architecture, the system is divided into multiple nodes, each of which contains a memory module and a set of CPU cores associated with it.

[0073] After obtaining the NUMA topology correspondence, it is necessary to further analyze the mapping relationship between each NUMA node and the processor. Based on the mapping relationship between the NUMA node and the processor, the correspondence between the core and the memory in the processor can be further determined.

[0074] According to the correspondence between the core and the memory, the memory training code corresponding to the memory module is allocated to the corresponding core of the processor, thereby realizing the allocation process of the memory training code. It can be understood that by obtaining the NUMA topology correspondence of the processor, determining the correspondence between the core and the memory, and allocating the memory training code based on the determined correspondence, the system resources can be utilized to the maximum extent and the performance can be improved.

[0075] In one embodiment, after determining that the memory training of the server is completed, it also includes: determining a main core from multiple cores in the processor, executing a subsequent BIOS startup process based on the main core, and stopping all slave cores from running until the BIOS startup is completed. The slave core is a core in the processor other than the main core.

[0076] After confirming that memory training is complete, the BIOS needs to continue executing the subsequent boot process, and in this process, it needs to properly manage the multiple cores of the processor.

[0077] The BIOS determines the main core from the multiple cores of the processor, and then hands over the subsequent boot process to the main core for execution, which includes a series of complex operations such as loading the operating system boot program, initializing hardware devices, and configuring system parameters.

[0078] For slave cores, they are other cores in the processor besides the master core. After the memory training is completed, in order to optimize the use of system resources and reduce potential interference, these slave cores are stopped until the BIOS boot is completed. This strategy helps ensure that the master core can focus on executing the boot process without being affected by the activities of other cores.

[0079] The memory training device provided by the present invention is described below. The memory training device described below and the memory training method described above can be referenced to each other.

[0080] like Figure 5 As shown, the device comprises: A partitioning module 510 is used to partition the memory training code in the basic input and output system BIOS startup process of the server based on multiple memory modules in the server to obtain the memory training code corresponding to each memory module; The allocation module 520 is used to allocate the memory training code corresponding to each memory module to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process; The memory training module 530 is used to determine whether the memory training of the server is completed based on reading the value of the memory training flag of each core. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0081] The memory training device provided by the present invention divides the memory training code in the BIOS startup process, and distributes the memory training code corresponding to each memory module to each core of the processor, so that each core can execute the memory training process of multiple memory modules in the server in parallel based on the distributed code during the BIOS startup process, thereby quickly completing the memory training process. By enabling multi-core parallel execution of memory training, the memory training time is shortened, thereby shortening the BIOS startup time, and improving user experience and work efficiency.

[0082] In one embodiment, the partitioning module 510 is specifically configured to: The method divides the memory training code in the process of starting the basic input and output system BIOS of the server based on multiple memory modules in the server to obtain the memory training code corresponding to each memory module, including: Based on the multiple memory modules in the server, searching in the memory training code in the BIOS startup process to determine the starting position code for performing memory training on each memory module; Based on the starting position code, the memory training code in the BIOS startup process is divided to obtain the memory training code corresponding to each memory module.

[0083] In one embodiment, the partitioning module 510 is further specifically configured to: The memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process, including: Based on the starting position code of the memory training of each memory module, a starting code address is allocated in the reset address register of each core of the processor, and the starting code address is used to determine the address corresponding to the code to be executed by jump; De-resetting each core so that the core can execute the memory training process of the corresponding memory module after the de-resetting is completed; The kernel executes a memory training process of a corresponding memory module, including: Read the kernel number stored in the register of the kernel, and based on the kernel number and the start code address stored in the reset address register in the kernel, determine the execution position of the memory training code in the BIOS startup process to jump to, and determine the allocated execution code based on the execution position to execute the memory training process of the corresponding memory module.

[0084] In one embodiment, the allocation module 520 is specifically configured to: Before allocating the memory training codes corresponding to the memory modules to the cores of the processors in the server, the method further includes: The code of the BIOS startup process is divided to obtain a BIOS early initialization code and a memory training code during the BIOS startup process, wherein the BIOS early initialization code is used to execute an initialization process before memory training; Determine that the early initialization code is executed to completion.

[0085] In one embodiment, the memory training module 530 is specifically used to: The step of determining whether the memory training of the server is completed based on reading the value of the memory training flag bit of each core includes: The value of the memory training flag of each core is read cyclically, and when it is determined that the training of the memory module corresponding to each core is completed based on the value of the memory training flag of all cores of the server, it is determined that the memory training of the server is completed.

[0086] In one embodiment, the allocation module 520 is further specifically configured to: The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: Obtaining a NUMA topology correspondence relationship of the processor; Based on the NUMA topology correspondence, the correspondence between the core and the memory in the processor is determined, and based on the correspondence between the core and the memory, the memory training code corresponding to each memory module is allocated to each core of the processor in the server.

[0087] In one embodiment, the memory training module 530 is further specifically configured to: After determining that the memory training of the server is completed, the method further includes: A master core is determined from multiple cores in the processor, a subsequent BIOS startup process is executed based on the master core, and all slave cores are stopped until the BIOS startup is completed. The slave cores are cores in the processor other than the master core.

[0088] Figure 6 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 6 As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630 and a communication bus 640, wherein the processor 610, the communication interface 620 and the memory 630 communicate with each other through the communication bus 640. The processor 610 may call the logic instructions in the memory 630 to execute the memory training method, which includes: based on multiple memory modules in the server, dividing the memory training code in the basic input and output system BIOS startup process of the server, and obtaining the memory training code corresponding to each memory module; Allocating memory training codes corresponding to each memory module to each core of a processor in the server, so that each core executes a memory training process of the corresponding memory module based on the allocated code during BIOS startup; Based on reading the value of the memory training flag of each core, it is determined that the memory training of the server is completed. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0089] In addition, the logic instructions in the above-mentioned memory 630 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0090] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored in a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the memory training method provided by the above methods, the method comprising: based on multiple memory modules in a server, dividing the memory training code in the basic input and output system BIOS startup process of the server, and obtaining the memory training code corresponding to each memory module; Allocating memory training codes corresponding to each memory module to each core of a processor in the server, so that each core executes a memory training process of the corresponding memory module based on the allocated code during BIOS startup; Based on reading the value of the memory training flag of each core, it is determined that the memory training of the server is completed. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0091] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to execute the memory training method provided by the above methods, the method comprising: based on multiple memory modules in a server, dividing the memory training code in the basic input and output system BIOS startup process of the server to obtain the memory training code corresponding to each memory module; Allocating memory training codes corresponding to each memory module to each core of a processor in the server, so that each core executes a memory training process of the corresponding memory module based on the allocated code during BIOS startup; Based on reading the value of the memory training flag of each core, it is determined that the memory training of the server is completed. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

[0092] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0093] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory training method, characterized in that: The method comprises: Based on multiple memory modules in the server, memory training codes in a basic input and output system BIOS startup process of the server are divided to obtain memory training codes corresponding to each memory module; Allocating memory training codes corresponding to each memory module to each core of a processor in the server, so that each core executes a memory training process of the corresponding memory module based on the allocated code during BIOS startup; Based on reading the value of the memory training flag of each core, it is determined that the memory training of the server is completed. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

2. The memory training method according to claim 1, characterized in that: The method divides the memory training code in the process of starting the basic input and output system BIOS of the server based on multiple memory modules in the server to obtain the memory training code corresponding to each memory module, including: Based on the multiple memory modules in the server, searching in the memory training code in the BIOS startup process to determine the starting position code for performing memory training on each memory module; Based on the starting position code, the memory training code in the BIOS startup process is divided to obtain the memory training code corresponding to each memory module.

3. The memory training method according to claim 2, characterized in that: The memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process, including: Based on the starting position code of the memory training of each memory module, a starting code address is allocated in the reset address register of each core of the processor, and the starting code address is used to determine the address corresponding to the code to be executed by jump; De-resetting each core so that the core can execute the memory training process of the corresponding memory module after the de-resetting is completed; The kernel executes a memory training process of a corresponding memory module, including: Read the kernel number stored in the register of the kernel, and based on the kernel number and the start code address stored in the reset address register in the kernel, determine the execution position of the memory training code in the BIOS startup process to jump to, and determine the allocated execution code based on the execution position to execute the memory training process of the corresponding memory module.

4. The memory training method according to claim 1, characterized in that: Before allocating the memory training codes corresponding to the memory modules to the cores of the processors in the server, the method further includes: The code of the BIOS startup process is divided to obtain a BIOS early initialization code and a memory training code during the BIOS startup process, wherein the BIOS early initialization code is used to execute an initialization process before memory training; Determine that the early initialization code is executed to completion.

5. The memory training method according to claim 1, characterized in that: The step of determining whether the memory training of the server is completed based on reading the value of the memory training flag bit of each core includes: The value of the memory training flag of each core is read cyclically, and when it is determined that the training of the memory module corresponding to each core is completed based on the value of the memory training flag of all cores of the server, it is determined that the memory training of the server is completed.

6. The memory training method according to claim 1, characterized in that: The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: Obtaining a NUMA topology correspondence relationship of the processor; Based on the NUMA topology correspondence, the correspondence between the core and the memory in the processor is determined, and based on the correspondence between the core and the memory, the memory training code corresponding to each memory module is allocated to each core of the processor in the server.

7. The memory training method according to claim 1, characterized in that: After determining that the memory training of the server is completed, the method further includes: A master core is determined from multiple cores in the processor, a subsequent BIOS startup process is executed based on the master core, and all slave cores are stopped until the BIOS startup is completed. The slave cores are cores in the processor other than the master core.

8. A memory training device, characterized in that: include: A partitioning module, for partitioning the memory training code in the basic input and output system BIOS startup process of the server based on multiple memory modules in the server, to obtain the memory training code corresponding to each memory module; An allocation module, used to allocate the memory training code corresponding to each memory module to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process; A memory training module is used to determine whether the memory training of the server is completed based on reading the value of the memory training flag of each core. The memory training flag is stored in the register of the core and is used to mark the memory training status of the memory module corresponding to the core.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the memory training method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the memory training method according to any one of claims 1 to 7 is implemented.

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