Method for converting AXI4 bus to Avalon bus and electronic equipment
By using the interface conversion module to identify and process the transmission instructions of the AXI4-Stream bus interface in FPGA inter-chip communication, the operation instructions and data that comply with the Avalon-MM bus interface are directly output, which solves the waste of logical resources and delays in traditional bus interface conversion methods. The problem of data transmission rate has increased.
Patent Information
- Application Number
- CN202310808403.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-03
- Publication Date
- 2025-01-03
Smart Images
Figure CN119248691A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of bus conversion, and in particular to a method and electronic device for converting an AXI4 bus to an Avalon bus. Background Art
[0002] Avalon memory mapped interface (Avalon-MM) is a bus interface based on memory mapping and requires the memory address to be operated during transmission. It is proposed by field programmable gate array (FPGA) manufacturers Intel or Altera. Advanced eXtensible interface Stream (AXI4-Stream) is a bus interface for stream transmission that does not involve memory addresses. It is proposed by FPGA manufacturers AMD or Xilinx.
[0003] When the FPGA internal interconnection bus uses the AXI-Stream bus, the international interconnection protocol (internet protocol, IP) based on the Avalon-MM bus interface cannot be used directly, and bus interface conversion is required. Although FPGA manufacturers provide bus interface conversion IP, it is mainly for bus interface conversion between Avalon-MM and AXI4-MM based on memory mapping, or between Avalon-Stream and AXI4-Stream oriented to data flow.
[0004] However, high-speed communication between FPGA chips usually uses serial high-speed transceivers as physical transmission links and transmits data based on the AXI4-Stream bus interface protocol. When two or more FPGAs transmit data in the above manner, and there are different bus interface devices in the two FPGAs for communication, it is usually necessary to convert the device bus interface to the same AXI4-Stream bus interface before communication can be carried out.
[0005] For example, the master device is an AXI4-MM bus interface and the slave device is an Avalon-MM bus interface. If the master device wants to access the slave device, the traditional bus conversion method is: on the master device side, the AXI4-MM bus interface is converted to an AXI4-Stream bus interface, and on the slave device side, the AXI4-Stream interface is first converted to an AXI4-MM bus interface, and then the AXI4-MM interface is converted to an Avalon-MM bus interface.
[0006] The traditional bus conversion method requires multiple bus interface conversions. Each interface conversion consumes a certain amount of logic resources in the FPGA, and the bus interface conversion will also cause transmission delays, affecting the data transmission rate. Summary of the invention
[0007] In an exemplary embodiment of the present application, a method and device for converting an AXI4 bus to an Avalon bus are provided to reduce the logic resources consumed during the interface conversion process and to increase the data transmission rate.
[0008] According to a first aspect of an exemplary embodiment, a method for converting an AXI4 bus to an Avalon bus is provided, the method being applied to a first device, the bus interface of the first device comprising an AXI4-Stream bus transmitting interface and an AXI4-Stream bus receiving interface, and the bus interface of the second device being an Avalon-MM bus interface; the first device comprising an interface conversion module, the method comprising:
[0009] The interface conversion module receives the transmission instruction from the second device through the AXI4-Stream bus transmission interface;
[0010] The interface conversion module identifies the type of transmission instruction;
[0011] If the transmission instruction is a write operation instruction, the interface conversion module outputs the write operation instruction and write data according to the Avalon-MM bus interface protocol specification;
[0012] If the transmission instruction is a read operation instruction, the interface conversion module outputs the read operation instruction and obtains the read data according to the Avalon-MM bus interface protocol specification, and outputs the read data through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification.
[0013] According to a second aspect of an exemplary embodiment, an electronic device is provided, the electronic device is a first device, the bus interface of the first device includes an AXI4-Stream bus transmission interface and an AXI4-Stream bus reception interface, the bus interface of the second device is an Avalon-MM bus interface, the first device includes an interface conversion module, and the interface conversion module includes a processor and a transceiver:
[0014] The transceiver is configured to perform:
[0015] Receiving a transmission instruction from a second device via an AXI4-Stream bus sending interface;
[0016] A processor configured to execute:
[0017] Identify the type of transmission instruction;
[0018] If the transmission instruction is a write operation instruction, the write operation instruction and write data are output according to the Avalon-MM bus interface protocol specification;
[0019] If the transmission instruction is a read operation instruction, the read operation instruction is output according to the Avalon-MM bus interface protocol specification and the read data is obtained, and the read data is output according to the AXI4-Stream bus interface protocol specification through the AXI4-Stream bus receiving interface.
[0020] According to a third aspect of an exemplary implementation, an interface conversion module is provided, which is applied to a first device, wherein the bus interface of the first device includes an AXI4-Stream bus transmission interface and an AXI4-Stream bus reception interface, and the bus interface of the second device is an Avalon-MM bus interface. The interface conversion module includes:
[0021] The data transmission unit is used to: receive a transmission instruction from a second device through an AXI4-Stream bus sending interface;
[0022] an identification unit, used for identifying the type of transmission instruction;
[0023] The data transmission unit is further used for: if the transmission instruction is a write operation instruction, outputting the write operation instruction and write data according to the Avalon-MM bus interface protocol specification;
[0024] The data transmission unit is also used to: if the transmission instruction is a read operation instruction, output the read operation instruction and obtain the read data according to the Avalon-MM bus interface protocol specification, and output the read data according to the AXI4-Stream bus interface protocol specification through the AXI4-Stream bus receiving interface.
[0025] According to a fourth aspect of the exemplary implementation, a computer storage medium is provided, in which computer program instructions are stored. When the instructions are executed on a computer, the computer executes the method of converting an AXI4 bus to an Avalon bus as in the first aspect.
[0026] In the embodiment of the present application, in the face of the problem that the AXI4-Stream bus interface cannot access the Avalon-MM bus interface device, an interface conversion module is set at the first device (slave device) end. The interface conversion module can send an interface through the AXI4-Stream bus, receive a transmission instruction from the second device (master device), and first identify whether the transmission instruction is a write operation instruction or a read operation instruction. When the transmission instruction is a write operation instruction, the interface conversion module outputs the write operation instruction and write data according to the Avalon-MM bus interface protocol specification; when the transmission instruction is a read operation instruction, the read operation instruction is output according to the Avalon-MM bus interface protocol specification and the read data is obtained, and the read data is output according to the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification. Compared with the traditional bus interface conversion method, the logical resources consumed by the interface conversion and the transmission delay caused by the protocol conversion are reduced, and the transmission efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0028] Figure 1 A schematic diagram of a bus interface conversion method in a related art provided by an embodiment of the present application is exemplified;
[0029] Figure 2 An application scenario diagram of a bus interface conversion method provided by an embodiment of the present application is exemplarily shown;
[0030] Figure 3 A schematic diagram showing, by way of example, a function of converting an AXI4-Stream bus interface to an Avalon-MM bus interface provided by an embodiment of the present application;
[0031] Figure 4 A flowchart of a method for converting an AXI4 bus to an Avalon bus provided by an embodiment of the present application is exemplified;
[0032] Figure 5 A schematic diagram of a write operation frame format of an AXI4-Stream bus sending interface provided in an embodiment of the present application is exemplarily shown;
[0033] Figure 6 A schematic diagram of an AXI4-Stream bus sending interface read operation frame format provided in an embodiment of the present application is exemplarily shown;
[0034] Figure 7 A schematic diagram of outputting a write operation instruction and write data according to the Avalon-MM bus interface protocol provided by an embodiment of the present application is exemplified;
[0035] Figure 8 A schematic diagram of outputting a read instruction and receiving read data according to the Avalon-MM bus interface protocol provided by an embodiment of the present application is exemplified;
[0036] Fig. 9 A schematic diagram of a read data frame format of an AXI4-Stream bus receiving interface provided in an embodiment of the present application is exemplarily shown;
[0037] Fig.10 The following is a schematic diagram showing the structure of an interface conversion module provided in an embodiment of the present application;
[0038] Fig.11 A structural diagram of a first device provided in an embodiment of the present application is exemplarily shown. DETAILED DESCRIPTION
[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.
[0040] For ease of understanding, the terms involved in the embodiments of the present application are explained below:
[0041] (1) For the sake of convenience, the AXI4-Stream bus is called the first bus; the Avalon-MM bus is called the second bus; the AXI-MM bus is called the third bus; the AXI4 bus is called the fourth bus; and Avalon is called the fifth bus.
[0042] High-speed communication between FPGA chips usually uses serial high-speed transceivers as physical transmission links and transmits data based on the AXI4-Stream bus interface protocol. When two or more FPGAs transmit data in the above manner, and there are different bus interface devices in the two FPGAs for communication, it is usually necessary to convert the device bus interface to the same AXI4-Stream bus interface before communication can be carried out.
[0043] For example, the master device is an AXI4-MM bus interface and the slave device is an Avalon-MM bus interface. If the master device wants to access the slave device, the traditional bus conversion method is: on the master device side, the AXI4-MM bus interface is converted to an AXI4-Stream bus interface, and on the slave device side, the AXI4-Stream interface is first converted to an AXI4-MM bus interface, and then the AXI4-MM interface is converted to an Avalon-MM bus interface.
[0044] The traditional bus conversion method requires multiple bus interface conversions. Each interface conversion consumes a certain amount of logic resources in the FPGA, and the bus interface conversion will also cause transmission delays, affecting the data transmission rate. Figure 1 The figure is a schematic diagram of a bus interface conversion method in the related art, wherein multiple conversions are required, thereby causing a waste of logic resources.
[0045] To this end, the embodiment of the present application provides a method for converting an AXI4 bus to an Avalon bus, specifically a method for converting an AXI4-Stream bus interface to an Avalon-MM bus interface, the method is applied to a first device, the first device is a slave device, and its bus interface includes an AXI4-Stream bus sending interface and an AXI4-Stream bus receiving interface, the second device is a master device, and its bus interface is an Avalon-MM bus interface; the first device includes an interface conversion module. In this method, the interface conversion module receives a transmission instruction from the second device through the AXI4-Stream bus sending interface; identifies the type of the transmission instruction; if the transmission instruction is a write operation instruction, outputs the write operation instruction and write data according to the Avalon-MM bus interface protocol specification; if the transmission instruction is a read operation instruction, outputs the read operation instruction and obtains the read data according to the Avalon-MM bus interface protocol specification, and outputs the read data according to the AXI4-Stream bus interface protocol specification through the AXI4-Stream bus receiving interface. Through such a design, the first device realizes the correct reception of read data and read instructions from the second device, or, write data and write instructions, and completes the conversion of the AXI4-Stream bus interface to the Avalon-MM bus interface.
[0046] After introducing the design ideas of the embodiments of the present application, the following briefly introduces the application scenarios to which the technical solutions of the embodiments of the present application can be applied. It should be noted that the application scenarios introduced below are only used to illustrate the embodiments of the present application and are not limited. In specific implementation, the technical solutions provided by the embodiments of the present application can be flexibly applied according to actual needs.
[0047] refer to Figure 2, shows an application scenario diagram of a bus interface conversion method, wherein the first device is a slave device and the second device is a master device. In a specific example, the first device and the second device can both be FPGA chips, for example, the first device is FPGA1 and the second device is FPGA2. Figure 2 As can be seen, the number of conversions is much less than Figure 1 The number of conversions can be avoided, thereby avoiding the waste of logic resources and increasing the data transmission rate.
[0048] To further illustrate the technical solution provided by the embodiment of the present application, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiment of the present application provides the method operation steps shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In the steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided in the embodiment of the present application.
[0049] Combine the following Figure 2 The application scenario shown is shown in Figure 3 A schematic diagram of an AXI4-Stream bus interface to Avalon-MM bus interface function is shown, wherein the first device is a slave device, and the bus interface of the first device includes an AXI4-Stream bus sending interface and an AXI4-Stream bus receiving interface, the second device is a master device, and the bus interface of the first device is an Avalon-MM bus interface, and the first device includes an interface conversion module, and the interface conversion module of the first device is used to realize the conversion of the AXI4-Stream bus interface to the Avalon-MM bus interface.
[0050] Figure 3 In the figure, “first” represents the data related to AXIS, and “second” represents the data related to Avalon. The interface module is the Avalon-MM interface module, and the interface conversion module is the AXI-Stream to Avalon-MM module.
[0051] refer to Figure 4 A flowchart of a method for converting an AXI4 bus to an Avalon bus is shown, and the method is applied to an interface conversion module of a first device to illustrate the technical solution provided in an embodiment of the present application.
[0052] S401: The interface conversion module sends an interface through the first bus (AXI4-Stream bus) to receive a transmission instruction from the second device.
[0053] S402: The interface conversion module identifies the type of the transmission instruction.
[0054] S403: If the transmission instruction is a write operation instruction, the interface conversion module outputs the write operation instruction and write data according to the second bus (Avalon-MM bus) interface protocol specification.
[0055] S404: If the transmission instruction is a read operation instruction, the interface conversion module outputs the read operation instruction and obtains the read data according to the interface protocol specification of the second bus (Avalon-MM bus), and outputs the read data according to the protocol specification of the first bus (AXI4-Stream bus) through the first bus (AXI4-Stream bus) receiving interface.
[0056] In the embodiment of the present application, in the face of the problem that the AXI4-Stream bus interface cannot access the Avalon-MM bus interface device, an interface conversion module is set at the first device (slave device) end. The interface conversion module can send an interface through the AXI4-Stream bus, receive a transmission instruction from the second device (master device), and first identify whether the transmission instruction is a write operation instruction or a read operation instruction. When the transmission instruction is a write operation instruction, the interface conversion module outputs the write operation instruction and write data according to the Avalon-MM bus interface protocol specification; when the transmission instruction is a read operation instruction, the read operation instruction is output according to the Avalon-MM bus interface protocol specification and the read data is obtained, and the read data is output according to the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification. Compared with the traditional bus interface conversion method, the logical resources consumed by the interface conversion and the transmission delay caused by the protocol conversion are reduced, and the transmission efficiency is improved.
[0057] In S401, the interface conversion module sends an interface through the AXI4-Stream bus to receive a transmission instruction from the second device. In the actual application process, the transmission process and the parsing process of the instruction are performed synchronously.
[0058] Among them, the interface conversion module is an AXI-Stream to Avalon-MM module, hereinafter referred to as the interface conversion module. The interface conversion module parses the transmission instruction according to the frame format to obtain the operation frame header, operation address, operation length and / or operation data. Exemplarily, the transmission instruction may be of two types, a write operation instruction and a read operation instruction. If it is a write operation instruction, the frame format of the write operation instruction is: write operation frame header, write operation address, write operation length and write data; if it is a read operation instruction, the frame format of the read operation instruction is: read operation frame header, read operation address and read operation length.
[0059] Figure 5 A schematic diagram of an AXI4-Stream bus sending interface write operation instruction frame format provided in an embodiment of the present application, Figure 6A schematic diagram of an AXI4-Stream bus sending interface read operation instruction frame format provided in an embodiment of the present application.
[0060] In the actual application process, the interface conversion module determines that the transmission instruction has been received by parsing the first setting signal identification frame received from the second device. This design allows the interface conversion module to accurately obtain the complete transmission instruction and avoid data loss during the transmission process. Optionally, the first setting signal identification frame can be the tx_last signal identification frame of the AXI4-Stream bus sending interface.
[0061] In S402, the interface conversion module identifies the operation frame header to determine whether the operation frame header is a read operation frame header or a write operation frame header, and further identifies the type of the transmission instruction as a read operation instruction or a write operation instruction.
[0062] In S403, when the transmission instruction is a write operation instruction, the interface conversion module outputs the write operation instruction and write data according to the Avalon-MM bus interface protocol specification.
[0063] For example, when there are multiple write data, after the first write data transmission is completed, the interface conversion module can output a write operation instruction according to the Avalon-MM bus interface protocol specification, and output other write data in sequence. The write operation instruction here includes a write operation address and a write operation length.
[0064] Figure 7 A schematic diagram of outputting write operation instructions and write data according to the Avalon-MM bus interface protocol is provided in an embodiment of the present application.
[0065] In case S404 is involved and the transmission instruction is a read operation instruction, the interface conversion module outputs the read operation instruction and obtains the read data according to the Avalon-MM bus interface protocol specification, and outputs the read data according to the AXI4-Stream bus interface protocol specification through the AXI4-Stream bus receiving interface.
[0066] Exemplarily, the interface conversion module outputs a read operation instruction according to the Avalon-MM bus interface protocol specification; wherein the read operation instruction includes a read operation address and a read operation length. In addition, due to the difference between the read operation instruction and the write operation instruction, the transmission instruction does not include read data. Therefore, in the case of the read operation instruction, it is necessary to obtain the read data according to the read operation length at the read operation address. In this way, after the interface conversion module obtains the read data, it outputs the read data according to the AXI4-Stream bus protocol interface specification.
[0067] Figure 8A schematic diagram of outputting read instructions and receiving read data according to the Avalon-MM bus interface protocol is provided in an embodiment of the present application. Fig. 9 A schematic diagram of an AXI4-Stream bus receiving interface read data frame format provided in an embodiment of the present application. In a specific example, the output read data frame format can refer to Fig. 9 , including reading data frame header and reading data.
[0068] In the actual application process, the interface conversion module receives the second setting signal identification frame from the second device through the AXI4-Stream bus interface to determine that the transmission instruction has been processed. This design allows the interface conversion module to accurately parse the complete transmission instruction and ensure that the data processing is completed. Optionally, the second setting signal identification frame can be the tx_last signal identification frame of the AXI4-Stream bus receiving interface.
[0069] In summary, in the embodiment of the present application, in view of the AXI4-Stream bus interface characteristics, the interface conversion module provides two sets of AXI4-Stream bus interfaces for sending and receiving, that is, the AXI4-Stream bus sending interface and the AXI4-Stream bus receiving interface. In view of the Avalon-MM bus being a protocol characteristic based on memory mapping, the memory address, transmission length and other information of the read and write operations are received in accordance with the AXI4-Stream bus interface protocol specification and the fixed frame format, the received data is parsed and cached according to the frame format, and the parsed memory address, transmission length and other information are mapped and output according to the Avalon-MM bus interface protocol specification.
[0070] like Fig.10 As shown, based on the same inventive concept, an embodiment of the present application provides an interface conversion module, which is applied to a first device, wherein the bus interface of the first device includes an AXI4-Stream bus transmission interface and an AXI4-Stream bus reception interface, and the bus interface of the second device is an Avalon-MM bus interface. The interface conversion module includes a data transmission unit 101 and an identification unit 102.
[0071] The data transmission unit 101 is used to: receive a transmission instruction from a second device through an AXI4-Stream bus sending interface;
[0072] An identification unit 102, used to identify the type of the transmission instruction;
[0073] The data transmission unit 101 is further configured to: if the transmission instruction is a write operation instruction, output the write operation instruction and write data according to the Avalon-MM bus interface protocol specification;
[0074] The data transmission unit 101 is also used to: if the transmission instruction is a read operation instruction, output the read operation instruction and obtain read data according to the Avalon-MM bus interface protocol specification, and output the read data through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification.
[0075] In a possible implementation, the method further includes a parsing unit for parsing the transmission instruction according to the frame format before identifying the type of the transmission instruction to obtain an operation frame header, an operation address, an operation length and / or operation data.
[0076] In a possible implementation, the identification unit 102 is specifically configured to: the interface conversion module identifies the type of the transmission instruction, including:
[0077] The interface conversion module determines whether the type of the transmission instruction is a read operation instruction or a write operation instruction by identifying the operation frame header.
[0078] In a possible implementation manner, the data transmission unit 101 is specifically configured to:
[0079] After the first write data transmission is completed, the interface conversion module outputs the write operation instruction according to the Avalon-MM bus interface protocol specification, and outputs other write data in sequence;
[0080] The write operation instruction includes an operation address and an operation length, the operation address is the write operation address, and the operation length is the write operation length.
[0081] In a possible implementation manner, the data transmission unit 101 is specifically configured to:
[0082] The interface conversion module outputs a read operation instruction according to the Avalon-MM bus interface protocol specification; wherein the read operation instruction includes an operation address and an operation length, the operation address is a read operation address, and the operation length is a read operation length;
[0083] The interface conversion module obtains the read data according to the operation address and the operation length, and outputs the read data according to the AXI4-Stream bus protocol interface specification.
[0084] In a possible implementation manner, a determination unit is further included, which is used to determine whether the transmission instruction has been received by parsing the first setting signal identification frame received from the second device before the interface conversion module identifies the type of the transmission instruction.
[0085] In a possible implementation manner, the determining unit is further configured to:
[0086] A second setting signal identification frame received from the second device through the AXI4-Stream bus interface determines that the transmission instruction has been processed.
[0087] Since the device is the device in the method in the embodiment of the present application, and the principle of solving the problem by the device is similar to that of the method, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.
[0088] like Fig.11 As shown, based on the same inventive concept, an embodiment of the present application provides an electronic device, the electronic device is a first device, the bus interface of the first device includes an AXI4-Stream bus sending interface and an AXI4-Stream bus receiving interface, the bus interface of the second device is an Avalon-MM bus interface, the first device includes an interface conversion module, and the interface conversion module includes a processor 1101 and a transceiver 1102:
[0089] The transceiver 1102 is configured to perform:
[0090] Receiving a transmission instruction from a second device via an AXI4-Stream bus sending interface;
[0091] The processor 1101 is configured to execute:
[0092] Identify the type of transmission instruction;
[0093] If the transmission instruction is a write operation instruction, the write operation instruction and write data are output according to the Avalon-MM bus interface protocol specification;
[0094] If the transmission instruction is a read operation instruction, the read operation instruction is output and the read data is obtained according to the Avalon-MM bus interface protocol specification, and the read data is output through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification.
[0095] In a possible implementation, before identifying the type of the transmission instruction, the processor 1101 is specifically configured to execute:
[0096] The transmission instruction is parsed according to the frame format to obtain an operation frame header, an operation address, an operation length and / or operation data.
[0097] In a possible implementation, the processor 1101 is specifically configured to execute:
[0098] The interface conversion module determines whether the type of the transmission instruction is a read operation instruction or a write operation instruction by identifying the operation frame header.
[0099] In a possible implementation, the processor 1101 is specifically configured to execute:
[0100] After the first write data transmission is completed, the interface conversion module outputs the write operation instruction according to the Avalon-MM bus interface protocol specification, and outputs other write data in sequence;
[0101] The write operation instruction includes an operation address and an operation length, the operation address is the write operation address, and the operation length is the write operation length.
[0102] In a possible implementation, the processor 1101 is specifically configured to execute:
[0103] The interface conversion module outputs a read operation instruction according to the Avalon-MM bus interface protocol specification; wherein the read operation instruction includes an operation address and an operation length, the operation address is a read operation address, and the operation length is a read operation length;
[0104] The interface conversion module obtains the read data according to the operation address and the operation length, and outputs the read data according to the AXI4-Stream bus protocol interface specification.
[0105] In a possible implementation manner, before the interface conversion module identifies the type of the transmission instruction, the processor 1101 is further configured to execute:
[0106] The interface conversion module determines that the transmission instruction has been received by parsing the first setting signal identification frame received from the second device.
[0107] In a possible implementation, after outputting the read data according to the AXI4-Stream bus interface protocol specification through the AXI4-Stream bus receiving interface, the processor 1101 is further configured to execute:
[0108] The interface conversion module receives a second setting signal identification frame from the second device through the AXI4-Stream bus interface, and determines that the transmission instruction has been processed.
[0109] The embodiment of the present application also provides a computer storage medium, in which computer program instructions are stored. When the instructions are executed on a computer, the computer executes the steps of the above-mentioned method of converting AXI4 bus to Avalon bus.
[0110] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0111] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0112] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0114] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A method for converting an AXI4 bus to an Avalon bus, characterized in that: Applied to a first device, the bus interface of the first device includes an AXI4-Stream bus transmission interface and an AXI4-Stream bus reception interface, and the bus interface of the second device is an Avalon-MM bus interface; The first device includes an interface conversion module, and the method includes: The interface conversion module receives a transmission instruction from the second device through the AXI4-Stream bus sending interface; The interface conversion module identifies the type of the transmission instruction; If the transmission instruction is a write operation instruction, the interface conversion module outputs the write operation instruction and write data according to the Avalon-MM bus interface protocol specification; If the transmission instruction is a read operation instruction, the interface conversion module outputs the read operation instruction and obtains read data according to the Avalon-MM bus interface protocol specification, and outputs the read data through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification.
2. The method according to claim 1, characterized in that: Before the interface conversion module identifies the type of the transmission instruction, the method further includes: The interface conversion module parses the transmission instruction according to the frame format to obtain the operation frame header, operation address, operation length and / or operation data.
3. The method according to claim 2, characterized in that The interface conversion module identifies the type of the transmission instruction, including: The interface conversion module determines whether the type of the transmission instruction is a read operation instruction or a write operation instruction by identifying the operation frame header.
4. The method according to claim 2, characterized in that: The interface conversion module outputs the write operation instruction and write data according to the Avalon-MM bus interface protocol specification, including: After the first write data transmission is completed, the interface conversion module outputs the write operation instruction according to the Avalon-MM bus interface protocol specification, and outputs other write data in sequence; The write operation instruction includes the operation address and the operation length, the operation address is the write operation address, and the operation length is the write operation length.
5. The method according to claim 2, characterized in that: The interface conversion module outputs the read operation instruction and obtains the read data according to the Avalon-MM bus interface protocol specification, and outputs the read data through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification, including: The interface conversion module outputs the read operation instruction according to the Avalon-MM bus interface protocol specification; wherein the read operation instruction includes the operation address and the operation length, the operation address is the read operation address, and the operation length is the read operation length; The interface conversion module obtains the read data according to the operation address and the operation length, and outputs the read data through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus protocol interface specification.
6. The method according to any one of claims 1 to 5, characterized in that: Before the interface conversion module identifies the type of the transmission instruction, the method further includes: The interface conversion module determines that the transmission instruction has been received by parsing the first setting signal identification frame received from the second device.
7. The method according to any one of claims 1 to 5, characterized in that: After outputting the read data through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification, the method further includes: The interface conversion module determines that the transmission instruction has been processed through the second setting signal identification frame received from the second device through the AXI4-Stream bus interface.
8. An electronic device, characterized in that: The bus interface of the electronic device includes an AXI4-Stream bus transmission interface and an AXI4-Stream bus reception interface, the bus interface of the second device is an Avalon-MM bus interface, and the electronic device includes an interface conversion module, and the interface conversion module includes a processor and a transceiver: The transceiver is configured to perform: Receiving a transmission instruction from a second device through the AXI4-Stream bus sending interface; The processor is configured to execute: identifying the type of the transmission instruction; If the transmission instruction is a write operation instruction, outputting the write operation instruction and write data according to the Avalon-MM bus interface protocol specification; If the transmission instruction is a read operation instruction, the read operation instruction is output and read data is obtained according to the Avalon-MM bus interface protocol specification, and the read data is output through the AXI4-Stream bus receiving interface according to the AXI4-Stream bus interface protocol specification.
9. The electronic device according to claim 8, characterized in that: Before identifying the type of the transfer instruction, the processor is further configured to execute: The transmission instruction is parsed according to the frame format to obtain an operation frame header, an operation address, an operation length and / or operation data.
10. The electronic device according to claim 9, characterized in that: The processor is specifically configured to execute: The interface conversion module determines whether the type of the transmission instruction is a read operation instruction or a write operation instruction by identifying the operation frame header.
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CN120973325A