Data acquisition and synchronous storage device and method based on multi-chip FPGA (Field Programmable Gate Array) system
By using unified timestamp signals and temperature calibration coefficients in multi-chip FPGA systems, the data delay difference caused by clock asynchronous between FPGAs is solved, the accuracy and reliability of data synchronous storage are improved, and the multi-chip parallel ADC system is ensured. data consistency in.
Patent Information
- Application Number
- CN202411333050.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-01-03
AI Technical Summary
In multi-chip FPGA systems, data capture delay differences due to asynchronous clocks between FPGAs, affecting the accuracy and reliability of data synchronous storage.
By replacing the preset data bits of the parallel ADC unit with a unified timestamp signal in a multi-chip FPGA system, identifying and adjusting data delay differences, ensuring that the data from the FPGA remains aligned in time, and synchronous calibration using temperature sensors and calibration coefficients .
It reduces the difficulty of synchronous storage of multi-chip FPGA data, improves the accuracy and reliability of synchronous storage, and ensures the data consistency of multi-chip parallel ADCs in multi-chip FPGA systems.
Smart Images
Figure CN119248703A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data processing, and in particular to a data acquisition synchronous storage device and method based on a multi-chip FPGA system. Background Art
[0002] Multiple parallel ADCs collect data at the same time and transmit them to multiple FPGAs in parallel. This implementation can significantly improve the data throughput and processing capabilities of the overall system, especially for applications that require high-speed data interfaces. For example, high-speed parallel ADCs usually have very high output data rates, and a single FPGA may not be able to fully process all data. Multiple FPGAs can effectively process high-speed, large-capacity data streams and support complex real-time data analysis and decision-making. Therefore, the technology of synchronously storing data received by multiple FPGAs from multiple parallel ADCs is widely used in modern engineering and scientific research.
[0003] In a multi-FPGA system, the delay difference between the internal data capture of different FPGAs may cause the capture of parallel ADC data sets to start at different times. The main reason is that there is a difference in the time when different FPGAs receive the external trigger signal to start data capture, or because the clocks received by different FPGAs are not synchronized, resulting in different times when they receive the external trigger signal. Summary of the invention
[0004] The purpose of the embodiment of the present invention is to provide a data acquisition synchronous storage device and method based on a multi-chip FPGA system, by using a unified timestamp signal to replace the preset data bits of each parallel ADC unit, so as to identify the data delay difference information transmitted from each parallel ADC unit to the corresponding slave FPGA, and adjust the data according to the data bit corresponding to the timestamp information, so that the data of each slave FPGA is aligned in time, reducing the difficulty of synchronous storage of data of multiple FPGAs, and improving the accuracy and reliability of synchronous storage of data of multiple parallel ADCs in the multi-chip FPGA system.
[0005] To solve the above technical problems, a first aspect of an embodiment of the present invention provides a data acquisition synchronous storage device based on a multi-chip FPGA system, comprising: a master FPGA, a plurality of slave FPGAs and a plurality of parallel ADC units;
[0006] The master FPGA is connected to the plurality of slave FPGAs respectively, and is also connected to the plurality of parallel ADC units respectively; the data output end of each parallel ADC unit is connected to a corresponding slave FPGA, and the data input end of each parallel ADC unit is connected to an external data input port;
[0007] The master FPGA sends a timestamp signal to the data input terminal of each slave FPGA according to a preset period;
[0008] Each of the parallel ADC units receives input data from the external data input port and performs analog-to-digital conversion processing to obtain first data, and outputs the first data to the corresponding slave FPGA;
[0009] The slave FPGA performs preset digital signal processing on the first data and the timestamp signal respectively received, obtains second data, and sends the second data to the master FPGA, and each of the slave FPGAs is provided with a storage unit for storing the first data and the second data;
[0010] The master FPGA receives the second data sent by each of the slave FPGAs, obtains the delay information of each of the second data based on the timestamp signal, performs synchronization calibration on each of the second data within the preset period, and controls each of the slave FPGAs to adjust its data bit accordingly so that the second data remains synchronously stored.
[0011] Furthermore, the slave FPGA receives the timestamp signal and places the timestamp signal at a preset data position of the first data.
[0012] Furthermore, the slave FPGA receives the timestamp signal and places the timestamp signal at the least significant bit of the first data.
[0013] Further, the parallel ADC unit is connected to the slave FPGA in a one-to-one correspondence;
[0014] or,
[0015] One slave FPGA is correspondingly connected to a plurality of parallel ADC units.
[0016] Further, the master FPGA obtains the delay information of each second data, selects a timestamp in the second data as a reference, respectively calculates the distance values between the timestamp information bits of other second data and the timestamp information bits of the second data as the reference, and sends the distance values to the corresponding slave FPGAs respectively;
[0017] The slave FPGA adjusts the data bits of the second data respectively based on the distance value, so that the timestamp in the adjusted second data is synchronized with the timestamp of the second data serving as a reference.
[0018] Furthermore, the data acquisition synchronous storage device based on the multi-chip FPGA system also includes: a plurality of temperature sensors respectively arranged at the slave FPGAs;
[0019] The temperature sensor acquires the real-time temperature value of the corresponding slave FPGA and sends the real-time temperature value to the master FPGA;
[0020] The master FPGA receives the real-time temperature value of each slave FPGA respectively, and obtains a delay calibration value in combination with the delay initial value in the delay information;
[0021] Based on the delay calibration value, synchronously calibrate the corresponding second data;
[0022] The calculation formula of the delay calibration value is:
[0023] D i_cal =D i_0 ×K i ;
[0024] Among them, D i_cal is the delay calibration value of the i-th slave FPGA, D i_0 is the initial delay value of the i-th slave FPGA, K i is the temperature calibration coefficient of the i-th slave FPGA.
[0025] Further, when the real-time temperature value of a slave FPGA is within a preset reasonable temperature range, the temperature calibration coefficient of the slave FPGA is 1;
[0026] When the real-time temperature value of a slave FPGA is greater than the upper limit of a preset reasonable temperature range, the calculation formula of the temperature calibration coefficient of the slave FPGA is:
[0027]
[0028] Wherein, i is the serial number of the slave FPGA, A is the first proportional coefficient representing the initial intensity of the influence of temperature change on the slave FPGA when the temperature is too high, B is the attenuation coefficient representing the attenuation rate of the intensity as the temperature increases, Δt i_1 The temperature difference between the real-time temperature value of the slave FPGA and the upper limit of a preset reasonable temperature range;
[0029] When the real-time temperature value of a slave FPGA is less than the lower limit of the preset reasonable temperature range, the calculation formula of the temperature calibration coefficient of the slave FPGA is:
[0030]
[0031] Wherein, i is the serial number of the slave FPGA, C is the second proportional coefficient representing the initial intensity of the influence of temperature change on the slave FPGA when the temperature is too low, E is the nonlinear coefficient of the corresponding curve representing the influence of adjusting the temperature when the temperature is too low, Δti_2 It is the temperature difference between the lower limit of the preset reasonable temperature range and the real-time temperature value of the slave FPGA.
[0032] Accordingly, a second aspect of an embodiment of the present invention provides a data acquisition and synchronous storage method based on a multi-chip FPGA system, wherein the data of a plurality of slave FPGAs is synchronously stored by the data acquisition and synchronous storage device based on the multi-chip FPGA system, comprising the following steps:
[0033] The master FPGA sends a timestamp signal to a plurality of slave FPGAs respectively according to a preset period;
[0034] The parallel ADC unit receives the input data and performs analog-to-digital conversion processing to obtain first data, and sends the first data to the corresponding slave FPGA;
[0035] The slave FPGA mixes the received first data and the timestamp signal and performs preset digital signal processing to obtain second data, and sends the second data to the master FPGA;
[0036] The master FPGA receives the second data transmitted by several slave FPGAs respectively, obtains the delay information of each second data based on the timestamp signal, controls each slave FPGA to perform synchronous calibration on the second data within the preset period, and keeps the second data output by each slave FPGA synchronously stored.
[0037] Further, the mixing of the first data and the timestamp signal received from the FPGA comprises:
[0038] The time stamp signal is placed at a preset data position of the first data.
[0039] Further, placing the timestamp signal at a preset data position of the first data includes:
[0040] The time stamp signal is placed at the least significant bit of the first data.
[0041] Furthermore, the acquiring the delay information of each second data based on the timestamp signal and controlling each slave FPGA to synchronously calibrate the second data within the preset period includes:
[0042] The master FPGA obtains the delay information of each second data, selects a timestamp in the second data as a reference, calculates the distance value between the timestamp information bits of other second data and the timestamp information bits of the second data as the reference, and sends the distance value to the corresponding slave FPGA;
[0043] The slave FPGA adjusts the data bits of the second data respectively based on the distance value, so that the timestamp in the second data is synchronized with the timestamp of the second data serving as a reference.
[0044] The above technical solution of the embodiment of the present invention has the following beneficial technical effects:
[0045] By using a unified timestamp signal to replace the preset data bits of each parallel ADC unit, the data delay difference information transmitted from each parallel ADC unit to the corresponding slave FPGA is identified, and the data is adjusted according to the data bits corresponding to the timestamp information, so that the data of each slave FPGA is aligned in time, reducing the difficulty of synchronous storage of data in multiple FPGAs and improving the accuracy and reliability of synchronous storage of data in multiple parallel ADCs in a multi-FPGA system. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 It is a schematic diagram of the principle of a data acquisition and synchronous storage device based on a multi-chip FPGA system provided by an embodiment of the present invention;
[0047] Figure 2 It is a flow chart of a data acquisition and synchronous storage method based on a multi-chip FPGA system provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0048] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.
[0049] Please refer to Figure 1According to a first aspect of an embodiment of the present invention, a data acquisition synchronous storage device based on a multi-chip FPGA system is provided, comprising: a master FPGA, a plurality of slave FPGAs and a plurality of parallel ADC units; the master FPGA is respectively connected to a plurality of slave FPGAs and is respectively connected to a plurality of parallel ADC units; the data output end of each parallel ADC unit is correspondingly connected to a slave FPGA, and the data input end of each parallel ADC unit is connected to an external data input port; the master FPGA sends a timestamp signal to the data input end of each slave FPGA according to a preset period; each parallel ADC unit receives input data from the external data input port and performs analog-to-digital conversion processing to obtain first data, and outputs the first data to the corresponding slave FPGA; the slave FPGA mixes the first data and the timestamp signal received respectively and performs preset digital signal processing to obtain second data, and sends the second data to the master FPGA, and each slave FPGA is provided with a storage unit for storing the first data and the second data; the master FPGA receives the second data sent by each slave FPGA, obtains the delay information of each second data based on the timestamp signal, and performs synchronous calibration on each second data within a preset period, and controls each slave FPGA to adjust its data bit accordingly, so that all the second data are kept synchronously stored.
[0050] The above-mentioned data acquisition synchronous storage device based on a multi-chip FPGA system is mainly used to ensure the time consistency during data acquisition and processing. Among them, the main FPGA sends a timestamp signal to each slave FPGA respectively to ensure the synchronization of data acquisition; each parallel ADC unit obtains the first data after converting the received analog signal into a data signal; the slave FPGA receives the first data and timestamp signal sent by the corresponding parallel ADC unit and mixes them, and sends them to the main FPGA after performing corresponding data processing; at this time, after the main FPGA receives the second data sent by each slave FPGA, it compares the timestamp signal of the preset data bit in the second data, determines the delay information of each slave FPGA according to the comparison result, and sends it to the corresponding slave FPGA; and each slave FPGA adjusts the data bit of its own sent data according to the corresponding delay information, so that the second data of all slave FPGAs can be stored synchronously.
[0051] Specifically, the master FPGA sends a timestamp signal to each slave FPGA, and the timestamp signal is used to replace the D0 bit of the first data sent by the parallel ADC unit. At the same time, after the timestamp signal and the first data of the parallel ADC unit are mixed, they will synchronously experience the same internal delay in the corresponding slave FPGA. Therefore, the D0 bit of the second data output by each slave FPGA, that is, the timestamp bit, can be observed through the second data received by the master FPGA, and any changes in the internal delay of the corresponding slave FPGA can be identified, or the changes in the time when the corresponding slave FPGA starts to capture the readings of the parallel ADC unit can be identified. After the master FPGA obtains the recognition result, it is sent to each slave FPGA respectively, and the control is performed by matching the high or low state changes of the sample relative to the timestamp bit to perform digital correction. Ideally, if there is no delay change in the signal path of the slave FPGA and no other changes, the D0 bit (timestamp bit) of different parallel ADC units should be latched in the slave FPGA at the same time.
[0052] In addition, the above implementation method can also increase the number of parallel ADC units and slave FPGAs according to actual needs, and has high scalability and flexibility.
[0053] Furthermore, a time stamp signal is received from the FPGA, and the time stamp signal is placed at the least significant bit of the first data.
[0054] In one implementation of the embodiment of the present invention, the parallel ADC units are connected to the slave FPGAs in a one-to-one correspondence.
[0055] In another implementation of the embodiment of the present invention, one slave FPGA is connected to a plurality of parallel ADC units accordingly.
[0056] The master FPGA obtains the delay information of each second data, selects the timestamp in a second data as a benchmark, calculates the distance values between the timestamp information bits of other second data and the timestamp information bits of the second data used as the benchmark, sends the corresponding distance values of each slave FPGA to the corresponding slave FPGA, and the slave FPGA adjusts the data bits of the second data so that the timestamp in the second data is synchronized with the timestamp of the second data used as the benchmark.
[0057] The above implementation method can keep the data processed by each slave FPGA accurately synchronized after calibration, ensuring the consistency of data stored in the multi-FPGA system.
[0058] If the same timestamp signal is sent to different slave FPGAs, ideally the slave FPGAs should show the same LSB change in the output bit stream; however, due to factors such as differences in path delays within each slave FPGA, which may cause the phase delay between different signal paths to be greater than one sampling period, thereby showing changes in the LSB bit stream, the moment when the LSB changes from high to low or vice versa may be different between the parallel signal data streams.
[0059] For example, the data sample LSB output by ADC1 goes high at sample number 25, while the sample LSB of ADC2 goes high at sample number 28. In this case, we adjust the 28th sample of ADC2 to the same time as the 25th sample of ADC1 by shifting the samples of ADC2 up 3 positions in the data stream (moving the 25th, 26th and 27th samples of ADC2 to the 22nd, 23rd and 24th positions, and keeping the 28th sample of ADC2 at the 25th sample position of ADC1); in this way, the 28th sample of ADC2 is adjusted to a position similar to the 25th sample of ADC1. After this adjustment, the LSB bits of all samples of ADC1 and ADC2 change from low to high at the same sampling moment.
[0060] In addition, further, the data acquisition synchronous storage device based on the multi-chip FPGA system also includes: a plurality of temperature sensors respectively arranged at the slave FPGAs;
[0061] The temperature sensor acquires the real-time temperature value of the corresponding slave FPGA and sends the real-time temperature value to the master FPGA;
[0062] The master FPGA receives the real-time temperature value of each slave FPGA respectively, and obtains a delay calibration value in combination with the delay initial value in the delay information;
[0063] Based on the delay calibration value, synchronously calibrate the corresponding second data;
[0064] The calculation formula of the delay calibration value is:
[0065] D i_cal =D i_0 ×K i ;
[0066] Among them, D i_cal is the delay calibration value of the i-th slave FPGA, D i_0 is the initial delay value of the i-th slave FPGA, K i is the temperature calibration coefficient of the i-th slave FPGA.
[0067] By introducing the temperature calibration coefficient of each slave FPGA, the influence of temperature can be considered when synchronously calibrating the slave FPGA, thereby ensuring the synchronization of data transmission after calibration.
[0068] By directly correlating temperature changes with delay adjustments, a simple and intuitive method is provided to predict and calibrate the data transmission delay characteristics of the FPGA at different temperatures. The above calibration method is computationally efficient and can adapt to different environmental conditions and FPGA working states by adjusting the temperature calibration coefficient.
[0069] Furthermore, when the real-time temperature value of a slave FPGA is within a preset reasonable temperature range, the temperature calibration coefficient of the slave FPGA is 1.
[0070] In this temperature range, no additional temperature compensation is required for the FPGA, which reduces computational complexity and resource consumption. This improves system stability and reliability, because within the optimal temperature operating range, the performance of the FPGA is usually the most stable, and no adjustment is required to ensure optimal performance.
[0071] When the real-time temperature value of a slave FPGA is greater than the upper limit of a preset reasonable temperature range, the calculation formula of the temperature calibration coefficient of the slave FPGA is:
[0072]
[0073] Wherein, i is the serial number of the slave FPGA, A is the first proportional coefficient representing the initial intensity of the influence of temperature change on the slave FPGA when the temperature is too high, B is the attenuation coefficient representing the attenuation rate of the intensity as the temperature increases, Δt i_1 It is the temperature difference between the real-time temperature value of the slave FPGA and the upper limit value of the preset reasonable temperature range.
[0074] When the real-time temperature value of a slave FPGA is less than the lower limit of the preset reasonable temperature range, the calculation formula of the temperature calibration coefficient of the slave FPGA is:
[0075]
[0076] Wherein, i is the serial number of the slave FPGA, C is the second proportional coefficient representing the initial intensity of the influence of temperature change on the slave FPGA when the temperature is too low, E is the nonlinear coefficient of the corresponding curve representing the influence of adjusting the temperature when the temperature is too low, Δt i_2 It is the temperature difference between the lower limit of the preset reasonable temperature range and the real-time temperature value of the slave FPGA.
[0077] The exponential decay model is used to calculate the temperature calibration coefficient of the slave FPGA when the temperature is higher than the preset interval and lower than the preset interval, respectively. This can accurately reflect the nonlinear effect of temperature changes on FPGA performance. By adjusting the first proportional coefficient and the attenuation coefficient when the temperature is too high, and adjusting the second proportional coefficient and the nonlinear coefficient when the temperature is too low, each slave FPGA unit can be individually temperature compensated, ensuring the stability and reliability of system performance when the preset temperature range is exceeded. The inclusion of real-time temperature values enables the calibration coefficient to dynamically respond to the current temperature state, while the nonlinear characteristics of the model accurately reflect the performance of the device under extreme temperature changes. In addition, the above calculation method is easy to implement in the digital signal processing resources of the FPGA, which is convenient for integration and automation, while maintaining a high degree of flexibility and scalability, providing strong support for system design.
[0078] Accordingly, a second aspect of an embodiment of the present invention provides a data acquisition and synchronous storage method based on a multi-chip FPGA system, wherein the data of a plurality of slave FPGAs is synchronously stored by the data acquisition and synchronous storage device based on the multi-chip FPGA system, comprising the following steps:
[0079] Step S100: The master FPGA sends a timestamp signal to a plurality of slave FPGAs respectively according to a preset period.
[0080] First, the master FPGA sends a timestamp signal to each slave FPGA to ensure synchronization of data acquisition.
[0081] Step S200: The parallel ADC unit receives input data and performs analog-to-digital conversion processing to obtain first data, and sends the first data to the corresponding slave FPGA.
[0082] Each parallel ADC unit obtains first data after converting the received analog signal into a data signal.
[0083] Step S300: The slave FPGA mixes the first data and the timestamp signal received respectively and performs preset digital signal processing to obtain second data, and sends the second data to the master FPGA.
[0084] The slave FPGA receives the first data sent by the corresponding parallel ADC unit and mixes it with the timestamp signal, obtains the second data after performing corresponding preset signal processing, and sends the second data to the master FPGA.
[0085] In step S400, the master FPGA receives the second data transmitted by the plurality of slave FPGAs respectively, obtains the delay information of each second data based on the timestamp signal, controls each slave FPGA to synchronously calibrate the second data within a preset period, and keeps the second data output by each slave FPGA synchronously stored.
[0086] After the master FPGA receives the second data sent by each slave FPGA, it compares the timestamp signal of the preset data bit in the second data, determines the delay information of each slave FPGA based on the comparison result, sends the corresponding delay information of each slave FPGA to the slave FPGA, and the slave FPGA synchronously calibrates the second data within a preset period, so that the second data output by all slave FPGAs can be kept synchronously stored.
[0087] Further, the mixing of the received first data and the timestamp signal from the FPGA in step S200 includes:
[0088] Step S210, placing a timestamp signal at a preset data position of the first data.
[0089] Furthermore, placing the timestamp signal at a preset data position of the first data in step S210 includes:
[0090] Step S211, placing the timestamp signal at the least significant bit of the first data.
[0091] Optionally, the step S400 of acquiring the delay information of each second data based on the timestamp signal and controlling each slave FPGA to synchronously calibrate the second data within a preset period includes:
[0092] In step S410, the master FPGA obtains delay information of each second data, selects a timestamp in a second data as a reference, calculates distance values between timestamp information bits of other second data and the timestamp information bits of the second data used as the reference, and sends them to the corresponding slave FPGA.
[0093] Step S420: The slave FPGA adjusts the data bits of the second data based on the distance value, so that the timestamp in the second data is synchronized with the timestamp of the second data serving as a reference.
[0094] The embodiment of the present invention aims to protect a data acquisition synchronous storage device and method based on a multi-chip FPGA system, wherein the device includes: a master FPGA, several slave FPGAs and several parallel ADC units; the master FPGA is respectively connected to several slave FPGAs and respectively connected to several parallel ADC units; the data output end of each parallel ADC unit is correspondingly connected to a slave FPGA, and the data input end of each parallel ADC unit is connected to an external data input port; the master FPGA sends a timestamp signal to the data input end of each slave FPGA according to a preset period; each parallel ADC unit receives input data from the external data input port and performs analog-to-digital conversion processing to obtain first data, and outputs the first data to the corresponding slave FPGA; the slave FPGA mixes the received first data and the timestamp signal and performs preset digital signal processing to obtain second data, and sends the second data to the master FPGA, and each slave FPGA is provided with a storage unit for storing the first data and the second data; the master FPGA receives the second data sent by each slave FPGA, obtains the delay information of each second data based on the timestamp signal, and performs synchronous calibration on each second data within a preset period, and controls each slave FPGA to adjust its data bit accordingly, so that all second data are kept synchronously stored. The above technical scheme has the following effects:
[0095] By using a unified timestamp signal to replace the preset data bits of each parallel ADC unit, the data delay difference information transmitted from each parallel ADC unit to the corresponding slave FPGA is identified, and the data is adjusted according to the data bits corresponding to the timestamp information, so that the data of each slave FPGA is aligned in time, reducing the difficulty of synchronous storage of data in multiple FPGAs and improving the accuracy and reliability of synchronous storage of data in multiple parallel ADCs in a multi-FPGA system.
[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A data acquisition synchronous storage device based on a multi-chip FPGA system, characterized in that: include: A master FPGA, several slave FPGAs, and several parallel ADC units; The master FPGA is connected to the plurality of slave FPGAs respectively, and is also connected to the plurality of parallel ADC units respectively; the data output end of each parallel ADC unit is connected to a corresponding slave FPGA, and the data input end of each parallel ADC unit is connected to an external data input port; The master FPGA sends a timestamp signal to the data input terminal of each slave FPGA according to a preset period; Each of the parallel ADC units receives input data from the external data input port and performs analog-to-digital conversion processing to obtain first data, and outputs the first data to the corresponding slave FPGA; The slave FPGA performs preset digital signal processing on the first data and the timestamp signal respectively received, obtains second data, and sends the second data to the master FPGA, and each of the slave FPGAs is provided with a storage unit for storing the first data and the second data; The master FPGA receives the second data sent by each of the slave FPGAs, obtains the delay information of each of the second data based on the timestamp signal, performs synchronization calibration on each of the second data within the preset period, and controls each of the slave FPGAs to adjust its data bit accordingly, so that all of the second data are kept synchronously stored.
2. The data acquisition synchronous storage device based on a multi-chip FPGA system according to claim 1, characterized in that: The slave FPGA receives the timestamp signal and places the timestamp signal at a preset data position of the first data.
3. The data acquisition synchronous storage device based on a multi-chip FPGA system according to claim 2, characterized in that: The slave FPGA receives the timestamp signal and places the timestamp signal in the least significant bit of the first data.
4. The data acquisition synchronous storage device based on a multi-chip FPGA system according to claim 1, characterized in that: The parallel ADC units are connected to the slave FPGAs in a one-to-one correspondence; or, One slave FPGA is correspondingly connected to a plurality of parallel ADC units.
5. The data acquisition synchronous storage device based on a multi-chip FPGA system according to claim 1, characterized in that: The master FPGA obtains the delay information of each second data, selects a timestamp in the second data as a reference, calculates the distance values between the timestamp information bits of other second data and the timestamp information bits of the second data as the reference, and sends the distance values to the corresponding slave FPGAs respectively; The slave FPGA adjusts the data bits of the second data respectively based on the distance value, so that the timestamp in the adjusted second data is synchronized with the timestamp of the second data serving as a reference.
6. The data acquisition synchronous storage device based on a multi-chip FPGA system according to any one of claims 1 to 5, characterized in that: Also includes: A plurality of temperature sensors respectively arranged at the slave FPGA; The temperature sensor acquires the real-time temperature value of the corresponding slave FPGA and sends the real-time temperature value to the master FPGA; The master FPGA receives the real-time temperature value of each slave FPGA respectively, and obtains a delay calibration value in combination with the delay initial value in the delay information; Based on the delay calibration value, synchronously calibrate the corresponding second data; The calculation formula of the delay calibration value is: D i_cal =D i_0 ×K i ; Among them, D i_cal is the delay calibration value of the i-th slave FPGA, D i_0 is the initial delay value of the i-th slave FPGA, K i is the temperature calibration coefficient of the i-th slave FPGA.
7. The data acquisition synchronous storage device based on a multi-chip FPGA system according to claim 6, characterized in that: When the real-time temperature value of a slave FPGA is within a preset reasonable temperature range, the temperature calibration coefficient of the slave FPGA is 1; When the real-time temperature value of a slave FPGA is greater than the upper limit of a preset reasonable temperature range, the calculation formula of the temperature calibration coefficient of the slave FPGA is: Wherein, i is the serial number of the slave FPGA, A is the first proportional coefficient representing the initial intensity of the influence of temperature change on the slave FPGA when the temperature is too high, B is the attenuation coefficient representing the attenuation rate of the intensity as the temperature increases, Δt i_1 The temperature difference between the real-time temperature value of the slave FPGA and the upper limit of a preset reasonable temperature range; When the real-time temperature value of a slave FPGA is less than the lower limit of the preset reasonable temperature range, the calculation formula of the temperature calibration coefficient of the slave FPGA is: Wherein, i is the serial number of the slave FPGA, C is the second proportional coefficient representing the initial intensity of the influence of temperature change on the slave FPGA when the temperature is too low, E is the nonlinear coefficient of the corresponding curve representing the influence of adjusting the temperature when the temperature is too low, Δt i_2 It is the temperature difference between the lower limit of the preset reasonable temperature range and the real-time temperature value of the slave FPGA.
8. A data acquisition and synchronous storage method based on a multi-chip FPGA system, characterized in that: The method of synchronously storing data of a plurality of slave FPGAs by using the data acquisition synchronous storage device based on a multi-chip FPGA system as described in any one of claims 1 to 7 comprises the following steps: The master FPGA sends a timestamp signal to a plurality of slave FPGAs respectively according to a preset period; The parallel ADC unit receives the input data and performs analog-to-digital conversion processing to obtain first data, and sends the first data to the corresponding slave FPGA; The slave FPGA mixes the received first data and the timestamp signal and performs preset digital signal processing to obtain second data, and sends the second data to the master FPGA; The master FPGA receives the second data transmitted by several slave FPGAs respectively, obtains the delay information of each second data based on the timestamp signal, controls each slave FPGA to perform synchronous calibration on the second data within the preset period, and keeps the second data output by each slave FPGA synchronously stored.
9. The method for synchronously storing data in a multi-chip FPGA system according to claim 8, characterized in that: The first data and the timestamp signal received from the FPGA are mixed, including: The time stamp signal is placed at the least significant bit of the first data.
10. The method for synchronously storing data in a multi-chip FPGA system according to claim 8 or 9, characterized in that: The acquiring the delay information of each second data based on the timestamp signal, and controlling each slave FPGA to synchronously calibrate the second data within the preset period, comprises: The master FPGA obtains the delay information of each second data, selects a timestamp in the second data as a reference, calculates the distance value between the timestamp information bits of other second data and the timestamp information bits of the second data as the reference, and sends the distance value to the corresponding slave FPGA; The slave FPGA adjusts the data bits of the second data respectively based on the distance value, so that the timestamp in the second data is synchronized with the timestamp of the second data serving as a reference.