Power semiconductor device fatigue life modeling method based on variable working condition power circulation
Through the method based on variable working conditions, the time and cost of fatigue life modeling of power semiconductor devices is shortened, and the problems of long experimental cycles and high economic costs in the prior art are solved, and efficient fatigue life modeling is achieved.
Patent Information
- Application Number
- CN202411246508.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2025-01-03
AI Technical Summary
The existing fatigue life evaluation methods of power semiconductor devices have problems such as long experimental cycles, large number of experimental groups, and large sample demands, which leads to high life modeling time and economic costs, which limits their application.
Using fatigue life modeling method based on variable working conditions power cycle, the power cycle assessment control strategy is determined by selecting device types and specifications, the working condition sequence is prepared, the initial and variable working conditions power cycle assessment is carried out, and the electric heating parameter degradation data is obtained. , process and fit to build a fatigue life model.
The number of test sets and time required for fatigue life modeling is significantly reduced, and efficient and low-cost life modeling is achieved, which shortens the experimental cycle and reduces economic costs.
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Figure CN119249700A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a fatigue life modeling method for power semiconductor devices based on variable operating condition power cycles. Background Art
[0002] When power semiconductor devices are in long-term operation, they are affected by their own operating losses and changes in the external environment, which will generate a continuously fluctuating thermal stress field inside the device, induce fatigue cracking of the packaging material or heterogeneous interface, affect the device's electrical and thermal conductivity and stress bearing capacity, and degrade the device's external port's electrical and thermal characteristics. The internal multi-physical field environment is further deteriorated, and eventually when the internal physical field strength exceeds the device's stress bearing boundary, the device will fail permanently. It can be seen that power semiconductor device packaging fatigue under the action of disturbed thermal stress is an important factor affecting the device's ultimate service life.
[0003] At present, stress analytical models are commonly used for fatigue life assessment of power semiconductor devices, such as the Manson-Coffin model, Lesit model, Norris-Landzberg model, and CIPS 08 model. The analytical model usually first conducts theoretical analysis of the factors affecting the device reliability model based on failure physics, and constructs a mathematical model of the device fatigue life and its bearing stress; then, a large number of accelerated stress experiments are performed to verify the model and obtain the model acceleration factor through data fitting.
[0004] The essence of the analytical model is the mathematical statistical relationship between the device operating conditions / condition parameters and fatigue life data. It has a simple principle, is easy to use, and has good evaluation accuracy within the accelerated stress range. However, the current analytical model has disadvantages such as long experimental cycle, large number of experimental groups, and large number of assessment samples, which greatly increases the time and economic cost of life modeling, and seriously limits its application in fatigue life assessment of power semiconductor devices.
[0005] Taking the typical Norris-Landzberg model as an example, the model includes the junction temperature fluctuation ΔT j , Maximum junction temperature T jmax and the power cycle conduction period or frequency t on If each factor is considered at 3 to 4 levels, the number of accelerated stress test groups required to fully construct the fatigue life is greater than 20. Usually, a single group of accelerated stress tests lasts for several days to weeks, and the number of experimental samples required for a single group of tests is usually 3 to 4. Therefore, the experimental cycle for constructing a complete fatigue life model of power semiconductor devices is as long as half a year or even more than one year, and the number of samples required is as high as hundreds, which brings huge time and economic costs to the application of fatigue life models. Summary of the invention
[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned technology and provide a method for fatigue life modeling of power semiconductor devices based on variable operating condition power cycles, thereby achieving the goal of efficient and low-cost life modeling of power semiconductor devices and greatly reducing the time and economic cost of fatigue life modeling of power semiconductor devices.
[0007] To achieve the above object, the fatigue life modeling method of power semiconductor devices based on variable operating condition power cycle designed by the present invention comprises the following steps:
[0008] A) Select the type and specification of the power semiconductor device to be tested, and determine the power cycle test control strategy;
[0009] B) calibrating the electric and thermal state parameters and initial electric and thermal parameters of the power semiconductor device under different working conditions;
[0010] C) Prepare a power cycle condition sequence and set several condition groups, including initial condition and variable condition;
[0011] D) Complete the initial working condition and the variable working condition sequence power cycle assessment in sequence to obtain the electrothermal parameter degradation data of the power semiconductor device under different working condition groups;
[0012] E) processing the degradation data of the electric-thermal parameters of the power semiconductor device under different working condition groups to obtain the complete degradation data of the electric-thermal parameters of the power semiconductor device under different working condition groups;
[0013] F) According to the fatigue failure criterion, the fatigue life is determined in combination with the complete data of the electrothermal parameter degradation of the power semiconductor device, and the fatigue life model is constructed.
[0014] Preferably, in step A), the power cycle assessment control strategy selects one of constant junction temperature fluctuation, constant current or constant power mode.
[0015] Preferably, in step A), types of power semiconductor devices include IGBT, MOSFET, diode and thyristor.
[0016] Preferably, in step B), the electrothermal state parameters include junction temperature fluctuation and maximum junction temperature, and the initial electrothermal parameters include junction-to-case thermal resistance and on-state voltage drop, which provide a basis for the compilation of subsequent power cycle assessment condition sequences and fatigue damage calculations.
[0017] Preferably, in the step C), when compiling the power cycle operating condition sequence, more than two operating condition groups are included, and the difference in junction temperature fluctuation of the devices in the highest operating condition group and the lowest operating condition group is greater than 50K, wherein the operating condition group with the largest junction temperature fluctuation is the initial operating condition, and the order of the remaining operating condition groups is random, which is a variable operating condition. The number of cycles of the initial operating condition is determined according to the degradation of the electrothermal parameters of the power semiconductor device, so that the electrothermal parameters increase by more than 3%, and the variable operating condition is cycled more than 5000 times, so that the electrothermal parameters of the power semiconductor devices in the operating condition group are significantly degraded.
[0018] Preferably, in the step C), when compiling the power cycle condition sequence, the coverage, quantity, initial condition and execution cycle of the condition group are included to ensure a wide coverage of the conditions obtained during the assessment process, and efficiently obtain accurate electrothermal parameter degradation data of power semiconductor devices during the power cycle assessment, thereby laying a solid foundation for subsequent degradation data fitting and fatigue life technology.
[0019] Preferably, in the step D), when the power cycle assessment of the initial working condition is performed, the power cycle test platform is first used to carry out a cycle assessment on the power semiconductor device under the initial working condition, and the trend of the electric and thermal parameters of the power semiconductor device with the cycle number is monitored. When the degradation of the electric and thermal parameters of the power semiconductor device is greater than 3%, the cycle assessment is stopped, and the fatigue initiation life N under the initial working condition is recorded. i As well as the degradation data of the rising stage of electrothermal parameters, the fatigue of power semiconductor devices has stage characteristics, namely fatigue initiation (steady-state platform stage of electrothermal characteristic parameters) and fatigue extension stage (continuous rising stage of electrothermal characteristics). Therefore, the working condition group with the largest junction temperature fluctuation in the working condition sequence is used to first accelerate the assessment of power semiconductor devices, so that they can quickly pass through the fatigue initiation stage and enter the fatigue extension stage, which is conducive to shortening the experiment time.
[0020] Preferably, in the step D), when performing power cycle assessment under variable operating conditions, a power cycle test platform is used to carry out cycle assessment on power semiconductor devices in sequence under variable operating conditions, and the degradation data of electric and thermal parameters under different operating condition groups are recorded. When the operating condition sequence is completed or the power semiconductor device fails, the test is terminated.
[0021] Preferably, in step E), the obtained electrothermal parameter degradation data of the power semiconductor device under different working conditions are grouped according to the working conditions, and then respectively classified according to
[0022]
[0023] Normalization is performed to obtain fatigue damage degradation curves of power semiconductor devices under different working conditions, where D pis fatigue extension damage, U0 is the initial electrothermal parameters of the power semiconductor device, including junction-to-case thermal resistance and on-state voltage drop, N is the number of power cycles, U(N) is the real-time electrothermal parameters of the power cycle device, and μ is the failure threshold coefficient;
[0024] A nonlinear function is used to mathematically fit the fatigue damage degradation curve of the power semiconductor device under different working conditions to obtain the specific values of the fitting parameters. Finally, the fitting parameters are substituted into the fitting function to obtain the complete fatigue damage degradation curve of the power semiconductor device under different working conditions.
[0025] Preferably, in step F), the fatigue extension damage D is set p = 1 is the failure threshold, and the fatigue extension life N is determined according to the complete fatigue damage degradation curve of the power semiconductor device under different working conditions and the set failure threshold p , according to the fatigue initiation life N of power semiconductor devices under initial working conditions i And the corresponding N p , according to N i =M·N p Calculate the proportionality factor M, based on the proportionality factor M and the fatigue extension life N of the power semiconductor device under different working conditions p , calculate the fatigue life N of power semiconductor devices under different working conditions f =(1+M)·N p .
[0026] Compared with the prior art, the present invention has the following advantages:
[0027] 1. A power semiconductor device fatigue life modeling method based on variable operating condition power cycle is adopted. Through a small number of power cycle assessment tests, the degradation data of the power semiconductor electric and thermal characteristics under different operating conditions is obtained in combination with the data inversion method, and then the fatigue life of the power semiconductor device under different operating conditions is obtained;
[0028] 2. The number of power cycle test groups required for fatigue life modeling of power semiconductor devices has been significantly reduced, achieving the goal of efficient and low-cost life modeling of power semiconductor devices, and greatly reducing the time and economic cost of fatigue life modeling of power semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A schematic diagram of a process for modeling a power semiconductor device fatigue life based on variable operating condition power cycles;
[0030] Figure 2 Schematic diagram of the power cycle operating sequence of the IGBT module in the embodiment;
[0031] Figure 3This is a schematic diagram of the initial calibration of the electric heating parameters for the power cycle assessment of the IGBT module in the embodiment;
[0032] Figure 4 It is a thermal resistance parameter degradation curve diagram of the IGBT module variable working condition power cycle assessment process in the embodiment;
[0033] Figure 5 It is a thermal resistance parameter degradation curve diagram of the IGBT module under different working condition groups in the embodiment. DETAILED DESCRIPTION
[0034] The present invention is further described in detail below in conjunction with specific embodiments.
[0035] like Figure 1 As shown, a method for modeling fatigue life of power semiconductor devices based on variable operating condition power cycles includes the following steps:
[0036] A) Select the type and specification of the power semiconductor device to be assessed. The types of power semiconductor devices include IGBT, MOSFET, diode and thyristor. The main packaging forms include discrete, modular and press-fit. Determine the power cycle assessment control strategy. The power cycle assessment control strategy selects one of the constant junction temperature fluctuation, constant current or constant power mode. Under the constant junction temperature fluctuation control strategy, the junction temperature fluctuation, on-time and off-time of the IGBT in the heating and cooling cycle during the entire power cycle process remain constant. Under the constant current control strategy, the heating current, on-time and off-time of the IGBT during the entire power cycle process remain constant. Under the constant power control strategy, the heating power, on-time and off-time of the IGBT during the entire power cycle process remain constant;
[0037] B) Calibrate the electric thermal state parameters and initial electric thermal parameters of the power semiconductor device under different working conditions. The electric thermal state parameters include junction temperature fluctuation and maximum junction temperature. The initial electric thermal parameters include junction-to-case thermal resistance and on-state voltage drop. Specifically, a power cycle assessment platform is used to assess the power semiconductor device under a specific cycle control strategy. Under each working condition, the power semiconductor device enters a thermal cycle steady state, and the electric thermal parameters of the power semiconductor device under the working condition are recorded to complete the calibration of the initial electric thermal parameters of the power semiconductor device;
[0038] C) Prepare a power cycle condition sequence, set several condition groups, including initial condition and variable condition. When preparing a power cycle condition sequence, include more than 2 condition groups, the difference in junction temperature fluctuation of the highest condition group and the lowest condition group is greater than 50K, among which the condition group with the largest junction temperature fluctuation is the initial condition, and the order of the remaining condition groups is random, which is a variable condition. The number of cycles of the initial condition is determined according to the degradation of the electric and thermal parameters of the power semiconductor device, so that the electric and thermal parameters increase by more than 3%. The variable condition is cycled for more than 5000 times, so that the electric and thermal parameters of the power semiconductor devices in the condition group are significantly degraded. When preparing a power cycle condition sequence, include the coverage, quantity, initial condition and condition group execution cycle of the condition group, as shown in Table 1:
[0039] Table 1 Working condition sequence compilation table
[0040]
[0041] The working condition with the largest thermal stress is selected as the initial working condition among the working conditions that have completed the initial electrothermal parameter calibration. The working conditions that have completed the initial electrothermal parameter calibration are selected and arranged in a random order. Each working condition section in the sequence lasts for more than 5000 cycles. The specific setting can be based on the working condition stress level to ensure that the electrothermal characteristics of the power semiconductor device in each working condition section are significantly degraded (2% to 5%).
[0042] D) Complete the initial working condition and the variable working condition sequence power cycle assessment in sequence, and obtain the electrothermal parameter degradation data of the power semiconductor device under different working condition groups. According to fatigue theory, the fatigue process of the power semiconductor device is divided into two successive stages: initiation and expansion. In the initiation stage, the electrothermal characteristics of the power semiconductor device do not degrade and basically remain constant. In the expansion stage, the electrothermal characteristics of the power semiconductor device continue to degrade and continue to rise. The present invention is based on the fatigue damage equivalence principle under different working conditions, and mainly inverts the degradation law of the complete electrothermal characteristics of the power semiconductor device under constant working conditions based on the degradation curve of the electrothermal characteristics of the power semiconductor device in the fatigue expansion stage under variable working conditions, so as to determine the fatigue life of the power semiconductor device under different working conditions. Therefore, the focus of the power cycle assessment is to obtain the segmented degradation data of the electrothermal characteristics of the power semiconductor device under different working conditions. In order to shorten the cumulative assessment time, the assessment condition with the largest stress level should be used to accelerate the assessment of the power semiconductor device to the fatigue expansion stage as soon as possible;
[0043] Carry out power cycle assessment of power semiconductor devices in sequence according to the compiled working condition sequence, monitor and record the curve of the change of the electrothermal characteristic parameters of power semiconductor devices with the cycle number during the cycle assessment, and obtain the segmented degradation data of the electrothermal parameters under different working conditions:
[0044] When conducting the power cycle assessment of the initial working condition, the power cycle test platform is first used to carry out a cycle assessment on the power semiconductor device under the initial working condition, and the trend of the electric and thermal parameters of the power semiconductor device with the cycle number is monitored. When the degradation of the electric and thermal parameters of the power semiconductor device is greater than 3%, the cycle assessment is stopped and the fatigue initiation life N under the initial working condition is recorded. i And the degradation data of the rising section of the electrothermal parameters;
[0045] When conducting power cycle assessment under variable working conditions, the power cycle test platform is used to carry out cycle assessment on power semiconductor devices in sequence under variable working conditions, and the degradation data of electric and thermal parameters under different working condition groups are recorded. When the working condition sequence is completed or the power semiconductor device fails, the test is terminated, and the segmented degradation data of electric and thermal parameters under different working conditions are obtained;
[0046] According to the fitting accuracy requirements of the fatigue life model of power semiconductor devices, a new power semiconductor device experimental group can be added. According to the same power cycle control strategy, steps B) to D) are repeated. Compared with the previous group of tests, the test condition sequence can be shifted to a certain extent.
[0047] E) Combined with Table 2:
[0048] Table 2 Grouping table of power semiconductor device electrothermal parameter degradation data
[0049]
[0050] The degradation data of the electric thermal parameters of the power semiconductor devices under different working condition groups are processed to obtain the complete degradation data of the electric thermal parameters of the power semiconductor devices under different working condition groups. Specifically, the obtained degradation data of the electric thermal parameters of the power semiconductor devices under different working conditions are grouped according to the working conditions, and then respectively
[0051]
[0052] Normalization is performed to obtain fatigue damage degradation curves of power semiconductor devices under different working conditions, where D p is fatigue extension damage, U0 is the initial electrothermal parameters of the power semiconductor device, including junction-to-case thermal resistance and on-state voltage drop, N is the number of power cycles, U(N) is the real-time electrothermal parameters of the power cycle device, and μ is the failure threshold coefficient;
[0053] A nonlinear function is used to mathematically fit the fatigue damage degradation curve of the power semiconductor device under different working conditions to obtain the specific values of the fitting parameters. Finally, the fitting parameters are substituted into the fitting function to obtain the complete fatigue damage degradation curve of the power semiconductor device under different working conditions.
[0054] F) According to the fatigue failure criterion, the fatigue life is determined in combination with the complete data of the degradation of the electrical and thermal parameters of the power semiconductor device, and the fatigue life model is constructed. Specifically, the fatigue extension damage D is set p = 1 is the failure threshold, and then the fatigue extension life N is determined according to the complete fatigue damage degradation curve of the power semiconductor device under different working conditions and the set failure threshold p , according to the fatigue initiation life N of power semiconductor devices under initial working conditions i And the corresponding N p , according to N i =M·N p Calculate the proportionality factor M, based on the proportionality factor M and the fatigue extension life N of the power semiconductor device under different working conditions p , calculate the fatigue life N of power semiconductor devices under different working conditions f =(1+M)·N p , as shown in Table 3:
[0055] Table 3 Power semiconductor device fatigue life calculation table
[0056]
[0057] Taking the 1700V-3600A modular IGBT constant current control strategy power cycle assessment as an example, five different working conditions are selected, namely 2700A-10s-20s, 2400A-10s-20s, 2100A-10s-20s, 1800A-10s-20s and 2700A-5s-15s, among which 2700A-10s-20s is set as the initial working condition, the cycle is set to 30000 times, and the remaining working conditions are executed 5000 to 20000 times respectively, and are arranged in 10 working condition sections in random order, such as Figure 2 shown.
[0058] According to the set working condition sequence, 50 power cycles are performed for each group of working conditions. The IGBT heating current, junction temperature fluctuation, maximum junction temperature, on-state voltage drop and other electrothermal parameters are recorded during the cycle to complete the initial electrothermal parameter calibration of the IGBT power cycle process. Figure 3 As shown, the junction temperature fluctuation amplitudes under the five operating conditions are in the range of 53℃~107℃.
[0059] According to the set working condition sequence, the power cycle equipment is used to carry out power cycle assessment on the IGBT module in sequence, and the degradation data of the IGBT module's electric and thermal parameters with the cycle number during the assessment process are recorded, such as Figure 4 As shown in the figure, the electrothermal parameters of the IGBT module remain basically constant at the initial stage. When the power cycle of the initial working condition reaches about 20,000 times, the electrothermal characteristics of the IGBT begin to degrade. The degradation starting point is recorded as the fatigue initiation life N under the initial working condition. iAt the same time, save the IGBT electrothermal parameter degradation data after 20,000 times, continue to carry out power cycle assessment according to the operating condition sequence, until all operating condition sections are completed, and record the IGBT electrothermal parameter degradation data.
[0060] The 10 degradation data segments are grouped according to the working condition groups and normalized into fatigue damage degradation curve D p -N, a third-order polynomial is used to fit the fatigue damage degradation curves of IGBTs under different working conditions to obtain the polynomial fitting parameters, and then the fitted parameters are substituted into the third-order polynomial to obtain the complete fatigue damage degradation curves of IGBTs under different working conditions, such as Figure 5 shown.
[0061] According to the complete IGBT fatigue damage degradation curve under different working conditions, the fatigue extension damage D p When it reaches 1, the IGBT module is judged to be fatigue failure, and the cycle number is recorded as the fatigue extension life N of the IGBT module under this working condition group. p ; Then, according to the IGBT fatigue initiation life N under the initial working condition i The fatigue extension life N corresponding to the initial working condition p , calculate the ratio M, and finally, according to the ratio M and the fatigue diffusion life of the IGBT under different working conditions, calculate the fatigue life N of the IGBT module under the corresponding working condition f .
[0062] The above assessment and analysis steps were repeated for the other two 1700V-3600A IGBT modules in constant current mode, and the fatigue life of the IGBT modules under different working conditions was obtained as shown in Table 4:
[0063] Table 4 IGBT module fatigue life data under different working conditions
[0064]
[0065]
Claims
1. A method for modeling fatigue life of power semiconductor devices based on variable operating condition power cycles, characterized in that: The steps include: A) Select the type and specification of the power semiconductor device to be tested, and determine the power cycle test control strategy; B) calibrating the electric and thermal state parameters and initial electric and thermal parameters of the power semiconductor device under different working conditions; C) Prepare a power cycle condition sequence and set several condition groups, including initial condition and variable condition; D) Complete the initial working condition and the variable working condition sequence power cycle assessment in sequence to obtain the electrothermal parameter degradation data of the power semiconductor device under different working condition groups; E) processing the degradation data of the electric thermal parameters of the power semiconductor device under different working condition groups to obtain the complete degradation data of the electric thermal parameters of the power semiconductor device under different working condition groups; F) According to the fatigue failure criterion, the fatigue life is determined in combination with the complete data of the electrothermal parameter degradation of the power semiconductor device, and the fatigue life model is constructed.
2. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 1 is characterized in that: In the step A), the power cycle assessment control strategy selects one of the constant junction temperature fluctuation, constant current or constant power modes.
3. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 1 is characterized in that: In the step A), the types of power semiconductor devices include IGBT, MOSFET, diode and thyristor.
4. The method for modeling fatigue life of power semiconductor devices based on variable operating condition power cycles according to claim 1, characterized in that: In the step B), the electrothermal state parameters include junction temperature fluctuation and maximum junction temperature, and the initial electrothermal parameters include junction-to-case thermal resistance and conduction voltage drop.
5. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 4 is characterized in that: In the step C), when compiling the power cycle operating condition sequence, it includes more than two operating condition groups, the difference in junction temperature fluctuation of the device in the highest operating condition group and the lowest operating condition group is greater than 50K, among which the operating condition group with the largest junction temperature fluctuation is the initial operating condition, and the order of the remaining operating condition groups is random, which is a variable operating condition. The number of cycles of the initial operating condition is determined according to the degradation of the electrothermal parameters of the power semiconductor device, so that the electrothermal parameters increase by more than 3%, and the variable operating condition is cycled more than 5000 times, so that the electrothermal parameters of the power semiconductor devices in the operating condition group are significantly degraded.
6. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 1, characterized in that: In the step C), when compiling the power cycle operating condition sequence, it includes the coverage, quantity, initial operating condition and execution period of the operating condition group.
7. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 1, characterized in that: In the step D), when the power cycle assessment of the initial working condition is performed, the power cycle test platform is first used to carry out a cycle assessment on the power semiconductor device under the initial working condition, and the trend of the electric and thermal parameters of the power semiconductor device with the cycle number is monitored. When the degradation of the electric and thermal parameters of the power semiconductor device is greater than 3%, the cycle assessment is stopped, and the fatigue initiation life N under the initial working condition is recorded. i And the degradation data of the electrothermal parameters in the rising section.
8. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 1, characterized in that: In the step D), when performing power cycle assessment under variable operating conditions, a power cycle test platform is used to carry out cycle assessment on power semiconductor devices in sequence under variable operating conditions, and the degradation data of electric and thermal parameters under different operating condition groups are recorded. When the operating condition sequence is completed or the power semiconductor device fails, the test is terminated.
9. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 1, characterized in that: In the step E), the obtained electrothermal parameter degradation data of the power semiconductor device under different working conditions are grouped according to the working conditions, and then respectively Normalization is performed to obtain fatigue damage degradation curves of power semiconductor devices under different working conditions, where D p is fatigue extension damage, U0 is the initial electrothermal parameters of the power semiconductor device, including junction-to-case thermal resistance and on-state voltage drop, N is the number of power cycles, U(N) is the real-time electrothermal parameters of the power cycle device, and μ is the failure threshold coefficient; A nonlinear function is used to mathematically fit the fatigue damage degradation curve of the power semiconductor device under different working conditions to obtain the specific values of the fitting parameters. Finally, the fitting parameters are substituted into the fitting function to obtain the complete fatigue damage degradation curve of the power semiconductor device under different working conditions.
10. The power semiconductor device fatigue life modeling method based on variable operating condition power cycle according to claim 1, characterized in that: In the step F), the fatigue extension damage D is set p = 1 is the failure threshold, and then the fatigue extension life N is determined according to the complete fatigue damage degradation curve of the power semiconductor device under different working conditions and the set failure threshold p , according to the fatigue initiation life N of power semiconductor devices under initial working conditions i And the corresponding N p , according to N i =M·N p Calculate the proportionality factor M, based on the proportionality factor M and the fatigue extension life N of the power semiconductor device under different working conditions p , calculate the fatigue life N of power semiconductor devices under different working conditions f =(1+M)·N p .