Method and system for fast and accurate co-simulation of coprocessor

Abstract

The invention discloses a rapid and accurate co-simulation method and system for a coprocessor, and the system comprises an FPGA end which is used for placing target CPU hardware implementation and comprises an FPGA development board which is provided with target CPU hardware design, a CPU control module, an instruction execution track collection module, a coprocessor request processing module and a communication interface module; and the host end is in communication connection with the FPGA development board through a high-speed interface of the FPGA development board and is used for placing an FPGA monitoring program, a target algorithm program and an instruction execution track acquisition program. Through the design of the FPGA end and the host end, the performance of the target algorithm under different coprocessor implementation schemes can be rapidly obtained, so that the advantages and disadvantages of different design schemes can be evaluated in the early stage of design, and rapid iteration is carried out.

Description

Technical Field

[0001] The present invention relates to the field of CPU design and coprocessor algorithms, and in particular to a method and system for fast and accurate co-simulation of a coprocessor, which is mainly used to support CPU design, coprocessor algorithms or implementation evaluation of special algorithm instructions. Background Art

[0002] The CPU coprocessor is a hardware algorithm implementation circuit developed on the coprocessor extension interface provided by the CPU design, which is closely integrated with the CPU design to complete computing / processing tasks. The main purpose of designing a coprocessor is to enhance the computing / processing capabilities of the CPU chip in certain specific fields or special scenarios.

[0003] In the coprocessor design process, the algorithm needs to be coordinated with the CPU design to execute the program together. The process is generally as follows: The CPU sends instructions and operands to the coprocessor, waits for the coprocessor to complete the corresponding instruction execution, and returns the result and completion status to the CPU. For complex coprocessor algorithms, in the early stages of design, the algorithm may be a program described in a high-level language such as C or Python, without a mature circuit structure, but it is necessary to timely evaluate the execution effect of the CPU program plus the coprocessor. Therefore, the coprocessor algorithm design platform needs to be able to support rapid iteration of algorithm design and be able to quickly execute and obtain effect feedback, so as to facilitate the exploration of algorithm design space.

[0004] The existing methods of coprocessor algorithms and CPU design for collaborative operation can be divided into two categories: 1. Integrate the coprocessor algorithm into software tools such as CPU instruction simulator and micro-architecture simulator, and obtain execution data for analysis by running software simulation programs; 2. Combine with the real CPU design (usually Verilog / SytemVerilog), connect the coprocessor design with the interface provided by the CPU design, and run the program in the CPU design verification environment to obtain data for analysis.

[0005] For the first method, since software tools such as CPU instruction simulators and micro-architecture simulators cannot accurately match the actual CPU design, it is difficult to obtain the accurate number of CPU instruction running beats after adding the coprocessor / accelerator, which affects the accuracy of the analysis and evaluation. If you want to obtain an instruction simulator / micro-architecture simulator that matches the actual CPU design, it will take a lot of manpower and time to calibrate, and the input-output ratio is low. At the same time, as more design details are added to the instruction simulator / micro-architecture simulator, its running speed will decrease and slow down until it loses its meaning.

[0006] For the second method, if the CPU test stimulus / program is run in the EDA soft simulation environment, the speed is very slow and it is difficult to meet the needs of rapid modification and rapid execution evaluation of the coprocessor algorithm; if the entire design is placed in the FPGA prototype to increase the running speed, firstly, there is no detailed circuit design in the early stage of the coprocessor algorithm design, and it is difficult to generate the FPGA circuit; secondly, even if the algorithm structure is described using HDL (Verilog, etc.), the time cycle for iterative modification and generation of the FPGA circuit is also very long, and it is difficult to meet the needs of rapid modification and rapid execution evaluation of the coprocessor algorithm.

[0007] The main reason for the above problems is that the existing methods and ideas are difficult to solve the contradiction between the coprocessor algorithm design and the CPU collaborative execution in the simulation execution speed and accuracy.

[0008] The existing approach is to either reduce the accuracy of the CPU model in exchange for execution speed, or to require a coprocessor to complete the detailed design and add it to the FPGA for operation, thereby extending the design iteration cycle in exchange for high-precision operation.

[0009] Therefore, it is necessary to propose a method that supports the rapid iterative design of the coprocessor algorithm and the rapid coordinated execution with the CPU design while ensuring the operating precision / accuracy and operating speed. Summary of the invention

[0010] Purpose of the invention: To provide a method and system for fast and accurate co-simulation of a coprocessor to solve the above-mentioned problems existing in the prior art.

[0011] Technical solution: A method for fast and accurate co-simulation of a coprocessor, comprising: Step 1: Draw out the instruction execution trace output interface, performance statistics output interface and coprocessor execution interface for the target CPU, and design the CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module; Step 2: Deploy the target CPU hardware design, CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module to the FPGA development board after integration; Step 3: The host runs the FPGA monitoring program, loads the main test program into the target CPU through the CPU control module, and starts execution; Step 4: When the target CPU executes the test program, the instruction execution trajectory acquisition module tracks the CPU operation status in real time and saves the instruction execution trajectory; Step 5, the coprocessor request processing module records the target algorithm instructions received during the target CPU executing the test program, and initiates a simulation request to the host side through the communication interface module; Step 6: After receiving the coprocessor call request, the host uses the pre-deployed target algorithm program to perform simulation execution, and returns the running result and the number of beats to be run to the coprocessor request processing module through the high-speed interface; Step 7: After receiving the simulated execution result of the target algorithm instruction, the coprocessor request processing module feeds back the result to the target CPU according to the number of beats to be run. The target CPU writes the result back and continues execution from the breakpoint. Step 8: After the FPGA test program is executed, the host reads the instruction execution trace information and performance statistics through the communication interface.

[0012] Designers can continue to optimize and iterate the target algorithm based on program execution and performance simulation; By designing the FPGA end, the execution of the real CPU can be quickly and accurately simulated. At the same time, the CPU instruction execution trajectory, performance parameters and coprocessor execution instructions are brought out in the form of an interface. When there is an instruction using the coprocessor, a simulation request is sent to the host end and paused at the appropriate time. After the pause, the target CPU clock cycle will no longer increase, and the PC will no longer change. After receiving the host simulation operation result, it will continue to execute from the breakpoint. The host-side FPGA monitoring program is designed to schedule the main test program to the target CPU on the FPGA side for execution, monitor and capture the coprocessor call requests issued by the target CPU, simulate the execution using the target algorithm program and send the calculation results back to the FPGA side, and collect the instruction execution trace and operation performance parameters of the target CPU. The performance of the target algorithm under different coprocessor implementation schemes can then be quickly obtained, so that the pros and cons of different design schemes can be evaluated in the early stages of the design and rapid iteration can be performed.

[0013] In a further embodiment, the CPU control module is responsible for loading instructions to the target CPU, providing clock / reset signals, controlling the startup and debugging of the target CPU, and providing a read and write interface for the target CPU internal control status register.

[0014] In a further embodiment, the instruction execution trace collection module is used to track the operation of the CPU in real time and collect the instruction execution trace.

[0015] In a further embodiment, the coprocessor request processing module is used to intercept the coprocessor algorithm instructions emitted by the target CPU during the execution of the test program, and send a target algorithm simulation request to the host side, while receiving the running results of the host side target algorithm program and feeding back the running results to the target CPU.

[0016] In a further embodiment, the communication interface module is used to convert the simulation request issued by the coprocessor request processing module into an interface signal according to the communication protocol and send it to the host side, while parsing the control status register read and write request and algorithm simulation results sent by the host side, and sending the control status register read and write request and algorithm simulation results to the CPU control module, instruction execution trajectory acquisition module and coprocessor request processing module for processing respectively.

[0017] In a further embodiment, step 4 further comprises: When the target CPU encounters the target algorithm instruction, the relevant information of the target algorithm instruction is extracted and sent to the coprocessor request processing module. At the same time, the operation of the target CPU is suspended at an appropriate time according to the number of cycles to be executed by the target algorithm instruction. The host side can check the operating status of the CPU at any time through the CPU control module.

[0018] A system for fast and accurate co-simulation of a coprocessor, comprising: The FPGA side is used to place the target CPU hardware implementation, including an FPGA development board with a target CPU hardware design, a CPU control module, an instruction execution trace acquisition module, a coprocessor request processing module, and a communication interface module; The host side is connected to the FPGA development board through the FPGA development board high-speed interface and is used to place the FPGA monitoring program, target algorithm program and instruction execution trajectory acquisition program.

[0019] Beneficial effects: The present invention discloses a method and system for fast and accurate co-simulation of a coprocessor. The method designs an FPGA end to quickly and accurately simulate the execution of a real CPU, and at the same time, the CPU instruction execution trajectory, performance parameters, and coprocessor execution instructions are introduced in the form of an interface. When an instruction uses the coprocessor, a simulation request is sent to the host end and paused at an appropriate time. After the pause, the target CPU clock cycle no longer increases, and the PC no longer changes. After receiving the host simulation operation result, the execution continues from the breakpoint. The host-side FPGA monitoring program is designed to schedule the main test program to the target CPU on the FPGA side for execution, monitor and capture the coprocessor call requests issued by the target CPU, simulate the execution using the target algorithm program and send the calculation results back to the FPGA side, and collect the instruction execution trace and operation performance parameters of the target CPU. The performance of the target algorithm under different coprocessor implementation schemes can then be quickly obtained, so that the pros and cons of different design schemes can be evaluated in the early stages of the design and rapid iteration can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the system structure of the present invention.

[0021] Figure 2 It is a schematic diagram of the prior art structure of the present invention. DETAILED DESCRIPTION

[0022] The present application relates to a method and system for fast and accurate co-simulation of a coprocessor. The existing methods for co-operation of coprocessor algorithms and CPU designs are mainly divided into two categories: 1. Integrate the coprocessor algorithm into software tools such as CPU instruction simulator and micro-architecture simulator, and obtain execution data for analysis by running software simulation programs; 2. Combine with the real CPU design (usually Verilog / SytemVerilog), connect the coprocessor design with the interface provided by the CPU design, and run the program in the CPU design verification environment to obtain data for analysis.

[0023] For the first method, since software tools such as CPU instruction simulators and micro-architecture simulators cannot accurately match the actual CPU design, it is difficult to obtain the accurate number of CPU instruction running beats after adding the coprocessor / accelerator, which affects the accuracy of the analysis and evaluation. If you want to obtain an instruction simulator / micro-architecture simulator that matches the actual CPU design, it will take a lot of manpower and time to calibrate, and the input-output ratio is low. At the same time, as more design details are added to the instruction simulator / micro-architecture simulator, its running speed will decrease and slow down until it loses its meaning.

[0024] For the second method, if the CPU test stimulus / program is run in the EDA soft simulation environment, the speed is very slow and it is difficult to meet the needs of rapid modification and rapid execution evaluation of the coprocessor algorithm; if the entire design is placed in the FPGA prototype to increase the running speed, firstly, there is no detailed circuit design in the early stage of the coprocessor algorithm design, and it is difficult to generate the FPGA circuit; secondly, even if the algorithm structure is described using HDL (Verilog, etc.), the time cycle for iterative modification and generation of the FPGA circuit is also very long, and it is difficult to meet the needs of rapid modification and rapid execution evaluation of the coprocessor algorithm.

[0025] The main reason for the above problems is that the existing methods and ideas are difficult to solve the contradiction between the coprocessor algorithm design and the CPU collaborative execution in the simulation execution speed and accuracy.

[0026] The existing approach is to either reduce the accuracy of the CPU model in exchange for execution speed, or to require a coprocessor to complete the detailed design and add it to the FPGA for operation, thereby extending the design iteration cycle in exchange for high-precision operation.

[0027] Therefore, it is necessary to propose a method to support the rapid iteration design of the coprocessor algorithm and the rapid coordinated execution with the CPU design under the premise of ensuring the operation precision / accuracy and operation speed; The present invention simulates the execution of a real CPU quickly and accurately by designing an FPGA end, and at the same time, draws out the CPU instruction execution trajectory, performance parameters, and coprocessor execution instructions in the form of an interface. When there is an instruction using the coprocessor, a simulation request is sent to the host end and paused at an appropriate time. After the pause, the target CPU clock cycle no longer increases, and the PC no longer changes. After receiving the host simulation operation result, it continues to execute from the breakpoint. The host-side FPGA monitoring program is designed to schedule the main test program to the target CPU on the FPGA side for execution, monitor and capture the coprocessor call requests issued by the target CPU, simulate the execution using the target algorithm program and send the calculation results back to the FPGA side, and collect the instruction execution trace and operation performance parameters of the target CPU. The performance of the target algorithm under different coprocessor implementation schemes can then be quickly obtained, so that the pros and cons of different design schemes can be evaluated in the early stages of the design and rapid iteration can be performed.

[0028] The following is a detailed explanation through specific implementation methods.

[0029] A method for fast and accurate co-simulation of a coprocessor, comprising: Step 1: Draw out the instruction execution trace output interface, performance statistics output interface and coprocessor execution interface for the target CPU, and design the CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module; Step 2: Deploy the target CPU hardware design, CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module to the FPGA development board after integration; Step 3: The host runs the FPGA monitoring program, loads the main test program into the target CPU through the CPU control module, and starts execution; Step 4: When the target CPU executes the test program, the instruction execution trajectory acquisition module tracks the CPU operation status in real time and saves the instruction execution trajectory; Step 5, the coprocessor request processing module records the target algorithm instructions received during the target CPU executing the test program, and initiates a simulation request to the host side through the communication interface module; Step 6: After receiving the coprocessor call request, the host uses the pre-deployed target algorithm program to perform simulation execution, and returns the running result and the number of beats to be run to the coprocessor request processing module through the high-speed interface; Step 7: After receiving the simulated execution result of the target algorithm instruction, the coprocessor request processing module feeds back the result to the target CPU according to the number of beats to be run. The target CPU writes the result back and continues execution from the breakpoint. Step 8: After the FPGA test program is executed, the host reads the instruction execution trace information and performance statistics through the communication interface.

[0030] Designers can continue to optimize and iterate the target algorithm based on program execution and performance simulation; By designing the FPGA end, the execution of the real CPU can be quickly and accurately simulated. At the same time, the CPU instruction execution trajectory, performance parameters and coprocessor execution instructions are brought out in the form of an interface. When there is an instruction using the coprocessor, a simulation request is sent to the host end and paused at the appropriate time. After the pause, the target CPU clock cycle will no longer increase, and the PC will no longer change. After receiving the host simulation operation result, it will continue to execute from the breakpoint. The host-side FPGA monitoring program is designed to schedule the main test program to the target CPU on the FPGA side for execution, monitor and capture the coprocessor call requests issued by the target CPU, simulate the execution using the target algorithm program and send the calculation results back to the FPGA side, and collect the instruction execution trace and operation performance parameters of the target CPU. The performance of the target algorithm under different coprocessor implementation schemes can then be quickly obtained, so that the pros and cons of different design schemes can be evaluated in the early stages of the design and rapid iteration can be performed.

[0031] The CPU control module is responsible for loading instructions to the target CPU, providing clock / reset signals, controlling the startup and debugging of the target CPU, and providing a read and write interface for the internal control status register of the target CPU.

[0032] The instruction execution trace collection module is used to track the operation of the CPU in real time and collect the instruction execution trace.

[0033] The coprocessor request processing module is used to intercept the coprocessor algorithm instructions emitted by the target CPU during the execution of the test program, and send a target algorithm simulation request to the host side, while receiving the running results of the host side target algorithm program and feeding back the running results to the target CPU.

[0034] The communication interface module is used to convert the simulation request issued by the coprocessor request processing module into an interface signal according to the communication protocol and send it to the host end, while parsing the control status register read and write request and algorithm simulation result sent by the host end, and sending the control status register read and write request and algorithm simulation result to the CPU control module, the instruction execution trajectory acquisition module and the coprocessor request processing module for processing respectively.

[0035] The step 4 also includes: When the target CPU encounters the target algorithm instruction, the relevant information of the target algorithm instruction is extracted and sent to the coprocessor request processing module. At the same time, the operation of the target CPU is suspended at an appropriate time according to the number of cycles to be executed by the target algorithm instruction. The host side can check the operating status of the CPU at any time through the CPU control module.

[0036] A system for fast and accurate co-simulation of a coprocessor, comprising: The FPGA side is used to place the target CPU hardware implementation, including an FPGA development board with a target CPU hardware design, a CPU control module, an instruction execution trace acquisition module, a coprocessor request processing module, and a communication interface module; The host side is connected to the FPGA development board through the FPGA development board high-speed interface, and is used to place the FPGA monitoring program (cooperative control software), target algorithm program and instruction execution trajectory acquisition program.

[0037] Working principle description: Derive the instruction execution trace output interface, performance statistics output interface and coprocessor execution interface for the target CPU, and design the CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module; The target CPU hardware design, CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module are integrated and deployed to the FPGA development board; The host runs the FPGA monitoring program, loads the main test program into the target CPU through the CPU control module, and starts execution; When the target CPU executes the test program, the instruction execution trajectory acquisition module tracks the CPU operation in real time and saves the execution trajectory; When the target CPU encounters the target algorithm instruction, it sends the target algorithm instruction to the coprocessor request processing module, and at the same time, according to the number of cycles to be executed by the target algorithm instruction, the operation of the target CPU is suspended at an appropriate time. The host side checks the CPU operation status at any time through the CPU control module; The coprocessor request processing module records the received target algorithm instructions and initiates a simulation request to the host through the communication interface module; After receiving the coprocessor call request, the host uses the pre-deployed target algorithm program to perform simulation execution, and returns the running results and the number of beats to be run to the coprocessor request processing module through the high-speed interface; After receiving the simulated execution result of the target algorithm instruction, the coprocessor request processing module feeds back the result to the target CPU according to the number of beats to be run. The target CPU writes the result back and continues execution from the breakpoint. When the test program on the FPGA side is executed, the host side reads the instruction execution trace information and performance statistics through the communication interface.

[0038] The preferred specific embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above specific embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical scheme of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.

Claims

1. A method for fast and accurate co-simulation of a coprocessor, characterized in that: include: Step 1: Draw out the instruction execution trace output interface, performance statistics output interface and coprocessor execution interface for the target CPU, and design the CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module; Step 2: Deploy the target CPU hardware design, CPU control module, instruction execution trace acquisition module, coprocessor request processing module and communication interface module to the FPGA development board after integration; Step 3: The host runs the FPGA monitoring program, loads the main test program into the target CPU through the CPU control module, and starts execution; Step 4: When the target CPU executes the test program, the instruction execution trajectory acquisition module tracks the CPU operation status in real time and saves the instruction execution trajectory; Step 5, the coprocessor request processing module records the target algorithm instructions received during the target CPU executing the test program, and initiates a simulation request to the host side through the communication interface module; Step 6: After receiving the coprocessor call request, the host uses the pre-deployed target algorithm program to perform simulation execution, and returns the running result and the number of beats to be run to the coprocessor request processing module through the high-speed interface; Step 7: After receiving the simulated execution result of the target algorithm instruction, the coprocessor request processing module feeds back the result to the target CPU according to the number of beats to be run. The target CPU writes the result back and continues execution from the breakpoint. Step 8: After the FPGA test program is executed, the host reads the instruction execution trace information and performance statistics through the communication interface.

2. The method for fast and accurate co-simulation of a coprocessor according to claim 1, characterized in that: The CPU control module is responsible for loading instructions to the target CPU, providing clock / reset signals, controlling the startup and debugging of the target CPU, and providing a read and write interface for the internal control status register of the target CPU.

3. The method for fast and accurate co-simulation of a coprocessor according to claim 1, characterized in that: The instruction execution trace collection module is used to track the operation status of the target CPU in real time and collect the instruction execution trace.

4. The method for fast and accurate co-simulation of a coprocessor according to claim 1, characterized in that: The coprocessor request processing module is used to intercept the target algorithm instruction and send the target algorithm simulation request to the host side, and at the same time receive the running result of the target algorithm program on the host side and feed back the running result to the target CPU.

5. The method for fast and accurate co-simulation of a coprocessor according to claim 1, characterized in that: The communication interface module is used to convert the simulation request issued by the coprocessor request processing module into an interface signal according to the communication protocol and send it to the host end, while parsing the control read and write requests and algorithm simulation results sent by the host end, and sending the control read and write requests and algorithm simulation results to the CPU control module, the instruction execution trajectory acquisition module and the coprocessor request processing module for processing respectively.

6. The method for fast and accurate co-simulation of a coprocessor according to claim 1, characterized in that: The step 4 also includes: When the target CPU encounters the target algorithm instruction, the relevant information of the target algorithm instruction is extracted and sent to the coprocessor request processing module. At the same time, the operation of the target CPU is suspended at an appropriate time according to the number of cycles to be executed by the target algorithm instruction. The host side can check the CPU operation status at any time through the CPU control module.

7. A system for fast and accurate co-simulation of coprocessors, used to implement the method according to any one of claims 1 to 6, characterized in that: include: The FPGA side is used to place the target CPU hardware implementation, including an FPGA development board with a target CPU hardware design, a CPU control module, an instruction execution trace acquisition module, a coprocessor request processing module, and a communication interface module; The host side is connected to the FPGA development board through the FPGA development board high-speed interface and is used to place the FPGA monitoring program, target algorithm program and instruction execution trajectory acquisition program.

Images