Model training method and device

Abstract

The invention discloses a model training method and device, and belongs to the technical field of artificial intelligence, and the method comprises the steps: obtaining a first calculation graph corresponding to a first model, the first calculation graph being used for describing a calculation sequence among N first calculation nodes of the first model, and N being a positive integer; determining M first computing nodes from the N first computing nodes, wherein M is a positive integer smaller than or equal to N; and calculating M gradients in one-to-one correspondence with the M first computing nodes, and respectively updating the weight parameters of the corresponding first computing nodes based on each gradient to obtain a trained first model.

Description

Technical Field

[0001] The present application belongs to the field of artificial intelligence technology, and specifically relates to a model training method and device thereof. Background Art

[0002] With the development of generative artificial intelligence (AI) technology, AI models are becoming more powerful. For example, AI models can generate ID photos similar to users. Currently, if you want to get an AI model that can generate content related to users, you need to train the AI ​​model with data related to users. For example, an AI model that can generate user portraits needs to be trained with images containing users, and an AI model that can simulate the user's language style to communicate with other users needs to be trained with the user's historical chat records.

[0003] However, since the AI ​​model training involves a large number of parameters and the training of the AI ​​model requires multiple rounds of iterations, the AI ​​model training takes up a large amount of memory and takes a long time to train, which leads to poor efficiency of model training. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a model training method and a device thereof, which can reduce the memory usage and training time during AI model training and improve the efficiency of AI model training.

[0005] In a first aspect, an embodiment of the present application provides a model training method, the method comprising: obtaining a first computational graph corresponding to a first model, the first computational graph being used to describe the computational order between N first computational nodes of the first model, where N is a positive integer; determining M first computational nodes from the N first computational nodes, where M is a positive integer less than or equal to N; calculating M gradients corresponding one-to-one to the M first computational nodes, and updating the weight parameters of the corresponding first computational nodes based on each gradient, to obtain a trained first model.

[0006] In the second aspect, an embodiment of the present application provides a model training device, which includes: a processing module; a processing module for obtaining a first calculation graph corresponding to a first model, the first calculation graph is used to describe the calculation order between N first calculation nodes of the first model, N is a positive integer; the processing module is also used to determine M first calculation nodes from the N first calculation nodes, M is a positive integer less than or equal to N; the processing module is also used to calculate M gradients corresponding to the M first calculation nodes one by one, and update the weight parameters of the corresponding first calculation nodes based on each gradient to obtain the trained first model.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.

[0010] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the first aspect.

[0011] In an embodiment of the present application, the electronic device may first obtain a first calculation graph corresponding to the first model, the first calculation graph is used to describe the calculation order between the N first calculation nodes of the first model, N is a positive integer; then determine M first calculation nodes from the N first calculation nodes, M is a positive integer less than or equal to N; calculate M gradients corresponding to the M first calculation nodes one by one, and update the weight parameters of the corresponding first calculation nodes based on each gradient, to obtain the trained first model. Through this scheme, since the electronic device can determine some first calculation nodes (i.e., M first calculation nodes) from the N first calculation nodes of the first model when obtaining the first calculation graph used to describe the calculation order between the N first calculation nodes of the first model, and only calculate the gradients of the part of the first calculation nodes without calculating the gradients of the N first calculation nodes, the electronic device can complete the training of the first model by only updating the weight parameters of some first calculation nodes based on the M gradients without updating the weight parameters of the N first calculation nodes. Therefore, by reducing the number of nodes that need to perform gradient calculations, the resource usage during model training is reduced, thereby reducing the memory usage and training time during model training and improving the efficiency of model training. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is one of the flow charts of a model training method provided in an embodiment of the present application;

[0013] Figure 2 This is the second flowchart of a model training method provided in an embodiment of the present application;

[0014] Figure 3 is a structural schematic diagram of a second calculation graph provided in an embodiment of the present application;

[0015] Figure 4 is a structural schematic diagram of a first calculation graph provided in an embodiment of the present application;

[0016] Figure 5 It is a schematic diagram of the structure of a calculation graph after adding a label calculation node and a loss function calculation node provided in an embodiment of the present application;

[0017] Figure 6 is a schematic diagram of the structure of a third calculation graph provided in an embodiment of the present application;

[0018] Figure 7 This is one of the schematic diagrams of a memory allocation strategy determination process provided in an embodiment of the present application;

[0019] Figure 8 This is the second schematic diagram of a process for determining a memory allocation strategy provided in an embodiment of the present application;

[0020] Fig. 9 This is a third schematic diagram of a process for determining a memory allocation strategy provided in an embodiment of the present application;

[0021] Fig.10 This is a fourth schematic diagram of a process for determining a memory allocation strategy provided in an embodiment of the present application;

[0022] Fig.11 This is a fifth schematic diagram of a process for determining a memory allocation strategy provided in an embodiment of the present application;

[0023] Fig.12 This is the sixth schematic diagram of a memory allocation strategy determination process provided by an embodiment of the present application;

[0024] Fig.13 It is a structural schematic diagram of a model training device provided in an embodiment of the present application;

[0025] Fig.14 This is one of the hardware structure diagrams of an electronic device provided in an embodiment of the present application;

[0026] Fig.15 This is the second schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0028] The terms "first", "second", etc. in the specification of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0029] The terms "at least one (item)", "at least one of" and the like in the specification of the present application refer to any one, any two or a combination of more than two of the objects contained therein. For example, at least one (item) of a, b, and c can be represented by: "a", "b", "c", "a and b", "a and c", "b and c" and "a, b and c", where a, b, and c can be single or multiple. Similarly, "at least two (items)" refers to two or more, and its meaning is similar to that of "at least one (item)". The logo in the present application is text, symbol, image, etc. used to indicate information, and logos or other containers can be used as carriers for displaying information, including but not limited to text logos, image logos, symbol logos, etc.

[0030] The model training method and device provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0031] The model training method and device provided in the embodiments of the present application can be applied to scenarios of training and updating model parameters, especially scenarios of training and updating model parameters in electronic devices.

[0032] At present, when training a model, the number of parameters reaches billions, and the data of intermediate nodes needs to be recorded. It also takes multiple rounds of iterations for the model to converge. Therefore, the model training takes up a lot of memory and takes a long time. Therefore, the model training is usually carried out in the cloud server.

[0033] If you need to obtain a personalized model for a user, you need to upload the user-related data to the cloud server to train the AI ​​model. However, the process of uploading user data may cause user data leakage or even abuse.

[0034] In the model training method and device provided by the embodiment of the present application, since only the gradients of some nodes in the first model can be calculated and updated, the training of the first model can be completed. Therefore, by reducing the number of nodes that need to be gradient calculated, the resource usage during model training is reduced, thereby reducing the memory usage and training time during model training, and improving the efficiency of model training. In addition, since there is no need to upload user-related data to the cloud server, the security of user data is guaranteed.

[0035] The execution subject of the model training method provided in the embodiment of the present application may be a model training device. Exemplarily, the model training device may be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The model training method provided in the embodiment of the present application will be exemplarily described below using an electronic device as an example.

[0036] The present application embodiment provides a model training method. Figure 1 A flow chart of a model training method provided in an embodiment of the present application is shown, and the method can be applied to electronic devices. Figure 1 As shown, the model training method provided in the embodiment of the present application may include the following steps 101 to 103.

[0037] Step 101: The electronic device obtains a first calculation graph corresponding to a first model.

[0038] The first calculation graph may be used to describe the calculation order between N first calculation nodes of the first model, where N is a positive integer.

[0039] In some embodiments of the present application, the first model may be a pre-trained model, or the first model may be a model whose parameters are to be updated.

[0040] It should be noted that the pre-trained model is a model obtained by large-scale pre-training of general domain data. In practical applications, the pre-trained model can be fine-tuned by specific tasks or fields to obtain the required model. Usually, the fine-tuning of the pre-trained model is achieved by updating all the parameters of the pre-trained model.

[0041] It is understandable that during the application of the model, the model's parameters can be continuously updated to make the model's prediction results more accurate.

[0042] In some embodiments of the present application, a computational graph is a directed acyclic graph, wherein a computational node in the computational graph may represent an operation or a mathematical function, and an edge represents a tensor or data, which provides a visual framework for forward propagation and backward propagation in deep learning.

[0043] It is understandable that the input of a node can be data or parameters, and the output of a node can represent a calculation result. In other words, a calculation graph can represent the entire calculation process from the input data of the model through a series of layers (such as convolutional layers, activation function layers, fully connected layers, etc.) to the output result.

[0044] In some embodiments of the present application, the electronic device can analyze the calculation process of the first model through graph capture to dynamically construct a first calculation graph corresponding to the first model. It can be understood that after capturing the calculation graph, the electronic device can obtain a global perspective of the entire calculation process of the first model, so that the first model can be better optimized.

[0045] In some embodiments of the present application, the above-mentioned first computation graph may include N first computation nodes of the first model and their computation order.

[0046] In some embodiments of the present application, the above-mentioned first computing node may be a computing node in a computing graph corresponding to the first model.

[0047] In some embodiments of the present application, Figure 1 ,like Figure 2 As shown, the above step 101 may include the following steps 101a to 101c.

[0048] Step 101a: The electronic device obtains a second calculation graph corresponding to the first model.

[0049] The second computation graph may be used to describe the computation order between T first computation nodes included in the first model, where T is a positive integer less than N.

[0050] In some embodiments of the present application, the T first computing nodes mentioned above may be computing nodes participating in calculation during the first model reasoning.

[0051] Step 101b: The electronic device adds a LoRA computing node to the T first computing nodes according to the second computing node in the T first computing nodes to obtain N first computing nodes.

[0052] Among them, the input of the above-mentioned low-rank adaptation (Low-Rank Adaptation, LoRA) computing node is connected to the output of the previous computing node of the second computing node, and the output of the LoRA computing node is connected to the output of the next computing node of the second computing node.

[0053] In some embodiments of the present application, the second computing node may be a computing node corresponding to the algorithm to be improved among the T first computing nodes. In other words, the electronic device may determine the second computing node corresponding to the task to be improved according to the algorithm effect requirements.

[0054] It is understandable that the first model may include computing nodes corresponding to multiple tasks. For specific tasks to be improved, LoRA computing nodes may be added to fine-tune the first model so that the first model may contain certain specific data, thereby providing personalized services to users.

[0055] It should be noted that, in the process of gradient descent of model loss, the weight update matrix is ​​basically a low-rank matrix. Therefore, the weight change of each computing node in the calculation graph corresponding to the model can be matrix decomposed, and the weight change matrix can be decomposed into two small matrices multiplied. In this way, during the model training process, each weight update will be updated to these two small matrices (LoRA computing nodes), so that on the basis of not changing the original model matrix, the output of the original model plus the output result of the multiplication of these two small matrices is equivalent to fine-tuning the original model.

[0056] In some embodiments of the present application, the above-mentioned N first computing nodes may include T first computing nodes and an additional LoRA computing node.

[0057] It should be noted that LoRA is a low-rank adaptive algorithm, which is a technology widely used to train large language models. The core idea of ​​LoRA is to simulate the change of parameters through low-rank decomposition, so as to achieve indirect training of the model with a very small number of parameters. In other words, LoRA technology allows the indirect training of some dense layer changes in the neural network by optimizing the rank decomposition matrix of the dense layer, while keeping the pre-trained weights frozen.

[0058] Step 101c: The electronic device generates a first computing graph according to the N first computing nodes.

[0059] In some embodiments of the present application, after the electronic device adds a LoRA computing node to T first computing nodes, N first computing nodes can be obtained, thereby obtaining a first computing graph.

[0060] For example, Figure 3As shown, the electronic device may first obtain a second computation graph Graph0 corresponding to the first model, wherein the second computation graph Graph0 includes an input computation node 200, a convolution computation node 201, a data shaping computation node 202, a fully connected computation node 203, an activation function computation node 204, a convolution computation node 205, and an output computation node 206. Then, as Figure 4 As shown, the electronic device can add LoRA computing nodes to the second computing graph graph0 according to the algorithm effect requirements to obtain a first computing graph graph1 containing LoRA nodes. The first computing graph graph1 includes input computing nodes 200, convolution computing nodes 201, data shaping computing nodes 202, fully connected computing nodes 203, activation function computing nodes 204, convolution computing nodes 205, output computing nodes 206, and LoRA down computing nodes 207, LoRA up computing nodes 208, and superposition computing nodes 209.

[0061] In actual implementation, corresponding tools can also be used on the cloud server to add LoRA nodes to specific layers of the first model according to the algorithm effect requirements, and then use the conversion tool to convert the first calculation graph containing the LoRA calculation node.

[0062] In this way, by adding LoRA computing nodes to the calculation graph corresponding to the first model, when fine-tuning the first model, only the computing nodes corresponding to a specific task can be updated, thereby reducing the amount of calculation for model training.

[0063] Step 102: The electronic device determines M first computing nodes from N first computing nodes.

[0064] Wherein, M is a positive integer less than or equal to N.

[0065] In some embodiments of the present application, the M first computing nodes may be computing nodes whose parameters need to be updated.

[0066] In some embodiments of the present application, the electronic device can set nodes that need to calculate gradients according to the training requirements of the LoRA computing nodes.

[0067] In some embodiments of the present application, the above step 102 may include the following step 102a.

[0068] Step 102a: The electronic device determines computing nodes from the LoRA computing node to the third computing node among the N first computing nodes as M first computing nodes.

[0069] The third computing node may be an output node among the N first computing nodes.

[0070] In some embodiments of the present application, LoRA computing nodes are added to the second computing graph. After obtaining the first computing graph, the electronic device can number the computing nodes in the first computing graph according to topological sorting, and the forward reasoning process of the first model can be performed according to the numbering of the computing nodes.

[0071] For example, Figure 5 As shown, in the first calculation graph graph1, the input calculation node 200 is numbered 0, the convolution calculation node 201 is numbered 1, the data shaping calculation node 202 is numbered 2, the fully connected calculation node 203 is numbered 3, the LoRA reduction calculation node 207 is numbered 4, the LoRA increase calculation node 208 is numbered 5, the superposition calculation node 209 is numbered 6, the activation function calculation node 204 is numbered 7, the convolution calculation node 205 is numbered 8, the output calculation node 206 is numbered 9, the label calculation node 210 is numbered 10, and the loss function calculation node 211 is numbered 11.

[0072] In some embodiments of the present application, after numbering the computing nodes in the first computing graph according to topological sorting, the electronic device can determine M first computing nodes according to the numbering, with the LoRA computing node as the starting point and the output computing node as the end point.

[0073] It should be noted that, since the output computing node only outputs the computing result but does not perform data processing, the output computing node may not be determined as the first computing node that needs to update parameters.

[0074] For example, Figure 4 As shown, the electronic device can take the LoRA down calculation node 207 as the starting point and the output calculation node 206 as the end point, and traverse the first calculation graph in a breadth-first manner, and set all the visited calculation nodes as nodes that need to calculate the gradient. In other words, the five calculation nodes numbered 4, 5, 6, 7, and 8 are determined as nodes that need to calculate the gradient, that is, M=5.

[0075] In this way, other computing nodes that need to calculate gradients can be determined based on the LoRA computing nodes without updating the parameters of all computing nodes of the entire first model, thereby reducing the number of nodes that need to perform gradient calculations and reducing resource usage during model training.

[0076] Step 103: The electronic device calculates M gradients corresponding to the M first computing nodes one by one, and updates the weight parameters of the corresponding first computing nodes based on each gradient to obtain a trained first model.

[0077] In some embodiments of the present application, for a computing node whose parameters need to be updated, the electronic device may calculate its gradient and thereby update the parameters of the computing node through gradient descent.

[0078] It should be noted that gradient descent is an optimization algorithm used to find parameter values ​​that minimize the loss function. In the context of machine learning and deep learning, the loss function measures the difference between the model's predicted value and the true value, and gradient descent is used to update the model's parameters (such as weights and biases) to minimize this difference. Gradient descent works by calculating the gradient of the loss function with respect to the model parameters, and then updating the parameters in the opposite direction of the gradient. In this way, each iteration will reduce the value of the loss function, gradually approaching the minimum value of the loss function.

[0079] In some embodiments of the present application, the electronic device may further add a label calculation node and a loss function calculation node to the first calculation graph to obtain the loss value during the training of the first model.

[0080] In some embodiments of the present application, the above-mentioned label calculation node can be used to receive the real value.

[0081] In some embodiments of the present application, the above-mentioned loss function calculation node can be used to calculate the difference between the predicted value and the true value output by the first model, and the output of the loss function calculation node can be the gradient of the loss function.

[0082] For example, Figure 5 As shown, Figure 5 The calculation graph after adding the label calculation node 210 and the loss function calculation node 211 is shown.

[0083] In some embodiments of the present application, the above loss function calculation node can select mean squared error (MSE), Softmax function and cross entropy loss function (SoftMax With Cross Entropy) or a custom loss function according to algorithm requirements. This embodiment of the present application is not specifically limited.

[0084] The model training method provided by the embodiment of the present application is that, since the electronic device can determine some first computing nodes (i.e., M first computing nodes) from the N first computing nodes of the first model when obtaining the first computing graph for describing the computing order between the N first computing nodes of the first model, and only calculate the gradients of the some first computing nodes without calculating the gradients of the N first computing nodes, the electronic device can complete the training of the first model by updating only the weight parameters of some first computing nodes based on the M gradients without updating the weight parameters of the N first computing nodes. Therefore, by reducing the number of nodes that need to perform gradient calculations, the resource usage during model training is reduced, thereby reducing the memory usage and training time during model training, and improving the efficiency of model training.

[0085] In some embodiments of the present application, before the above step 103, the model training method provided in the embodiments of the present application may also include the following steps 104 and 105.

[0086] Step 104: The electronic device adds M gradient calculation nodes to the first calculation graph based on the M first calculation nodes to generate a third calculation graph.

[0087] Step 105: The electronic device calculates M gradients in sequence according to the third calculation graph.

[0088] The third computation graph may be used to describe the computation order between M first computation nodes, each of the M first computation nodes corresponding to a gradient computation node.

[0089] In some embodiments of the present application, the above-mentioned gradient calculation node can be used to calculate the gradient of the first calculation node corresponding to it.

[0090] In some embodiments of the present application, the input of the above-mentioned gradient calculation node may be the input of the corresponding first calculation node.

[0091] In some embodiments of the present application, after determining the M first computing nodes whose parameters need to be updated, the electronic device can add a gradient computing node for each of the M first computing nodes, and during the training process of the first model, the gradient of the first computing node can be reduced through back propagation.

[0092] It can be understood that back propagation starts at the loss function calculation node and propagates backward along the computational graph. During the back propagation process, the gradient of each calculation node is the partial derivative of the loss function with respect to the input of the node, which can indicate how to adjust the input of the node to minimize the loss function.

[0093] It is understandable that after calculating the gradient of each computing node, the electronic device can use gradient descent to update the parameters of the model. By repeatedly performing forward propagation, calculating losses, back propagation, and updating parameters, the first model gradually learns to extract useful features from the input data and generate accurate predictions.

[0094] In some embodiments of the present application, in the process of adding M gradient calculation nodes in the first calculation graph based on the M first calculation nodes, the electronic device can add gradient calculation nodes to the M first calculation nodes in the first calculation graph from back to front based on the first calculation graph.

[0095] For example, Figure 6 As shown, the electronic device can start adding gradient calculation nodes from Loss_layer_11. For each node that needs to calculate the gradient, namely LoRA_down_4, LoRA_up_5, Add_6, Softmax_7, Conv_8, the electronic device can set the gradient calculation nodes Grad_Mul_12, Grad_Softmax_13, Grad_Add_14, Grad_LoRA_up_15, Grad_LoRA_down_16 according to the type of the node, as well as the input and node parameters of these gradient calculation nodes to obtain the third calculation graph.

[0096] It is understandable that the electronic device may also number the increased gradient calculation nodes based on topological sorting.

[0097] In this way, the electronic device can calculate the gradient of the corresponding first computing node through the gradient computing node, thereby realizing the training of the first model through gradient descent.

[0098] In some embodiments of the present application, the model training method provided in the embodiments of the present application may also include the following steps 106 and 107.

[0099] Step 106: The electronic device determines a first order based on the N+M first memory sizes.

[0100] Among them, each first memory size corresponds to a computing node in the third computing graph, and the first memory size is the memory size required for calculating the corresponding computing node.

[0101] In some embodiments of the present application, the above-mentioned first order is used to indicate the order of allocating memory blocks to the N+M computing nodes in the third computing graph.

[0102] In some embodiments of the present application, the electronic device can calculate the memory size node_memory required for each node according to the data shape of the node input to obtain a memory set memory_set. It can be understood that the memory set memory_set includes the memory size required for each computing node in the third computing graph.

[0103] It is understandable that the electronic device can calculate the memory sizes of N+M computing nodes in the third computing graph to obtain N+M first memory sizes.

[0104] In some embodiments of the present application, after obtaining the memory set memory_set, the electronic device may sort the memory sizes node_memory in the memory set memory_set from large to small, and when allocating memory blocks, allocate the memory blocks in order from large to small.

[0105] It is understandable that allocating memory blocks in order from large to small allows the released memory blocks to be reused on other computing nodes when they are released, without the situation where the memory block size is insufficient.

[0106] Step 107: The electronic device allocates memory blocks to the N+M computing nodes based on the first order and in accordance with the memory allocation strategy.

[0107] In some embodiments of the present application, the above-mentioned memory allocation strategy may include at least one of the following: when allocating memory blocks to the fourth computing node, if there are free memory blocks in the memory block set, then allocate free memory blocks to the fourth computing node; when allocating memory blocks to the fourth computing node, if there are no free memory blocks in the memory block set, then apply for the first memory block for the fourth computing node.

[0108] In some embodiments of the present application, the fourth computing node may be any one of the N+M computing nodes.

[0109] In some embodiments of the present application, the above-mentioned N+M computing nodes obtain and release memory blocks in the memory block set.

[0110] In some embodiments of the present application, the above-mentioned memory block set may be a memory block set for applying for memory blocks and releasing memory blocks during the first model training. In other words, the application and release of memory blocks during the first model training are performed in the memory block set.

[0111] In some embodiments of the present application, when allocating memory blocks to a computing node, the electronic device can first determine whether there are free memory blocks in the memory block set. If there are free memory blocks, the memory blocks can be directly reused; if there are no free memory blocks, a memory block can be applied for the computing node.

[0112] In some embodiments of the present application, when allocating memory blocks to computing nodes, if there are free available memory blocks in the memory block set, the electronic device can take the number of the computing node and the number of the node from which the memory block was released last as a combination (node_id, last_top_node_id), and add them to the task queue of the memory block; if there are no free available memory blocks in the memory block set, the electronic device can apply for a memory block for the computing node, and take the number of the computing node and the number of the node from which the memory block was released last as a combination (node_id, last_top_node_id), and add them to the task queue of the applied memory block.

[0113] It is understandable that during the forward reasoning process of the gradient calculation node, the node value input needs to be kept and cannot be released, and the third calculation graph needs to be used as a whole to allocate memory to the node to ensure that the node value of the forward calculation can be saved to the back propagation stage. Therefore, this will cause the memory occupied during the first model training process to be much larger than the memory during reasoning.

[0114] In this regard, in the model training method provided in the embodiment of the present application, a greedy algorithm can be used to pre-determine the memory blocks to be reused, thereby determining the memory allocation strategy, thereby reducing resource usage during model training.

[0115] It should be noted that in the third calculation graph, the input values ​​and output values ​​of calculation nodes such as the activation function (Softmax) calculation node, the data reshaping (Reshape) calculation node, and the superposition (Add) calculation node correspond one to one, so these calculation nodes can directly reuse the memory blocks of their input nodes.

[0116] The following combination Figure 6 ,by Figure 6 The node numbers in indicate nodes, and the process of determining the memory allocation strategy corresponding to the third computation graph is exemplarily described.

[0117] Assume that the first order is 1, 2, 0, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 4, 16. Figure 7 As shown, for node 1, the electronic device can apply for allocation of memory block Memory_block_0 for it, with size (size) = 4096kb; for node 2, since node 2 is a data shaping (Reshape) computing node, node 2 can be directly reused;

[0118] For node 0, since Memory_block_0 is occupied by node 16, if Figure 8 As shown, a memory block Memory_block_1 needs to be applied for node 0. It is understandable that node 3 can also reuse Memory_block_1;

[0119] For node 5, since Memory_block_0 is occupied by node 16 and Memory_block_1 is occupied by node 6, Fig. 9 As shown, a new memory block Memory_block_2 needs to be allocated to node 5. It can be understood that the Add operation corresponding to node 6 can reuse Memory_block_2, and the Softmax operation corresponding to node 7 can also reuse Memory_block_2;

[0120] For node 8, Memory_block_2 released by node 7 can be reused; for node 9, since node 9 is an output node, the memory block Memory_block_2 of node 8 can be directly reused; for node 10, since node 10 is an input node, Fig.10 As shown, a memory block Memory_block_3 needs to be applied for node 10;

[0121] For node 11, since node 11 is a loss function node, it cannot directly reuse the memory block of the input node, and there is no free memory block available at this time. Therefore, Fig.11 As shown, it is necessary to apply for memory block Memory_block_4 for node 11; for node 12, node 12 can reuse the idle memory_block_3;

[0122] like Fig.12 As shown, for node 13, memory block Memory_block_2 is free, so node 13 can directly reuse memory block Memory_block_2; for node 14, Memory_block_1 is free, so node 14 can directly reuse memory block Memory_block_1; for node 15, Memory_block_2 is free, so node 15 can directly reuse memory block Memory_block_2; for node 4, Memory_block_3 is free, so node 4 can directly reuse memory block Memory_block_3; for node 16, Memory_block_1 is free, so node 16 can directly reuse memory block Memory_block_1.

[0123] The detailed information of memory allocation of computing nodes in the third computing graph is shown in Table 1 below:

[0124] Table 1

[0125]

[0126] It can be seen from Table 1 that if memory blocks are allocated for the first model in accordance with the memory allocation method, 3072kb+4096kb+4096kb+512kb+128kb+512kb+512kb+512kb+512kb+512kb+512kb+512kb+512kb+512kb+512kb+512kb+129kb+8kb=17161kb is required, while the memory block allocation strategy based on the greedy algorithm requires 4096kb+3072kb+512kb+512kb+512kb=8704kb, which greatly reduces the memory usage.

[0127] In actual implementation, the electronic device can also directly obtain the third computational graph and its corresponding memory allocation strategy, and save the third computational graph and its corresponding memory allocation strategy. During training, forward calculation can be performed first, and the forward calculation node can be executed once. Then, back propagation calculation can be performed, and finally the parameters of the training node can be updated. The cycle is iterated until the loss value stabilizes and no longer changes, and a trained model is obtained.

[0128] In some embodiments of the present application, for a model whose training parameters have been determined, the electronic device may determine the memory allocation strategy before training, and then before subsequent training in the electronic device, all memory may be allocated at one time to reduce memory allocation overhead.

[0129] In this way, by reusing the allocated memory blocks as much as possible, the memory overhead can be effectively reduced, and the continuous need for large memory blocks during model training can be avoided, thereby realizing model training in electronic devices.

[0130] Each of the above-mentioned method embodiments, or various possible implementation methods in each method embodiment can be executed separately, or any two or more of them can be executed in combination with each other. The specific implementation method can be determined according to actual usage requirements, and the embodiments of the present application do not limit this.

[0131] The model training method provided in the embodiment of the present application can be executed by a model training device. In the embodiment of the present application, the model training device executing the model training method is taken as an example to illustrate the model training device provided in the embodiment of the present application.

[0132] Fig.13 A possible structural diagram of the model training device involved in the embodiment of the present application is shown. Fig.13 As shown, the model training device 130 may include: a processing module 131.

[0133] Among them, the processing module 131 is used to obtain a first calculation graph corresponding to the first model, where the first calculation graph is used to describe the calculation order between N first calculation nodes of the first model, where N is a positive integer; and to determine M first calculation nodes from the N first calculation nodes, where M is a positive integer less than or equal to N; and, further used to calculate M gradients corresponding to the M first calculation nodes one by one, and to update the weight parameters of the corresponding first calculation nodes based on each gradient, so as to obtain the trained first model.

[0134] In a possible implementation, the processing module 131 is specifically configured to:

[0135] Obtain a second computation graph corresponding to the first model, where the second computation graph is used to describe a computation order between T first computation nodes included in the first model, where T is a positive integer less than N;

[0136] According to the second computing node among the T first computing nodes, a LoRA computing node is added to the T first computing nodes to obtain N first computing nodes, the input of the LoRA computing node is connected to the output of the previous computing node of the second computing node, and the output of the LoRA computing node is connected to the output of the next computing node of the second computing node;

[0137] A first computation graph is generated according to the N first computation nodes.

[0138] In a possible implementation, the processing module 131 is specifically used to determine the computing nodes from the LoRA computing node to the third computing node among the N first computing nodes as M first computing nodes, and the third computing node is an output node among the N first computing nodes.

[0139] In a possible implementation, the processing module 131 is further used to, before calculating the M gradients corresponding one-to-one to the M first computing nodes, add M gradient computing nodes to the first computing graph based on the M first computing nodes to generate a third computing graph, where the third computing graph is used to describe the calculation order between the M first computing nodes, and each of the M first computing nodes corresponds to a gradient computing node; and, further used to calculate the M gradients in sequence according to the third computing graph.

[0140] In one possible implementation, the above-mentioned processing module 131 is also used to determine a first order based on N+M first memory sizes, each first memory size corresponds to a computing node in the third computing graph, the first memory size is the memory size required for calculating the corresponding computing node, and the first order is used to indicate the order of allocating memory blocks to the N+M computing nodes in the third computing graph; and, it is also used to allocate memory blocks to the N+M computing nodes according to the memory allocation strategy based on the first order.

[0141] In a possible implementation, the memory allocation strategy includes at least one of the following:

[0142] When allocating a memory block to the fourth computing node, if there is a free memory block in the memory block set, the free memory block is allocated to the fourth computing node;

[0143] When allocating a memory block for the fourth computing node, if there is no free memory block in the memory block set, applying for the first memory block for the fourth computing node;

[0144] The fourth computing node is any one of the N+M computing nodes, and the N+M computing nodes obtain and release memory blocks in the memory block set.

[0145] The embodiment of the present application provides a model training device. Since the model training device can determine some first computing nodes (i.e., M first computing nodes) from the N first computing nodes of the first model when obtaining the first computing graph for describing the computing order between the N first computing nodes of the first model, and only calculate the gradients of the some first computing nodes without calculating the gradients of the N first computing nodes, the electronic device can complete the training of the first model by only updating the weight parameters of some first computing nodes based on the M gradients without updating the weight parameters of the N first computing nodes. Therefore, by reducing the number of nodes that need to perform gradient calculations, the resource usage during model training is reduced, thereby reducing the memory usage and training time during model training, and improving the efficiency of model training.

[0146] The model training device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than the terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtualreality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personalcomputer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personalcomputer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application is not specifically limited.

[0147] The model training device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0148] The model training device provided in the embodiment of the present application can implement the various processes implemented in the above-mentioned model training method embodiment and achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0149] Alternatively, if Fig.14 As shown, an embodiment of the present application also provides an electronic device 1400, including a processor 1401 and a memory 1402, wherein the memory 1402 stores a program or instruction that can be executed on the processor 1401, and when the program or instruction is executed by the processor 1401, each step of the above-mentioned model training method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0150] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0151] Fig.15 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0152] The electronic device 1500 includes but is not limited to: a radio frequency unit 1501, a network module 1502, an audio output unit 1503, an input unit 1504, a sensor 1505, a display unit 1506, a user input unit 1507, an interface unit 1508, a memory 1509, and a processor 1510 and other components.

[0153] Those skilled in the art will appreciate that the electronic device 1500 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1510 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.15 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0154] Among them, processor 1510 is used to obtain a first calculation graph corresponding to the first model, where the first calculation graph is used to describe the calculation order between N first calculation nodes of the first model, where N is a positive integer; and to determine M first calculation nodes from the N first calculation nodes, where M is a positive integer less than or equal to N; and, further used to calculate M gradients corresponding to the M first calculation nodes one by one, and to update the weight parameters of the corresponding first calculation nodes based on each gradient, so as to obtain the trained first model.

[0155] In a possible implementation, the processor 1510 is specifically configured to:

[0156] Obtain a second computation graph corresponding to the first model, where the second computation graph is used to describe a computation order between T first computation nodes included in the first model, where T is a positive integer less than N;

[0157] According to the second computing node in the T first computing nodes, a low-rank adaptive LoRA computing node is added to the T first computing nodes to obtain N first computing nodes, the input of the LoRA computing node is connected to the output of the previous computing node of the second computing node, and the output of the LoRA computing node is connected to the output of the next computing node of the second computing node;

[0158] A first computation graph is generated according to the N first computation nodes.

[0159] In a possible implementation, the processor 1510 is specifically used to determine the computing nodes from the LoRA computing node to the third computing node among the N first computing nodes as M first computing nodes, and the third computing node is an output node among the N first computing nodes.

[0160] In a possible implementation, the processor 1510 is further used to, before calculating the M gradients corresponding one-to-one to the M first computing nodes, add M gradient computing nodes to the first computing graph based on the M first computing nodes to generate a third computing graph, where the third computing graph is used to describe the calculation order between the M first computing nodes, and each of the M first computing nodes corresponds to a gradient computing node; and, further used to calculate the M gradients in sequence according to the third computing graph.

[0161] In one possible implementation, the processor 1510 is further used to determine a first order based on N+M first memory sizes, each first memory size corresponds to a computing node in the third computing graph, the first memory size is the memory size required for calculating the corresponding computing node, and the first order is used to indicate the order of allocating memory blocks to the N+M computing nodes in the third computing graph; and, is also used to allocate memory blocks to the N+M computing nodes according to the memory allocation strategy based on the first order.

[0162] In a possible implementation, the memory allocation strategy includes at least one of the following:

[0163] When allocating a memory block to the fourth computing node, if there is a free memory block in the memory block set, the free memory block is allocated to the fourth computing node;

[0164] When allocating a memory block for the fourth computing node, if there is no free memory block in the memory block set, applying for the first memory block for the fourth computing node;

[0165] The fourth computing node is any one of the N+M computing nodes, and the N+M computing nodes obtain and release memory blocks in the memory block set.

[0166] The embodiment of the present application provides an electronic device. Since the electronic device can determine some first computing nodes (i.e., M first computing nodes) from the N first computing nodes of the first model when obtaining a first computing graph for describing the computing order between the N first computing nodes of the first model, and only calculate the gradients of the some first computing nodes without calculating the gradients of the N first computing nodes, the electronic device can complete the training of the first model by updating only the weight parameters of some first computing nodes based on the M gradients without updating the weight parameters of the N first computing nodes. Therefore, by reducing the number of nodes that need to perform gradient calculations, the resource usage during model training is reduced, thereby reducing the memory usage and training time during model training, and improving the efficiency of model training.

[0167] It should be understood that in the embodiment of the present application, the input unit 1504 may include a graphics processor (Graphics Processing Unit, GPU) 15041 and a microphone 15042, and the graphics processor 15041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1506 may include a display panel 15061, and the display panel 15061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1507 includes a touch panel 15071 and at least one of other input devices 15072. The touch panel 15071 is also called a touch screen. The touch panel 15071 may include two parts: a touch detection device and a touch controller. Other input devices 15072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0168] The memory 1509 can be used to store software programs and various data. The memory 1509 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1509 may include a volatile memory or a non-volatile memory, or the memory 1509 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1509 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0169] The processor 1510 may include one or more processing units; optionally, the processor 1510 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1510.

[0170] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned model training method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0171] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0172] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned model training method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0173] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0174] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned model training method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0175] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0176] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0177] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A model training method, characterized in that: The method comprises: Obtain a first computation graph corresponding to the first model, where the first computation graph is used to describe a computation order between N first computation nodes of the first model, where N is a positive integer; Determine M first computing nodes from the N first computing nodes, where M is a positive integer less than or equal to N; M gradients corresponding to the M first computing nodes are calculated, and weight parameters of the corresponding first computing nodes are updated based on each gradient to obtain a trained first model.

2. The method according to claim 1, characterized in that The obtaining of a first calculation graph corresponding to the first model includes: Obtain a second computation graph corresponding to the first model, where the second computation graph is used to describe a computation order between T first computation nodes included in the first model, where T is a positive integer less than N; According to the second computing node among the T first computing nodes, a low-rank adaptive LoRA computing node is added to the T first computing nodes to obtain the N first computing nodes, the input of the LoRA computing node is connected to the output of the previous computing node of the second computing node, and the output of the LoRA computing node is connected to the output of the next computing node of the second computing node; Generate the first computation graph according to the N first computation nodes.

3. The method according to claim 2, characterized in that The determining of M first computing nodes from the N first computing nodes includes: The computing nodes from the LoRA computing node to the third computing node among the N first computing nodes are determined as the M first computing nodes, and the third computing node is an output node among the N first computing nodes.

4. The method according to claim 1, characterized in that: Before calculating the M gradients corresponding one-to-one to the M first computing nodes, the method further includes: Based on the M first computing nodes, M gradient computing nodes are added to the first computing graph to generate a third computing graph, wherein the third computing graph is used to describe the computing order between the M first computing nodes, and each of the M first computing nodes corresponds to a gradient computing node; According to the third computation graph, the M gradients are calculated in sequence.

5. The method according to claim 4, characterized in that The method further comprises: Determine a first order based on N+M first memory sizes, each first memory size corresponds to a computing node in the third computing graph, the first memory size is a memory size required for computing the corresponding computing node, and the first order is used to indicate an order of allocating memory blocks to the N+M computing nodes in the third computing graph; Based on the first order, memory blocks are allocated to the N+M computing nodes according to a memory allocation strategy.

6. A model training device, characterized in that: The device comprises: a processing module; The processing module is used to obtain a first calculation graph corresponding to the first model, where the first calculation graph is used to describe the calculation order between N first calculation nodes of the first model, where N is a positive integer; The processing module is further used to determine M first computing nodes from the N first computing nodes, where M is a positive integer less than or equal to N; The processing module is also used to calculate M gradients corresponding to the M first computing nodes one by one, and update the weight parameters of the corresponding first computing nodes based on each gradient to obtain the trained first model.

7. The device according to claim 6, characterized in that The processing module is specifically used for: Obtaining a second computation graph corresponding to the first model, where the second computation graph is used to describe a computation order between T first computation nodes included in the first model, where T is a positive integer less than N; According to the second computing node among the T first computing nodes, a LoRA computing node is added to the T first computing nodes to obtain the N first computing nodes, the input of the LoRA computing node is connected to the output of the previous computing node of the second computing node, and the output of the LoRA computing node is connected to the output of the next computing node of the second computing node; Generate the first computation graph according to the N first computation nodes.

8. The device according to claim 7, characterized in that The processing module is specifically used to determine the computing nodes from the LoRA computing node to the third computing node among the N first computing nodes as the M first computing nodes, and the third computing node is the output node among the N first computing nodes.

9. The device according to claim 6, characterized in that The processing module is further configured to, before calculating the M gradients corresponding to the M first computing nodes one by one, add M gradient computing nodes to the first computing graph based on the M first computing nodes to generate a third computing graph, wherein the third computing graph is used to describe the computing order between the M first computing nodes, and each of the M first computing nodes corresponds to a gradient computing node; The processing module is further used to calculate the M gradients in sequence according to the third calculation graph.

10. The device according to claim 9, characterized in that The processing module is further used to determine a first order based on N+M first memory sizes, each first memory size corresponds to a computing node in the third computing graph, the first memory size is a memory size required for calculating the corresponding computing node, and the first order is used to indicate an order of allocating memory blocks to the N+M computing nodes in the third computing graph; The processing module is further used to allocate memory blocks to the N+M computing nodes based on the first order and according to a memory allocation strategy.

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