Method for improving film step coverage rate by using atomic layer etching technology

Abstract

The invention relates to a method for improving the step coverage rate of a thin film material in a semiconductor manufacturing process. The method comprises the following steps of: depositing the thin film material on a (non-planar) structure with a certain depth-to-width ratio; obtaining step coverage rate data of the thin film material; selecting an atomic layer etching (ALE) chemical reaction for the thin film material; parameters of the ALE process are adjusted, so that the step coverage rate of the ALE process is smaller than that of the thin film material; and performing atomic layer etching on the thin film material by using the selected ALE reaction and parameters. And if necessary, repeating the etching or deposition-etching circulation step until the required target step coverage rate is reached. According to the invention, the step coverage rate of a thin film material can be improved to a height which cannot be reached by a thin film deposition technology, so that the performance and yield of a semiconductor device can be improved. The invention provides a new way for the continuous development of the semiconductor technology.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a manufacturing process for high aspect ratio structures in DRAM and 3D NAND. Background Art

[0002] In high-end semiconductor chips, there are many units with high aspect ratio structures. For example, in current DRAM chips, the aspect ratio of capacitor units has long exceeded 30:1. And as the density of memory per unit area continues to increase, the aspect ratio of capacitors must continue to increase to compensate for the loss of (wafer) area occupied by capacitors. Especially for capacitors with deep hole structures, a higher aspect ratio is required. The same is true in 3D NAND chips, for example, the aspect ratio of V-NAND channel holes has exceeded 40:1.

[0003] As the aspect ratio increases, related processes also encounter greater challenges. For example, it is increasingly difficult for thin film deposition processes to achieve ideal step coverage. The emergence of atomic layer deposition (ALD) technology has alleviated this difficulty to a large extent. Due to the self-limiting characteristics of its surface reaction, ALD has superior step coverage performance than other thin film deposition technologies. This feature makes it widely used in the semiconductor industry in the process of high aspect ratio structures to achieve the required high step coverage. However, as device density increases and aspect ratios increase, even processes such as ALD that can achieve high step coverage are beginning to fail to meet the needs.

[0004] To this end, the present invention is proposed. Summary of the invention

[0005] The purpose of the present invention is to further improve the step coverage of thin film deposition technology, so that the quality and performance of high-end semiconductor devices can be improved and developed towards the next generation. The present invention is applicable to any thin film deposition technology.

[0006] In order to achieve the above objectives, the present invention provides the following technical solutions, which include:

[0007] Depositing thin film materials on structures with a certain aspect ratio,

[0008] Obtaining the characteristics and step coverage data of the thin film material,

[0009] The chemical reaction of atomic layer etching (ALE) is selected according to the characteristics of the thin film material,

[0010] The process parameters of ALE are selected according to the step coverage of the thin film material so that the step coverage of the ALE is lower than the step coverage of the thin film material.

[0011] The thin film material is etched according to the ALE reaction and process parameters selected above.

[0012] Because the step coverage of ALE is smaller than that of the thin film material, ALE etches more material at the top of the structure than at the bottom, and the top / bottom etched thickness difference is larger than the top / bottom difference of the thin film material before etching. Therefore, the top / bottom thickness difference of the remaining thin film material after ALE etching is reduced, and the step coverage is improved.

[0013] For example, if the step coverage of the thin film material deposited on a trench with a high aspect ratio is 80%, in order to improve the step coverage of the thin film material, an atomic layer etching process condition with a step coverage of 50% is selected. After etching away 25% of the material at the top of the trench, the step coverage of the remaining thin film material is 90%. If 40% of the thin film material is etched away, the step coverage of the remaining thin film material will reach 100%. If further etching is performed, the step coverage of the remaining thin film material will be greater than 100%.

[0014] If the step coverage improved by one ALE etching is not enough, the above ALE etching process can be repeated.

[0015] Because the selected ALE process parameters make the step coverage of ALE less than the step coverage of the thin film material, the above ALE etching will increase the step coverage of the remaining part of the thin film material and eventually be greater than 100%. If some applications require more material to be deposited at the bottom of the structure than at the top of the structure, the technology provided by the present invention can also be used.

[0016] In order to repeat the above process continuously while maintaining a certain film thickness, a cycle of etching-deposition-etching-deposition can be performed continuously.

[0017] In summary, compared with the prior art, the present invention achieves the purpose of further improving the step coverage of thin film materials. In particular, for the step coverage technical indicators that the ALD technology with the best step coverage performance cannot achieve, the present invention can still achieve a step coverage of more than 100%. It provides a new way for the continued development of semiconductor technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 : is a schematic diagram of a thin film deposited on a structure with a certain aspect ratio. The shaded portion 101 is the structure with a certain aspect ratio. 102 is the upper surface of the thin film deposited on the structure. 103 is the thin film.

[0019] Figure 2: The dotted line 102b is the target position of the ALE etching, that is, the upper surface of the film after etching. 103a is the portion of the film 103 etched by ALE, and 103b is the remaining portion of the film 103 after ALE etching.

[0020] Figure 3 :yes Figure 1 and Figure 2 Schematic diagram of the thin film material after ALE etching. The step coverage of the thin film is improved. DETAILED DESCRIPTION

[0021] The following will describe embodiments of the present invention. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, some well-known common sense and technical descriptions are omitted in the description to avoid unnecessary confusion of the concept of the present invention.

[0022] Example 1: In the capacitor manufacturing process of DRAM, if the step coverage of the bottom electrode TiN is 90%, the target step coverage is 100%. An ALE reaction step can be selected to first oxidize TiN and then fluorinate TiO2 to generate TiF4 and volatilize it. In actual operation, the TiN surface is first oxidized with an oxidant (such as ozone or oxygen-containing plasma). The oxidation process needs to be controlled to achieve a thick top oxide layer, a thin bottom oxide layer, and a step coverage of the oxide layer of 50%. In the next step of the surface fluorination reaction, only the oxidized part is removed. Because the step coverage of the TiN oxidation reaction is 50%, the corresponding step coverage of ALE is also 50%. After etching away the top 25% of the thin film material using this ALE process, the step coverage of the remaining thin film material is 103%.

[0023] Example 2: In the capacitor manufacturing process of DRAM, if the step coverage of the high dielectric constant (high-k) dielectric layer HfO2 is 80%. HfO2 can be fluorinated first to generate HfF4 on the surface, and then BCl3 is used to react with HfF4 to generate volatile HfCl4 and BF3. In actual operation, the HfO2 surface is first defluorinated with fluoride. The fluorination process can be controlled to achieve a similar degree of fluorination at the top and bottom. When BCl3 is used to remove the surface fluoride in the next step, the process is controlled to remove more fluoride at the top and less fluoride at the bottom, reaching a bottom removal amount of only 50% of the top removal amount. After etching away 25% of the HfO2 thin film material on the top with this ALE process, the step coverage of the remaining HfO2 thin film material is 90%. The same method can also be used to improve the step coverage of ZrO2 thin film materials on DRAM capacitors.

[0024] Example 3: In the manufacturing process of 3D NAND, if the step coverage of the silicon nitride SiN charge trapping layer is 90%, the SiN surface can be oxidized first to generate silicon oxide SiO2, and then SiO2 can be etched using highly selective thermal ALE. In actual operation, the SiN surface is first oxidized using an oxidant (such as ozone or oxygen-containing plasma). The oxidation process needs to be controlled to achieve a thick top oxide layer, a thin bottom oxide layer, and a step coverage of the oxide layer of 50%. In the next step of the highly selective thermal ALE reaction, only the oxidized portion is removed. Because the step coverage of the SiN oxidation reaction is 50%, the corresponding step coverage of the ALE is also 50%. After etching away the top 25% of the SiN film material using this ALE process, the step coverage of the remaining SiN film material is 103%.

Claims

1. A method for improving the step coverage of a thin film in a semiconductor manufacturing process, characterized in that: include: Depositing a thin film material on a structure with a certain aspect ratio; etching the thin film material using an atomic layer etching (ALE) process; if necessary, repeating the above steps until a desired target step coverage is achieved.

2. According to the method of claim 1, the applicable range of the aspect ratio of the structure is 10:1 to 300:

1.

3. According to the method described in claim 1, there is no limitation on the technology for depositing thin film materials, although it will be more widely used in thin film materials deposited by technologies including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), ion beam deposition (IBD), vapor phase epitaxy (EPI), electron beam evaporation (e-beam), electrochemical deposition (electroplating), surface oxidation reaction (for example, generating oxides or nitrides by oxidation or nitridation of the surface), surface reduction reaction (for example, reducing metal oxides or metal nitrides to metals, etc.).

4. The method according to claim 1, wherein the thin film material comprises insulating material, semiconductor material, and conductive material, and the material can be etched by ALE or can be etched by ALE after other surface reactions. 5 . The method according to claim 1 , wherein the atomic layer etching process comprises thermal atomic layer etching and plasma atomic layer etching. 6 . The method according to claim 1 , wherein the step coverage of the atomic layer etching process is lower than the step coverage of the thin film deposition process. 7 . The method according to claim 1 , wherein thin film deposition and atomic layer etching are repeatedly cycled to achieve a target thickness and a target step coverage of the thin film material.

8. The method according to claim 1, wherein for a multilayer thin film structure composed of different materials, different atomic layer etching reactions are used to etch different materials.

9. The method according to claim 4, wherein the insulating material includes but is not limited to silicon oxide, silicon nitride, germanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, copper oxide, titanium oxide, low-k materials, etc.

10. The method according to claim 4, wherein the semiconductor material includes but is not limited to silicon, germanium, silicon carbide, gallium nitride, indium phosphide, gallium arsenide, etc.

11. The method according to claim 4, wherein the conductive material includes but is not limited to titanium, titanium nitride, titanium carbide, titanium silicide, tungsten, tungsten nitride, tungsten silicide, tantalum, tantalum nitride, cobalt, etc. 12 . The method according to claim 5 , wherein the thermal atomic layer etching is an atomic layer etching without plasma participating in the etching reaction or producing reactants.

13. The method according to claim 5, wherein the plasma atomic layer etching is an atomic layer etching in which plasma participates in the etching reaction or produces reactants.

14. The method according to claim 6, wherein the step coverage of the atomic layer etching process is at least 10 percentage points lower than the step coverage of the thin film deposition process.

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