Polysilicon gate spacing process window electrical test structure, component and test method

Abstract

The present invention provides a process window electrical test structure for polysilicon gate spacing, which is placed within a cutting path and includes at least one formal test structure. The formal test structure includes an N-well resistor reference test structure and a polysilicon gate resistor test structure. The N-well resistor reference test structure includes a rectangular N-well resistor within the active area, and first and second test leads located at both ends of the N-well resistor, the first and second test leads being electrically connected to first and second test pads, respectively. The polysilicon gate resistor test structure includes the N-well resistor reference test structure, at least two long, parallel strips of polysilicon located above the N-well resistor, and third and fourth test leads located at both ends of the N-well resistor and the two polysilicon strips, the third and fourth test leads being electrically connected to third and fourth test pads, respectively. This solution enables non-destructive testing of the metal silicide preparation process between polysilicon gates, reducing costs and improving monitoring convenience.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a process window electrical test structure, component and test method for polysilicon gate spacing. Background Art

[0002] In the field of semiconductor chips, in order to save area and reduce costs, when designing semiconductor chips, MOS in series are often not drilled with ohmic contacts (CT) in the middle, and the distance between polysilicon gates (Poly) is set to the minimum value specified by the design rules. At the same time, it is also necessary to ensure that sidewalls (spacers) and metal silicides can be formed between the polysilicon gates.

[0003] However, due to excessively wide sidewalls, residual silicon oxide in the middle of the sidewalls not being completely removed, and poor hole-filling capabilities during metal filling, the metal material is unable to enter the potential silicide-free region (between the two polysilicon gate sidewalls) and make contact with the silicon. Consequently, silicide formation in this region fails as expected, leading to abnormal series resistance and impacting chip functionality and performance. Existing techniques typically use slicing to monitor the metal silicide between the polysilicon gate sidewalls of series-connected MOS transistors. However, slicing can damage the wafer and is costly, making it unsuitable for industrial production. Summary of the Invention

[0004] In view of the above problems, the present invention provides a process window electrical test structure, component and test method for polysilicon gate spacing to solve the problem that when monitoring whether metal silicide is formed between MOS devices connected in series by slicing, the wafer will be damaged and the cost is high.

[0005] According to a first aspect of the present invention, a process window electrical test structure for a polysilicon gate spacing is provided. The process window electrical test structure is placed in a dicing street of a wafer and includes at least one formal test structure. The formal test structure includes an N-well resistance reference test structure and a polysilicon gate resistance test structure. The N-well resistance reference test structure and the polysilicon gate resistance test structure are arranged in parallel up and down in the dicing street. The N-well resistance reference test structure is provided with a first test pad and a second test pad, and the polysilicon gate resistance test structure is provided with a third test pad and a fourth test pad. The first test pad, the third test pad, the second test pad, and the fourth test pad are staggered along the dicing street direction, wherein:

[0006] The N-well resistance reference test structure includes:

[0007] An N-well resistor in the active area, the N-well resistor being rectangular, and a first test lead and a second test lead located at both ends of the rectangular N-well resistor, the first test lead and the second test lead being electrically connected to the first test pad and the second test pad, respectively;

[0008] The polysilicon gate resistance test structure includes:

[0009] The N-well resistor reference test structure and at least two long strips of polysilicon located above the N-well resistor and a third test lead and a fourth test lead located at both ends of the N-well resistor and the two long strips of polysilicon. The two long strips of polysilicon are arranged in parallel, and the distance between the two polysilicons is located between the third test lead and the fourth test lead. The third test lead and the fourth test lead are electrically connected to the third test pad and the fourth test pad respectively.

[0010] Optionally, the two long strip-shaped polysilicon sidewalls are both formed with sidewalls, and the distance between the two polysilicon strips is the distance between the sidewalls.

[0011] Optionally, the test structure further includes a virtual test structure, which is symmetrically arranged at upper and lower positions of the formal test structure; the virtual test structure has the same structure as the formal test structure.

[0012] According to a second aspect of the present invention, a method for manufacturing a process window electrical test structure for a polysilicon gate spacing is provided, which is used to manufacture the process window electrical test structure for a polysilicon gate spacing described in the first aspect of the present invention, comprising:

[0013] Forming the N-well resistance reference test structure includes:

[0014] forming an N-well resistor in an active area within the cutting street, wherein the N-well resistor is rectangular;

[0015] forming first and second test leads at both ends of the rectangular N-well resistor respectively;

[0016] The polysilicon gate resistance test structure is fabricated in the cutting lane and arranged in parallel with the N-well resistance reference test structure, including:

[0017] At least two long strips of polysilicon are formed in the area above the N-well resistor; the two long strips of polysilicon are arranged in parallel;

[0018] A third test lead-in terminal and a fourth test lead-in terminal are formed at both ends of the N-well resistor and the two long strips of polysilicon respectively. The distance between the two strips of polysilicon is located between the third test lead-in terminal and the fourth test lead-in terminal.

[0019] According to a third aspect of the present invention, a method for measuring a contact layer is provided, comprising:

[0020] Detecting the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure in the process window electrical test structure for the polysilicon gate spacing according to any one of the third aspects of the present invention;

[0021] Whether the metal silicide layer is formed between the two long strips of polysilicon is determined according to the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure.

[0022] According to the fourth aspect of the present invention, a process window electrical test component for polysilicon gate spacing is provided, comprising several process window electrical test structures for polysilicon gate spacing as described in any one of the first aspect of the present invention, wherein the spacings between the polysilicon are different.

[0023] According to a fifth aspect of the present invention, a method for determining a minimum spacing in a semiconductor process is provided, comprising:

[0024] Obtaining the spacing between polysilicon layers corresponding to the process window electrical test structures of the plurality of polysilicon gate spacings as described in the first aspect of the present invention;

[0025] Measuring the total resistance of the process window electrical test structure for each polysilicon gate spacing;

[0026] Obtaining a first relationship model between the spacing between the polysilicon and the corresponding total resistance according to the spacing between the polysilicon and the total resistance;

[0027] According to the first relationship model, the value of the minimum distance is determined.

[0028] Optionally, the method further includes:

[0029] Obtaining slices of the process window electrical test structures of the plurality of polysilicon gate spacings;

[0030] The value of the minimum distance is determined according to the plurality of slices and the first relationship model.

[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0032] In the process window electrical test structure of the polysilicon gate spacing provided by the technical solution of the present invention, a test structure including a polysilicon gate resistance test structure and an N-well resistance reference test structure is set. Compared with the N-well resistance reference test structure, the polysilicon gate resistance test structure is provided with at least two long strips of polysilicon above the N-well resistance, so that in the subsequent process, the N-well resistance of the N-well resistance reference test structure will be completely covered with a metal silicide barrier layer (SAB, Salicide-block), resulting in the area on its N-well resistance being a metal silicide-free area; while in the polysilicon gate resistance test structure, the area covered by polysilicon will not form a metal silicide barrier layer. The resistance of this area is equivalent to the resistance of the N-well resistor covered by the metal silicide barrier layer. Only the area between the two polysilicon strips is not covered by the metal silicide barrier layer, where metal silicide will form. Therefore, only the area between the two polysilicon strips may affect the resistance of the polysilicon gate resistance test structure. The polysilicon gate resistance test structure and the N-well resistance reference test structure are respectively connected through a pad and a pad lead-out terminal. By testing the resistance between the polysilicon gate resistance test structure and the N-well resistance reference test structure and comparing the resistances between the two, the purpose of non-destructive testing of the metal silicide preparation process between polysilicon gates can be achieved using electrical testing methods. This makes it possible to monitor whether metal silicide has formed between two polysilicon strips without slicing, reducing costs, improving monitoring convenience, and preventing wafer damage.

[0033] Furthermore, a method for determining the minimum spacing of a semiconductor process is provided. The method comprises setting a plurality of process window electrical test structures for polysilicon gate spacing, and setting the spacing between polysilicon in the polysilicon gate resistance test structures corresponding to the process window electrical test structures for the polysilicon gate spacing to different sizes. After obtaining the spacing between the plurality of polysilicon and the plurality of total resistance values ​​corresponding to the process window electrical test structures for the polysilicon gate spacing, a first relationship model for the variation of the spacing between the polysilicon is established based on the spacing between the plurality of polysilicon and the plurality of total resistance values. The value of the minimum spacing can be determined based on the first relationship model. Thus, when developing a new node or establishing a new production line, the method provided by the present invention can determine the minimum spacing at the process node, providing a reference for monitoring the spacing between polysilicon in subsequent production stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The schematic diagram is a diagram illustrating the structure of two adjacent polysilicon pieces in a series MOS device;

[0035] Figure 2 A schematic diagram of a process window electrical test structure for polysilicon gate spacing provided in one embodiment of the present invention;

[0036] Figure 3 A schematic diagram of a pad structure of a process window electrical test structure for polysilicon gate spacing provided by one embodiment of the present invention;

[0037] Figure 4 for Figure 2 The process window electrical test structure of the polysilicon gate spacing is shown as a cross-sectional view along p1-p1' (a), a cross-sectional view along p2-p2' (b), and a cross-sectional view along p3-p3' (c);

[0038] Figure 5 for Figure 2 A cross-sectional view of a process window electrical test structure for a polysilicon gate spacing along the line p4-p4' is shown;

[0039] Figure 6 A flowchart of a method for determining a minimum spacing in a semiconductor process according to an embodiment of the present invention;

[0040] Figure 7 A schematic diagram of a process window electrical test structure for polysilicon gate spacing provided by another embodiment of the present invention;

[0041] Figure 8 A first relationship model between the spacing between polysilicon layers and the corresponding total resistance is provided in an embodiment of the present invention.

[0042] Description of reference numerals:

[0043] 10-potentially metal silicide-free area;

[0044] 30-substrate;

[0045] 40-polysilicon;

[0046] 50-side wall;

[0047] 60-metal silicide-free area;

[0048] 70-metal silicide barrier layer;

[0049] 80-resistance zone;

[0050] 1- Process window electrical test structure of polysilicon gate spacing;

[0051] 11-Formal test structure;

[0052] 111-polysilicon gate resistance test structure;

[0053] 1111-third test pad;

[0054] 1112- fourth test pad;

[0055] 1113-polysilicon;

[0056] 1114-third test lead-out terminal;

[0057] 1115-Fourth test lead-out terminal;

[0058] 112-N well resistance reference test structure;

[0059] 1121-first test pad;

[0060] 1122-second test pad;

[0061] 1123-N well resistor;

[0062] 1124-first test lead-out terminal;

[0063] 1125-second test lead-out terminal;

[0064] 101-substrate;

[0065] 102-P well region;

[0066] 103-Isolation structure;

[0067] 104-N-type heavily doped region;

[0068] 12-Dummy test structure. DETAILED DESCRIPTION

[0069] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0070] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0071] As described in the background art, the technical solution of the present invention aims to solve the problem of wafer damage and high cost when monitoring whether metal silicide is formed between series-connected MOS devices by slicing.

[0072] Figure 1 The figure is a schematic diagram illustrating the structure of two adjacent polysilicon pieces in a series MOS device.

[0073] Please refer to Figure 1 The structure includes two polysilicon blocks 40 on a substrate 30, with sidewalls 50 formed on the sidewalls of the polysilicon. When the two polysilicon blocks are very close, even at the minimum space, for example Figure 1 As for the potential non-silicide region 10 shown, since spacers need to be formed on both sides of the polysilicon, the space between the two for forming metal silicide will be occupied. At the 0.18um node, the minimum spacing (Polyminimum space) between the polysilicon gates will be greater than the sum of the sidewalls on both sides. Therefore, under normal circumstances, metal silicide can and should be formed in the potential non-silicide region 10. However, during the process, the sidewalls may be made too wide, or the oxide in the middle of the sidewalls may not be completely removed. Or when filling the metal material (such as Co, Ti, NiPt, etc.), due to the poor hole filling ability of the process, the metal material cannot enter the potential non-silicide region 10 and contact the silicon, resulting in the failure to form metal silicide in this area as expected, which in turn leads to abnormal series resistance, affecting the function and performance of the chip.

[0074] From this, we can conclude that based on the deduction that the offset of the spacing between polysilicon (poly space) causes the metal silicide to not grow normally and leads to abnormal series resistance, the stability of the poly space can be detected by measuring the resistance change of the area between polysilicon.

[0075] However, due to the lack of in-line measurement in the existing technology, it is necessary to set up multiple sets of experiments with different polyspaces and determine the minimum poly spacing and process window through repeated slicing. In addition, slicing is also required to monitor the stability of the process later. This method may cause wafer damage and is costly, which is not conducive to industrial production.

[0076] The methods and problems of the prior art have prompted the inventors of this application to think that if there is a method for electrical measurement: using electrical parameters as characteristic parameters to reflect whether metal silicide is formed in the potential metal-free silicide area 10, in the early stage of developing new technology nodes and establishing production lines, by continuously collecting these electrical parameters, a distribution diagram of the electrical parameters changing with the poly space is established, and the minimum gate spacing and process window are determined while also determining the normal range of the parameter. Then, in the later stage, the stability of the process can be determined by the electrical parameters, which can achieve cost savings compared to the traditional slicing method.

[0077] In view of this, an embodiment of the present invention provides a process window electrical test structure for polysilicon gate spacing, wherein the process window electrical test structure is placed in a cutting path of a wafer and includes at least one formal test structure, wherein the formal test structure includes an N-well resistance reference test structure and a polysilicon gate resistance test structure, wherein the N-well resistance reference test structure and the polysilicon gate resistance test structure are arranged in parallel up and down in the cutting path, wherein the N-well resistance reference test structure is provided with a first test pad and a second test pad, and the polysilicon gate resistance test structure is provided with a third test pad and a fourth test pad, wherein the first test pad, the third test pad, the second test pad, and the fourth test pad are staggered along the cutting path direction, wherein:

[0078] The N-well resistance reference test structure includes:

[0079] An N-well resistor in the active area, the N-well resistor being rectangular, and a first test lead and a second test lead located at both ends of the rectangular N-well resistor, the first test lead and the second test lead being electrically connected to the first test pad and the second test pad, respectively;

[0080] The polysilicon gate resistance test structure includes:

[0081] An N-well resistor reference test structure and at least two long strips of polysilicon located above the N-well resistor and a third test lead and a fourth test lead located at both ends of the N-well resistor and the two long strips of polysilicon. The two long strips of polysilicon are arranged in parallel, and the distance between the two polysilicons is located between the third test lead and the fourth test lead. The third test lead and the fourth test lead are electrically connected to the third test pad and the fourth test pad, respectively.

[0082] In the process window electrical test structure of the polysilicon gate spacing provided by the technical solution of the present invention, a test structure including a polysilicon gate resistance test structure and an N-well resistance reference test structure is set. Compared with the N-well resistance reference test structure, the polysilicon gate resistance test structure is provided with at least two long strips of polysilicon above the N-well resistance, so that in the subsequent process, the N-well resistance of the N-well resistance reference test structure will be completely covered with a metal silicide barrier layer (SAB, Salicide-block), resulting in the area on its N-well resistance being a metal silicide-free area; while in the polysilicon gate resistance test structure, the area covered by polysilicon will not form a metal silicide barrier layer. The resistance of this region is equivalent to that of the N-well resistor covered by the metal silicide barrier layer. Only the region between the two polysilicon strips is not covered by the metal silicide barrier layer, where metal silicide may form. Therefore, only the region between the two polysilicon strips may affect the resistance of the polysilicon gate resistance test structure. The polysilicon gate resistance test structure and the N-well resistance reference test structure are respectively connected via a pad and a pad lead-out terminal. By testing the resistance between the polysilicon gate resistance test structure and the N-well resistance reference test structure and comparing the resistances between the two, the purpose of non-destructive testing of the metal silicide preparation process between polysilicon gates can be achieved using electrical testing methods. Whether metal silicide has formed between two polysilicon strips can be monitored without slicing, reducing costs, improving monitoring convenience, and preventing wafer damage.

[0083] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0084] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0085] Please refer to Figure 2-Figure 5 ,in, Figure 2 A schematic diagram of a process window electrical test structure for polysilicon gate spacing provided in one embodiment of the present invention; Figure 3 A schematic diagram of a pad structure of a process window electrical test structure for polysilicon gate spacing provided by one embodiment of the present invention; Figure 4 for Figure 2 The process window electrical test structure of the polysilicon gate spacing is shown as a cross-sectional view along p1-p1' (a), a cross-sectional view along p2-p2' (b), and a cross-sectional view along p3-p3' (c); Figure 5 for Figure 2 The cross-sectional view of the process window electrical test structure for the polysilicon gate spacing is taken along p4-p4'.

[0086] like Figure 2-Figure 5As shown, an embodiment of the present invention provides a process window electrical test structure 1 for a polysilicon gate spacing. The process window electrical test structure 1 is placed in a cutting path of a wafer and includes at least one formal test structure 11. The formal test structure 11 includes an N-well resistance reference test structure 112 and a polysilicon gate resistance test structure 111. The N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 are arranged in parallel up and down in the cutting path. The N-well resistance reference test structure 112 is provided with a first test pad 1121 and a second test pad 1122. The polysilicon gate resistance test structure 111 is provided with a third test pad 1111 and a fourth test pad 1112. The first test pad 1121, the third test pad 1111, the second test pad 1122, and the fourth test pad 1112 are staggered along the cutting path direction.

[0087] The N-well resistance reference test structure 112 includes:

[0088] An N-well resistor 1123 in the active area is rectangular, and a first test lead 1124 and a second test lead 1125 are located at both ends of the rectangular N-well resistor 1123. The first test lead 1124 and the second test lead 1125 are electrically connected to the first test pad 1121 and the second test pad 1122 respectively.

[0089] The polysilicon gate resistance test structure 111 includes:

[0090] The N-well resistor reference test structure 112 and at least two long strips of polysilicon 1113 located above the N-well resistor 1123, and a third test lead 1114 and a fourth test lead 1115 located at both ends of the N-well resistor 1123 and the two long strips of polysilicon 1113. The two long strips of polysilicon 1113 are arranged in parallel, and the distance between the two polysilicon 1113 is located between the third test lead 1114 and the fourth test lead 1115. The third test lead 1114 and the fourth test lead 1115 are electrically connected to the third test pad 1111 and the fourth test pad 1112, respectively.

[0091] See also Figure 2 The N-well resistor 1123 can be understood as the resistor corresponding to the portion of the N-well region serving as the resistor region 80 in the active region 105 on the substrate. Figure 2 , and combined with the graph pair Figure 4 、 Figure 5Comparing the polysilicon gate resistor test structure 111 and the N-well resistor reference test structure 112, it can be seen that, except for the structure of the region above the N-well resistor 1123, the structures of other regions are identical. In the region above the N-well resistor 1123, the N-well resistor reference test structure 112 has the same structure as a conventional device, both being completely covered by the metal silicide barrier layer 70, with the region above it being a metal silicide-free region 60. In the polysilicon gate resistor test structure 111, metal silicide may form between two polysilicon lines 1113, while metal silicide will not form in the region covered by the polysilicon 1113. This is equivalent to the resistance of the N-well resistor 1123 covered by the metal silicide barrier layer 70. Only the region between the two polysilicon lines 1113 may affect the resistance change of the polysilicon gate resistor test structure 111 due to the possible formation of metal silicide, thereby generating a resistance difference between the polysilicon gate resistor test structure 111 and the N-well resistor reference test structure 112.

[0092] Continue reading Figure 3 If the polysilicon spacing (Poly space) is sufficiently small that metal silicide cannot form between two polysilicon pieces 1113, experiments have shown that the resistance measured between the first test pad 1121 and the second test pad 1122 is equal to the resistance between the third test pad 1111 and the fourth test pad 1112. If the polysilicon spacing is larger, when metal silicide forms in the region between the polysilicon pieces, the resistance measured between the first test pad 1121 and the second test pad 1122 is greater than the resistance between the third test pad 1111 and the fourth test pad 1112. Therefore, by comparing the resistance between the two test pads of the polysilicon gate resistance test structure and the resistance between the two test pads of the N-well resistance reference test structure, the present invention can monitor whether metal silicide has formed between polysilicon pieces using an electrical test method. Compared with existing slicing-based monitoring methods, the electrical testing method provided by the present invention significantly reduces costs, improves monitoring convenience, and does not cause wafer damage.

[0093] In one embodiment, Figure 5 As shown, the sidewalls of the two long strips of polysilicon 1113 are both formed with spacers 50. In this case, the spacing between the two polysilicon strips 1113 is specifically the spacing between the sidewalls 50 of the two polysilicon strips 1113. Therefore, in this embodiment, it is possible to monitor the metal silicide formed between the two polysilicon sidewalls under the influence of factors such as the sidewalls being affected by process fluctuations and causing the poly space to shift.

[0094] like Figure 2 、 Figure 4 and Figure 5 As shown, the N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 further include: a substrate 101, a P-well region 102 formed on the substrate 101 and distributed on both sides of the N-well resistor 1123, an isolation structure 103 formed in the P-well region 102, and an N-type heavily doped region 104. The first test lead 1124 and the second test lead 1125 are in contact with the N-type heavily doped region 104 in the N-well resistance reference test structure 112, and the third test lead 1114 and the fourth test lead 1115 are both in contact with the N-type heavily doped region 104 in the polysilicon gate resistance test structure 111. The N-well resistor 1123 in the N-well resistance reference test structure 112 is covered by a metal silicide barrier layer 70 ( Figure 2 1 is a schematic diagram of the N-well resistor in the reference test structure 112, and the metal silicide barrier layer on the N-well resistor is not illustrated).

[0095] Continue to refer Figure 2 and Figure 4 As a preferred embodiment, the length of the region above the N-well resistor 1123 in the polysilicon gate resistance test structure 111 is consistent with the length of the N-well resistor 1123 in the N-well resistance reference test structure 112, and the outer boundaries of the two polysilicon blocks are flush with the boundaries of the metal silicide barrier layer 70. Furthermore, other aspects of the polysilicon gate resistance test structure 111 and the N-well resistance reference test structure 112 are consistent, such as the size and spacing of the source and drain implant regions to maintain consistent ohmic contact, the number of contact holes, the distances from the contact holes to the resistor region 80, and the size of the resistor region 80 in both structures. This helps to mitigate the effects of irrelevant variables.

[0096] Furthermore, to achieve better uniformity and eliminate the impact of process fluctuations, it is preferable to set the distance between the polysilicon gate resistance test structure 111 and the N-well resistance reference test structure 112 to be sufficiently small. For example, the distance can be set within a range from the minimum distance specified by the process design rules to twice the minimum distance. Specifically, the minimum distance specified by the process design rules varies at different process nodes, and the minimum distance specified by the design rules is well known to those skilled in the art and will not be described in detail here. Those skilled in the art can select an appropriate distance between the polysilicon layers of the series-connected MOS tubes according to different process technology nodes.

[0097] As a further preferred method, in order to eliminate the influence of other processes, such as the drift of the size of the active area (AA), polysilicon, N-well, etc., their sizes should be appropriately increased. However, if these sizes are set too large, the resistance change caused between the sidewalls of the polysilicon sidewalls will be too small to be detected, so the sizes of these structural layers should be determined based on actual calculations. Regarding the method for determining the above-mentioned sizes, in a specific typical example, for example, it is known that the width of a single-sided sidewall is 0.09um, the square resistance of the N-well is 500Ω / sq, and the resistance of the metal silicide block is 20Ω / sq (the above three data depend on the specific process); when L = 50um (the length of the N-well resistor), W = 2um (the width of the N-well resistor), and the poly space is 0.25um, it is calculated that: R NW =500*(50 / 2)=12500Ω, R silicide =20*(50 / (0.25-0.09*2.0))=14285Ω, the resistance of the two in parallel is: R 并 =6666.5Ω; where R NW is the resistance of the N-well resistor, R silicide is the resistance of metal silicide, R 并 is the resistance of the N-well resistor and the metal silicide resistor in parallel. When the poly space is offset by 0.01 μm, the solution is:

[0098]

[0099] Of course, the above is only an example of calculating and determining the aforementioned structural layer. The values ​​of the aforementioned data may vary depending on the specific process. However, regardless of the process, the size of the corresponding structural layer can be calculated under the premise of knowing the corresponding data.

[0100] Please Figure 2 Based on the combination Figure 7 As a preferred embodiment, the process window electrical test structure 1 for the polysilicon gate spacing provided by the present invention includes a virtual test structure 12 on the basis of the formal test structure 11. The virtual test structure 12 is symmetrically arranged at the upper and lower positions of the formal test structure 11; the virtual test structure 12 has the same structure as the formal test structure 11. In the actual production process, the chip environment is dense. In order for the test structure of the present invention to be able to monitor during the production process and enable the electrical properties of the test structure to simulate the electrical properties of the chip environment, it is necessary to add a virtual test structure around the test structure to achieve a uniform pattern, thereby simulating the chip environment. Furthermore, the metal connection between the formal test structure 11 and the test pad must also be symmetrical to reduce the interference caused by the metal connection.

[0101] In a further embodiment of the present invention, a method for manufacturing a process window electrical test structure for a polysilicon gate spacing is provided, which is used to prepare the process window electrical test structure 1 for a polysilicon gate spacing described in the above embodiment. The method comprises:

[0102] The N-well resistor reference test structure 112 is formed simultaneously with other device structures in the functional area of ​​the wafer. Specifically, the N-well resistor reference test structure 112 includes: forming an N-well resistor 1123 in the active area within the dicing street; the N-well resistor 1123 is rectangular; and forming a first test lead 1124 and a second test lead 1125 at each end of the rectangular N-well resistor 1123.

[0103] The polysilicon gate resistor test structure 111 is fabricated in the cutting lane and arranged in parallel with the N-well resistor reference test structure 112. Specifically, the method includes: forming at least two long strips of polysilicon 1113 in the area above the N-well resistor 1123, wherein the two long strips of polysilicon 1113 are arranged in parallel; and forming a third test lead 1114 and a fourth test lead 1115 at both ends of the N-well resistor 1123 and the two long strips of polysilicon 1113, respectively, and the spacing between the two polysilicon 1113 is between the third test lead 1114 and the fourth test lead 1115. The fabrication of other test structures in the process window electrical test structure 1 for the polysilicon gate spacing, such as the fabrication of the isolation structure, the P-well region, etc., is also prepared together with the fabrication process of forming other device structures in the functional area of ​​the wafer. According to another embodiment of the present invention, a method for measuring a contact layer is also provided, and the method includes:

[0104] Detecting the resistance values ​​of the N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 in the process window electrical test structure 1 for the polysilicon gate spacing according to any of the aforementioned embodiments of the present invention;

[0105] Whether the metal silicide layer is formed between the two long strips of polysilicon is determined based on the resistance values ​​of the N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 .

[0106] If the resistance between first test pad 1121 and second test pad 1122 is greater than the resistance between third test pad 1111 and fourth test pad 1112, it indicates that a metal silicide layer has formed between the polysilicon layers. If the two values ​​are approximately the same, it indicates that the metal silicide layer has not formed properly. This enables non-destructive testing of whether metal silicide has formed between the polysilicon layers of a semiconductor device, significantly reducing costs and improving monitoring convenience.

[0107] According to another embodiment of the present invention, a process window electrical test component for polysilicon gate spacing is provided, comprising several process window electrical test structures 1 for polysilicon gate spacing as described in any of the aforementioned embodiments of the present invention, wherein the spacing (Polyspace) between the polysilicon is different in the several process window electrical test structures 1 for polysilicon gate spacing.

[0108] When developing new nodes and establishing new production lines, it is necessary to determine the minimum value of the spacing between two polysilicons at the process node. The process window electrical test component of the polysilicon gate spacing provided by the embodiment of the present invention is placed in the cutting path of the wafer, that is, a number of process window electrical test structures 1 of the polysilicon gate spacing are set in the cutting path, and the spacing between polysilicon in each process window electrical test structure of the polysilicon gate spacing is different; the resistance of each process window electrical test structure of the polysilicon gate spacing under different spacing between polysilicon is measured, and these test structures only have different spacing between polysilicon, and other structures and sizes are consistent. By collecting a large number of test results, a point-line distribution diagram of the measured resistance as the spacing between polysilicon in test structures of different sizes changes with resistance can be obtained, and the process minimum value and process window of the spacing between polysilicon can be determined from the point-line distribution diagram.

[0109] Figure 6 A flowchart of a method for determining a minimum spacing in a semiconductor process according to an embodiment of the present invention is provided. Figure 8 is a first relationship model between the spacing between polysilicon and the corresponding total resistance, wherein Figure 8 The first spacing is the spacing between polysilicon, the unit of the first spacing is um, and wafer center refers to the center position of the wafer.

[0110] in, Figure 8 The distance between polysilicon at the sudden resistance value in the dotted line graph is the minimum process distance. Figure 6 shown.

[0111] like Figure 6 As shown, a method for determining a minimum spacing of a semiconductor process provided in one embodiment of the present invention includes:

[0112] S1: Obtaining the spacing between polysilicon layers corresponding to the process window electrical test structure 1 of several polysilicon gate spacings as described in the aforementioned embodiment of the present invention.

[0113] S2: Measure the total resistance of the resistance of the process window electrical test structure 1 of each polysilicon gate spacing. Specifically, measure the resistance between the first test pad 1121 and the second test pad 1122, and the resistance between the third test pad 1111 and the fourth test pad 1112 in the process window electrical test structure of each polysilicon gate spacing to obtain the total resistance. As an example, the total resistance is expressed as Indicates. Among them, R 测 represents the resistance value of the polysilicon gate resistance test structure 111; R NW represents the resistance value of the N-well resistance reference test structure 112 .

[0114] S3: See Figure 8 According to the spacing between the polysilicon and the total resistance, a first relationship model between the spacing between the polysilicon and the corresponding total resistance is obtained.

[0115] In a typical example, the spacing between polysilicon and several total resistance values ​​at the center of the wafer in the test chip are obtained, and a distribution graph of the changes in the spacing between polysilicon is made. Data from multiple wafers are collected and a distribution graph is also made. Statistical analysis is performed on these data to make a fitted distribution curve.

[0116] Preferably, the above two steps may be repeated at different representative positions such as the center of the wafer or other positions in the wafer to obtain fitting curves at different positions.

[0117] In a typical example, taking the 0.18um technology node as an example, the spacing between polysilicon and several total resistance values ​​at the center of the wafer in the test chip are obtained. The total resistance is Get the distribution diagram of the change in the spacing between polysilicon, collect data from multiple wafers, and also make a distribution diagram, perform statistical analysis on these data, and make a fitting distribution curve. According to the distribution curve, as the spacing between polysilicon decreases, the change curve of the total resistance should be a curve that is flat first and then rises. Repeat the above two steps at other locations on the wafer, and you will get fitting curves at different locations, such as Figure 8 As shown. Figure 8It can be seen that: when the spacing between polysilicon is large, excluding the possibility of other process fluctuations, the total resistance of the area is a constant value due to the normal growth of metal silicide in the potential metal silicide-free area; as the spacing between polysilicon increases, the proportion of metal silicide resistance in the middle increases, so the measured total resistance will be smaller, and as the spacing between polysilicon decreases, the measured resistance will increase in a nearly linear form until the spacing between polysilicon decreases to a certain extent, at which point the rate of increase in the measured resistance will slowly slow down until it reaches a level. This is because when the spacing between polysilicon is very small, the potential metal silicide-free area cannot form a uniform metal silicide layer, or even no metal silicide layer. At this time, continuing to reduce the spacing between polysilicon will not change the total resistance much.

[0118] S4: Determine the minimum spacing value based on the first relationship model. Preferably, if the spacing between polysilicon crystals under a certain condition is within a 10% deviation range of the corresponding curve point, the spacing between polysilicon crystals is determined to be the minimum process spacing (minimum poly space). Figure 8 As shown, the minimum process spacing is 0.2um.

[0119] Preferably, slices of the process window electrical test structure 1 of the polysilicon gate spacing can also be obtained. According to the slices and the first relationship model, the value of the minimum spacing is determined. In this embodiment, the slicing results are compared with the electrical test results to ensure the accuracy of the electrical test during the research and development stage of developing new nodes and establishing new production lines. After determining the minimum process spacing, process monitoring of metal silicide can be achieved without slicing in the subsequent production stage, thereby greatly reducing the monitoring cost while achieving the determination of the minimum process spacing and metal silicide process monitoring. At the same time, this embodiment further verifies the accuracy of the minimum process spacing determined by the solution of the present invention through slicing. Therefore, the technical solution provided by this embodiment reduces experimental errors and improves accuracy.

[0120] In summary, the process window electrical test structure of the polysilicon gate spacing provided by the present invention is provided with a test structure including a polysilicon gate resistance test structure and an N-well resistance reference test structure, wherein, compared with the N-well resistance reference test structure, the polysilicon gate resistance test structure is provided with at least two long strips of polysilicon above the N-well resistance, so that in the subsequent process, the N-well resistance of the N-well resistance reference test structure will be completely covered with a metal silicide barrier layer (SAB, Salicide-block), resulting in the area on its N-well resistance being a metal silicide-free area; whereas in the polysilicon gate resistance test structure, the area covered by polysilicon will not form a metal silicide. The resistance of this region is equivalent to the resistance of the N-well resistor covered by the metal silicide barrier layer. Only the region between the two polysilicon strips is not covered by the metal silicide barrier layer, where metal silicide may form. Therefore, only the region between the two polysilicon strips may affect the resistance of the polysilicon gate resistance test structure. The polysilicon gate resistance test structure and the N-well resistance reference test structure are respectively connected via a pad and a pad lead-out terminal. By testing the resistance between the polysilicon gate resistance test structure and the N-well resistance reference test structure and comparing the resistances between the two, the purpose of non-destructive testing of the metal silicide preparation process between polysilicon gates can be achieved using electrical testing methods. This makes it possible to monitor whether metal silicide has formed between two polysilicon strips without slicing, reducing costs, improving monitoring convenience, and preventing wafer damage.

[0121] Furthermore, a method for determining the minimum spacing of a semiconductor process is provided. The method comprises setting a plurality of process window electrical test structures for polysilicon gate spacing, and setting the spacing between polysilicon in the polysilicon gate resistance test structures corresponding to the process window electrical test structures for the polysilicon gate spacing to different sizes. After obtaining the spacing between the plurality of polysilicon and the plurality of total resistance values ​​corresponding to the process window electrical test structures for the polysilicon gate spacing, a first relationship model for the variation of the spacing between the polysilicon is established based on the spacing between the plurality of polysilicon and the plurality of total resistance values. The value of the minimum spacing can be determined based on the first relationship model. Thus, when developing a new node or establishing a new production line, the method provided by the present invention can determine the minimum spacing at the process node, providing a reference for monitoring the spacing between polysilicon in subsequent production stages.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A process window electrical test structure for a polysilicon gate spacing, wherein the process window electrical test structure is placed in a dicing street of a wafer, characterized in that: At least one formal test structure is included, the formal test structure includes an N-well resistance reference test structure and a polysilicon gate resistance test structure, the N-well resistance reference test structure and the polysilicon gate resistance test structure are arranged in parallel up and down in the cutting street, the N-well resistance reference test structure is provided with a first test pad and a second test pad, the polysilicon gate resistance test structure is provided with a third test pad and a fourth test pad, the first test pad, the third test pad, the second test pad and the fourth test pad are staggered along the cutting street direction, wherein: The N-well resistance reference test structure includes: An N-well resistor in the active area, the N-well resistor being rectangular, and having a first test lead and a second test lead located at both ends of the rectangular N-well resistor, the first test lead and the second test lead being electrically connected to the first test pad and the second test pad, respectively; wherein a surface of the N-well resistor is covered with a metal silicide barrier layer; The polysilicon gate resistance test structure includes: An N-well resistor reference test structure and at least two long strips of polysilicon located above the N-well resistor and a third test lead and a fourth test lead located at both ends of the N-well resistor and the two long strips of polysilicon. The two long strips of polysilicon are arranged parallel to each other, the spacing between the two polysilicons is between the third test lead and the fourth test lead, and the outer boundaries of the two polysilicons are flush with the boundaries of the metal silicide barrier layer. The third test lead and the fourth test lead are electrically connected to the third test pad and the fourth test pad, respectively.

2. The process window electrical test structure for polysilicon gate spacing according to claim 1, wherein: The two long strip-shaped polysilicon sidewalls are both formed with side walls, and the distance between the two polysilicon strips is the distance between the side walls.

3. The process window electrical test structure for polysilicon gate spacing according to claim 1, wherein: The test structure further includes a dummy test structure, which is symmetrically arranged above and below the formal test structure; the dummy test structure has the same structure as the formal test structure.

4. A method for manufacturing a process window electrical test structure for a polysilicon gate spacing, for manufacturing the process window electrical test structure for a polysilicon gate spacing according to claim 1, characterized in that: include: Forming the N-well resistance reference test structure includes: forming an N-well resistor in an active area within the cutting street, wherein the N-well resistor is rectangular; forming first and second test leads at both ends of the rectangular N-well resistor respectively; The polysilicon gate resistance test structure is fabricated in the cutting lane and arranged in parallel with the N-well resistance reference test structure, including: At least two long strips of polysilicon are formed in the area above the N-well resistor; the two long strips of polysilicon are arranged in parallel; A third test lead-in terminal and a fourth test lead-in terminal are formed at both ends of the N-well resistor and the two long strips of polysilicon respectively. The distance between the two strips of polysilicon is located between the third test lead-in terminal and the fourth test lead-in terminal.

5. A method for measuring a contact layer, characterized in that: include: Detecting the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure in the process window electrical test structure for the polysilicon gate spacing according to any one of claims 1 to 3; Whether the metal silicide is formed between the two long strips of polysilicon is determined according to the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure.

6. A process window electrical test component for polysilicon gate spacing, characterized in that: It comprises a plurality of process window electrical test structures of polysilicon gate spacing as described in any one of claims 1 to 3, wherein the spacings between the polysilicon are different in the process window electrical test structures of the plurality of polysilicon gate spacing.

7. A method for determining the minimum spacing of a semiconductor process, characterized in that: include: Obtaining the spacing between polysilicon layers corresponding to the process window electrical test structures of the plurality of polysilicon gate spacings as claimed in claim 6; Measuring the total resistance of the process window electrical test structure for each polysilicon gate spacing; Obtaining a first relationship model between the spacing between the polysilicon and the corresponding total resistance according to the spacing between the polysilicon and the total resistance; According to the first relationship model, a value of a minimum distance is determined.

8. The method for determining the minimum spacing of a semiconductor process according to claim 7, wherein: The method further includes: Obtaining slices of the process window electrical test structures of the plurality of polysilicon gate spacings; The value of the minimum distance is determined according to the plurality of slices and the first relationship model.

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