A rail-to-rail input bias circuit

Abstract

The present application relates to a rail-to-rail input bias circuit, which is used to provide a bias voltage for the input stage of a rail-to-rail input operational amplifier; the circuit includes a detection module and a bias module; the detection module is used to generate a selection control signal according to a differential input amplitude and output it to the bias module; the differential input amplitude is the voltage difference between an external input signal and an output signal of the rail-to-rail input operational amplifier; the bias module is used to control the input of an external input signal or a common-mode input signal in response to the selection control signal and transmit the generated bias voltage to the input stage of the rail-to-rail input operational amplifier; wherein, when the differential input amplitude is greater than a detection threshold, the bias module inputs a common-mode input signal; when the differential input amplitude is less than or equal to the detection threshold, the bias module inputs an external input signal; the rail-to-rail input bias circuit of the present application can avoid the influence of the offset ripple at the output end on the bias current, and improve the common-mode rejection ratio of the rail-to-rail input operational amplifier.

Description

Technical Field

[0001] The present application relates to the field of circuit design, and in particular to a rail-to-rail input bias circuit. Background Art

[0002] The rail-to-rail input operational amplifier (Rail-to-Rail Input Operational Amplifier) ​​uses a rail-to-rail input stage composed of a complementary differential input pair tube (Complementary Differential Pair). Its input voltage range can cover the positive and negative power supply voltages, thereby allowing a wider input signal range. The rail-to-rail input operational amplifier can dynamically adjust the bias current of the complementary differential input pair tube according to the common-mode input signal through the rail-to-rail input bias circuit to maintain the transconductance of the operational amplifier constant. In practice, the operational amplifier has an output offset, and the output offset can be reduced by using chopping technology. However, when using chopping technology, the offset ripple generated at the output of the rail-to-rail input operational amplifier will affect the traditional input bias circuit, causing the absolute value of the offset voltage to change with the working phase of chopping, so that the output offset cannot be completely offset. Summary of the invention

[0003] In view of this, the present application proposes a rail-to-rail input bias circuit, which can avoid the influence of the offset ripple generated at the output end on the rail-to-rail input bias circuit when using the chopping technology, and improve the common mode rejection ratio of the rail-to-rail input operational amplifier.

[0004] According to one aspect of the present application, a rail-to-rail input bias circuit is provided, which is used to provide a bias voltage for the input stage of a rail-to-rail input operational amplifier; the rail-to-rail input bias circuit includes a detection module and a bias module; the detection module is used to generate a selection control signal according to a differential input amplitude and output it to the bias module; the differential input amplitude is the voltage difference between an external input signal and an output signal of the rail-to-rail input operational amplifier; the bias module is used to control the input of the external input signal or the common-mode input signal in response to the selection control signal, and transmit the bias voltage generated according to the input external input signal or the common-mode input signal to the input stage of the rail-to-rail input operational amplifier; the common-mode input signal is the sum of the external input signal and the output signal divided by 2; wherein, when the differential input amplitude is greater than a detection threshold, the bias module inputs the common-mode input signal in response to the selection control signal; when the differential input amplitude is less than or equal to the detection threshold, the bias module inputs the external input signal in response to the selection control signal.

[0005] In a possible implementation, the bias module includes a multiplexer, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a third PMOS tube; the control end of the multiplexer inputs the selection control signal; the first input end of the multiplexer inputs the common-mode input signal; the second input end of the multiplexer inputs the external input signal; the output end of the multiplexer is connected to the gate of the second NMOS tube, and the multiplexer controls the common-mode input signal at the first input end of the multiplexer or the external input signal at the second input end to input the gate of the second NMOS tube through the output end in response to the received selection control signal; the source of the first NMOS tube, the source of the second NMOS tube and the drain of the third NMOS tube are connected; the first NMOS The drain of the first PMOS tube, the drain of the second PMOS tube and the gate of the first PMOS tube are connected; the drain of the second NMOS tube, the drain of the second PMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube are connected; the drain of the third PMOS tube, the drain of the fourth NMOS tube and the gate of the fourth NMOS tube are connected; the gate of the first NMOS tube is connected to the P / N switching threshold voltage; the gate of the third NMOS tube is connected to the first voltage; the source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to the positive power supply voltage of the rail-to-rail input operational amplifier; the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the negative power supply voltage of the rail-to-rail input operational amplifier; the gate of the first PMOS tube and the gate of the fourth NMOS tube are used to output the bias voltage.

[0006] In a possible implementation, the detection module includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube and an OR gate; the gate of the tenth NMOS tube inputs the external input signal; the gate of the eleventh NMOS tube inputs the output signal; the source of the tenth NMOS tube, the source of the eleventh NMOS tube and the drain of the seventh NMOS tube are connected; the drain of the tenth NMOS tube, the drain of the sixth PMOS tube, the gate of the sixth PMOS tube and the gate of the eighth PMOS tube are connected; the drain of the eleventh NMOS tube, the drain of the seventh PMOS tube, the gate of the seventh PMOS tube and the ninth PMOS tube are connected The gate of the seventh NMOS tube, the gate of the eighth NMOS tube and the gate of the ninth NMOS tube are connected and connected to a second voltage; the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the eighth PMOS tube and the source of the ninth PMOS tube are connected to the positive power supply voltage of the rail-to-rail input operational amplifier; the source of the seventh NMOS tube, the source of the eighth NMOS tube and the source of the ninth NMOS tube are connected to the negative power supply voltage of the rail-to-rail input operational amplifier; the drain of the eighth NMOS tube, the drain of the eighth PMOS tube and the first input end of the OR gate are connected; the drain of the ninth NMOS tube, the drain of the ninth PMOS tube and the second input end of the OR gate are connected; the output end of the OR gate outputs the selection control signal.

[0007] In a possible implementation, the input stage of the rail-to-rail input operational amplifier includes a first input NMOS tube, a second input NMOS tube, a first input PMOS tube, a second input PMOS tube, a fifth NMOS tube and a fourth PMOS tube; the gate of the first input NMOS tube is connected to the gate of the first input PMOS tube to form the positive input terminal of the rail-to-rail input operational amplifier; the gate of the second input NMOS tube is connected to the gate of the second input PMOS tube to form the negative input terminal of the rail-to-rail input operational amplifier; the source of the first input NMOS tube, the second input The source of the first input NMOS tube is connected to the drain of the fifth NMOS tube; the source of the first input PMOS tube, the source of the second input PMOS tube and the drain of the fourth PMOS tube are connected; the gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube to receive the bias voltage; the gate of the fourth PMOS tube is connected to the gate of the first PMOS tube to receive the bias voltage; the source of the fourth PMOS tube is connected to the positive power supply voltage of the rail-to-rail input operational amplifier; the source of the fifth NMOS tube is connected to the negative power supply voltage of the rail-to-rail input operational amplifier.

[0008] In a possible implementation, the output end of the rail-to-rail input operational amplifier is connected to the positive input end or the negative input end of the rail-to-rail input operational amplifier; wherein, when the output end of the rail-to-rail input operational amplifier is connected to the negative input end of the rail-to-rail input operational amplifier, the external input signal is input to the positive input end of the rail-to-rail input operational amplifier; when the output end of the rail-to-rail input operational amplifier is connected to the positive input end of the rail-to-rail input operational amplifier, the external input signal is input to the negative input end of the rail-to-rail input operational amplifier.

[0009] In one possible implementation, when the differential input amplitude is greater than the detection threshold, the selection control signal is at a high level, and the multiplexer inputs the common-mode input signal to the gate of the second NMOS tube in response to the selection control signal; when the differential input amplitude is less than or equal to the detection threshold, the selection control signal is at a low level, and the multiplexer inputs the external input signal to the gate of the second NMOS tube in response to the selection control signal.

[0010] In a possible implementation, the detection threshold is adjusted and set according to at least one of the width-to-length ratio of the seventh NMOS tube, the width-to-length ratio of the eighth NMOS tube, the width-to-length ratio of the ninth NMOS tube, the width-to-length ratio of the sixth PMOS tube, the width-to-length ratio of the seventh PMOS tube, the width-to-length ratio of the eighth PMOS tube, or the width-to-length ratio of the ninth PMOS tube.

[0011] The detection module of the rail-to-rail input bias circuit of the present application can automatically detect the differential input amplitude of the rail-to-rail input operational amplifier and generate a selection control signal. When the differential input amplitude exceeds the detection threshold, the bias module can respond to the selection control signal to provide a bias voltage and a bias current according to the common-mode input signal of the rail-to-rail input operational amplifier, thereby avoiding input transconductance changes, so that the rail-to-rail input operational amplifier has a rail-to-rail input range when responding to large-amplitude transient inputs; when the differential input amplitude is not greater than the detection threshold, the bias module can respond to the selection control signal to provide a bias voltage and a bias current according to the external input signal of the rail-to-rail input operational amplifier, decouple the bias current from the output signal, and directly bias it by the external input signal, thereby avoiding the offset ripple generated at the output end when using the chopping technology to cause the bias current to change, so that the output offset does not change with the common-mode input signal, and the common-mode rejection ratio can be significantly improved.

[0012] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0014] Figure 1 A schematic diagram showing the use of an operational amplifier to drive a switched capacitor circuit.

[0015] Figure 2 A circuit structure diagram of a non-rail-to-rail input operational amplifier is shown.

[0016] Figure 3 A schematic diagram of the circuit structure of a rail-to-rail input operational amplifier and a traditional rail-to-rail input bias circuit is shown.

[0017] Figure 4 A schematic structural diagram of a rail-to-rail input bias circuit according to an embodiment of the present application is shown.

[0018] Figure 5 A circuit structure diagram of a bias module of a rail-to-rail input bias circuit and a circuit structure diagram of a rail-to-rail input operational amplifier according to an embodiment of the present application are shown.

[0019] Figure 6 A circuit structure schematic diagram of a detection module of a rail-to-rail input bias circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0021] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0022] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0023] The input signal is a low-frequency continuous-time signal, and the output is used to drive a discrete-time switched capacitor circuit, which is a typical application scenario of an operational amplifier. When the operational amplifier is loaded with a switched capacitor circuit, the capacitance of the switched capacitor circuit at the output of the operational amplifier switches, which will cause a transient pull-down signal or a transient overshoot signal at the output of the operational amplifier. The transient signal at the output controls the input of the operational amplifier through a feedback loop, providing a transient charging and discharging path for the switched capacitor circuit. Figure 1 A schematic diagram showing the use of an operational amplifier to drive a switched capacitor circuit is shown in FIG. Figure 1 As shown, the input signal of the positive input terminal of the operational amplifier is a low-frequency signal, and the output terminal is connected to the negative input terminal through a feedback network. When the switch PH1 is turned on and PH2 is turned off, the output terminal of the operational amplifier is connected to the input terminal of the switched capacitor circuit. If the voltage of the left plate of the capacitor in the switched capacitor circuit is lower than the voltage of the output terminal of the operational amplifier, the voltage of the output terminal of the operational amplifier will be pulled down, and a transient pull-down signal will be generated at the output terminal of the operational amplifier. The transient pull-down signal at the output terminal of the operational amplifier is fed back to the negative input terminal of the operational amplifier through the feedback network, so that the negative input terminal of the operational amplifier also generates a transient pull-down signal. The operational amplifier can charge the capacitor until the voltage of the left plate of the capacitor is the same as the voltage at the output terminal of the operational amplifier. After a certain settling time, the differential input voltage of the operational amplifier is established to near 0, that is, the voltage of the signal VINP at the positive input terminal is approximately equal to the voltage of the signal VINN at the negative input terminal, and the output terminal voltage is established to near the steady-state value. Since the frequency of the external input signal VIN is low and almost unchanged, the steady-state value of the voltage at the output terminal of the operational amplifier is consistent with the initial value of the voltage before the transient pull-down signal arrives.

[0024] A non-rail-to-rail input operational amplifier is an operational amplifier whose input voltage range cannot fully reach the positive and negative voltages of the power supply. Conventional non-rail-to-rail input operational amplifiers use a differential input pair consisting of a PMOS tube or a differential input pair consisting of an NMOS tube to input differential signals. Figure 2 A circuit diagram of a non-rail-to-rail input operational amplifier is shown in FIG. Figure 2 As shown, the non-rail-to-rail input operational amplifier uses an NMOS differential input pair tube as the input stage, a low-frequency signal VIN is input to the positive input terminal, and the output terminal is connected to the negative input terminal to form a feedback loop. If the feedback coefficient is large, such as unity gain negative feedback, the feedback coefficient is 1, and the signal VO at the output terminal will be fully fed back to the negative input terminal. When the non-rail-to-rail input operational amplifier load switch capacitor circuit is used, if the transient pull-down signal or transient overshoot signal generated at the output terminal when the capacitor is switched is large in amplitude, although the low-frequency signal VIN input to the non-feedback terminal (i.e., the positive input terminal) is almost unchanged, the large transient signal jump at the feedback input terminal (i.e., the negative input terminal) will still cause a significant change in the common-mode input signal; wherein, the common-mode input signal VCM = (VINP + VINN) / 2, VINP is the input signal at the positive input terminal, and VINN is the input signal at the negative input terminal. The common-mode input range of the non-rail-to-rail input operational amplifier is limited, and the drain-source voltage of the bias current tube MN1 of its differential input pair tube changes with the common-mode input signal, and its output impedance is limited. Figure 2 For the NMOS differential input pair in the circuit, when the common-mode input signal jumps downward significantly, the bias current ITAILN provided by its bias current tube MN1 decreases. When the drain-source voltage of MN1 is compressed to less than the overdrive voltage, MN1 enters the linear region, and the bias current will be more attenuated, which means that the input transconductance will be greatly attenuated. The input transconductance indicates the rate of change of the output current when the input signal voltage of the operational amplifier changes, which can reflect the amplifier's amplification performance. The significant attenuation of the input transconductance will cause the bandwidth and gain of the operational amplifier to drop significantly, and the process of the operational amplifier establishing a steady state will be significantly slowed down.

[0025] Therefore, a rail-to-rail input stage consisting of a complementary differential input pair is generally used in CMOS-based operational amplifiers. The rail-to-rail input stage has a rail-to-rail common-mode input range and can achieve an input swing from the negative power rail to the positive power rail. This operational amplifier whose input voltage range can approach or reach the positive and negative voltages of the power supply is called a rail-to-rail input operational amplifier. Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a rail-to-rail input operational amplifier and a conventional rail-to-rail input bias circuit, wherein the rail-to-rail input bias circuit is used to provide a bias voltage and a bias current for the input stage of the rail-to-rail input operational amplifier. Figure 3As shown, the input stage of the rail-to-rail input operational amplifier is realized by a complementary differential input pair consisting of an NMOS differential input pair and a PMOS differential input pair. The input voltage of the positive input terminal of the rail-to-rail input operational amplifier is VINP, and the input voltage of the negative input terminal is VINN. When the common-mode input voltage is close to the positive power rail VDD, the NMOS differential input pair is turned on, and the input transconductance is completely provided by the bias current ITAILN of the NMOS differential input pair, and the bias current ITAILP of the PMOS differential input pair is 0; when the common-mode input voltage is close to the negative power rail VSS, the PMOS differential input pair is turned on, and the input transconductance is completely provided by the bias current ITAILP of the PMOS differential input pair, and the bias current ITAILN of the NMOS differential input pair is 0; this ensures that within the entire rail-to-rail input range, at least one differential input pair is turned on to provide input transconductance. When the common-mode input voltage is at the middle of the power rail, that is, when the common-mode input voltage is close to (VDD-VSS) / 2, the NMOS differential input pair and the PMOS differential input pair are turned on at the same time, and the NMOS differential input pair and the PMOS differential input pair need to provide half of the input transconductance respectively. ITAILN and ITAILP are usually biased to half of the NMOS differential input pair or the PMOS differential input pair when they are turned on alone (that is, the NMOS differential input pair and the PMOS differential input pair are in the subthreshold region) or 1 / 4 (that is, the NMOS differential input pair and the PMOS differential input pair are in the saturation region), so that the equivalent input transconductance is the same as the input transconductance when the NMOS differential input pair or the PMOS differential input pair is turned on alone.

[0026] The rail-to-rail input operational amplifier can dynamically adjust the bias current of the NMOS differential input pair and the PMOS differential input pair according to the common-mode input signal through the rail-to-rail input bias circuit to maintain the equivalent input transconductance provided by the differential input pair approximately constant. When the common-mode input signal jumps downward, the rail-to-rail input bias circuit can increase the bias current ITAILP of the PMOS differential input pair and reduce the bias current ITAILN of the NMOS differential input pair; when the common-mode input signal jumps upward, the rail-to-rail input bias circuit can reduce the bias current ITAILP of the PMOS differential input pair and increase the bias current ITAILN of the NMOS differential input pair; in this way, the equivalent input transconductance provided by the differential input pair can be kept approximately constant over the entire rail-to-rail input range. Figure 3A traditional rail-to-rail input bias circuit is shown, which consists of a differential input pair of transistors composed of MN1 and MN2 and a current mirror. One end of the differential input pair (i.e., the gate of MN1) inputs the P / N switching threshold voltage Vr, and Vr is generally equal to (VDD - VSS) / 2; the other end of the differential input pair (i.e., the gate of MN2) is connected to the common-mode input voltage VIN_CM of the rail-to-rail input operational amplifier, and VIN_CM = (VINP + VINN) / 2. This rail-to-rail input bias circuit can deliver the generated bias voltages (i.e., the gate voltages of MP1 and MN4) to the gate of MP4 and the gate of MN5 respectively, so that MP4 can generate the bias current ITAILP and MN5 can generate the bias current ITAILN, thereby providing bias currents for the input stage of the rail-to-rail input operational amplifier. When Vr = VIN_CM, the bias currents provided by the rail-to-rail input bias circuit are evenly divided by the NMOS differential input pair of transistors and the PMOS differential input pair of transistors, that is, ITAILN = ITAILP, and at this time both the NMOS differential input pair of transistors and the PMOS differential input pair of transistors are conducting; when VIN_CM increases to exceed Vr, the bias current provided by the rail-to-rail input bias circuit mainly flows through the NMOS differential input pair of transistors, and the bias current flowing through the PMOS differential input pair of transistors decreases, that is, ITAILN > ITAILP, and when VIN_CM approaches the positive power supply rail VDD, the bias current all flows through the NMOS differential input pair of transistors; when VIN_CM decreases to be lower than Vr, the bias current provided by the rail-to-rail input bias circuit mainly flows through the PMOS differential input pair of transistors, and the bias current flowing through the NMOS differential input pair of transistors decreases, that is, ITAILN < ITAILP, and when VIN_CM approaches the negative power supply rail VSS, the bias current all flows through the PMOS differential input pair of transistors.

[0027] Operational amplifiers are generally used in negative feedback loops, for example Figure 3 The rail-to-rail input operational amplifier shown is configured in the unity-gain negative feedback mode. One end of the input of this operational amplifier is connected to the input signal VIN, and the other end is connected to the output signal VO of the output terminal. This means that the common-mode input voltage of the operational amplifier is related to the output, that is, the bias currents of the NMOS differential input pair of transistors and the PMOS differential input pair of transistors are related to the output.

[0028] Although the rail-to-rail input stage expands the common-mode input range, in practice, problems such as output offset and 1 / f noise exist in operational amplifiers. To reduce the output offset, operational amplifiers usually use chopping techniques. Conventional chopping techniques are achieved by adding chopping switches in operational amplifiers, such as Figure 3As shown, a chopping switch chop1 is added to the input end of the rail-to-rail input operational amplifier, and chopping switches chop2 and chop3 are added to the load end. The chopping operation is divided into two phases. When the first phase is working, one side of each chopping switch is turned on; when the second phase is working, the other side of each chopping switch is turned on. For example, for chop1, when the first phase is working, the positive input end of the rail-to-rail input operational amplifier is connected to the input signal VIN through chop1, and the negative input end is connected to the output end through chop1; when the second phase is working, the positive input end is connected to the output end through chop1, and the negative input end is connected to the input signal VIN through chop1. Since the input signal VIN undergoes two stages of chopping switch switching, the polarity of the input signal changes twice, and the signal seen at the output end does not change; the main offset voltage only passes through one stage of chopping switch (chop2 or chop3), so ideally, the offset output has the same magnitude and opposite polarity in the two phases of chopping. After chopping, the output of the operational amplifier appears as a signal that periodically superimposes positive offset output and negative offset output, which means that in the time domain, the output offset voltage can be offset on average.

[0029] The input signal VIN of the operational amplifier is generally a DC or slowly changing signal. When the common-mode input voltage is at one end of the power rail and only one differential input pair is turned on at the input stage of the operational amplifier, although the output of the operational amplifier will generate offset ripple due to chopping, causing the common-mode input voltage to change, the differential input pair is in a unilateral overdrive state, and the bias current flows completely through the NMOS differential input pair or completely through the PMOS differential input pair. The bias current of the differential input pair is not affected by the common-mode input voltage. Therefore, when the common-mode input voltage is near the power rail, the static operating point of the circuit will not change with chopping, that is, the absolute value of the offset voltage of the operational amplifier will not change with chopping, and chopping can normally offset the output offset. When the common-mode input voltage is in the middle of the power rail, the NMOS differential input pair and the PMOS differential input pair of the operational amplifier input stage are both turned on. When the chopping technique is used, the offset ripple at the output of the operational amplifier will cause the common-mode input voltage to change, further causing the bias current of the NMOS differential input pair and the PMOS differential input pair to change. The bias current of the NMOS differential input pair and the PMOS differential input pair changes in the two working phases of chopping, and their static operating points will change in the two working phases of chopping. The output offset of the operational amplifier is related to its static operating point, which means that the absolute value of the offset voltage of the operational amplifier is not equal in the two working phases, and chopping leaks, that is, the output offset cannot be completely offset in the sense of time averaging.

[0030] As mentioned above, when the operational amplifier turns on chopping, the output offset can be offset when the common-mode input voltage is close to the power rail; when the common-mode input voltage is in the middle of the power rail, the output offset cannot be completely offset, and there is residual output offset. In other words, the output offset changes significantly with the change of the common-mode input voltage, and the ratio of the output offset change with the common-mode input voltage is called the common-mode rejection ratio (CMRR). Therefore, if Figure 3 In the traditional rail-to-rail input bias circuit shown in , when the operational amplifier is configured in negative feedback mode, due to the coupling of the output signal for bias current judgment, when the operational amplifier turns on chopping, when the common-mode input voltage is in the middle of the power rail, the output offset cannot be fully offset and the common-mode rejection ratio deteriorates significantly.

[0031] In view of this, an embodiment of the present application proposes a rail-to-rail input bias circuit, which can avoid the influence of the offset ripple generated when using the chopping technology on the bias current provided by the rail-to-rail input bias circuit, and improve the common mode rejection ratio of the rail-to-rail input operational amplifier.

[0032] Figure 4 FIG. 1 is a schematic diagram showing a structure of a rail-to-rail input bias circuit according to an embodiment of the present application. The rail-to-rail input bias circuit can be used to provide a bias voltage and a bias current for an input stage of a rail-to-rail input operational amplifier. Figure 4 As shown, the circuit may include a detection module 401 and a bias module 402 .

[0033] The detection module 401 is used to generate a selection control signal according to the differential input amplitude and output it to the bias module 402; the differential input amplitude is the voltage difference between the external input signal and the output signal of the rail-to-rail input operational amplifier.

[0034] The bias module 402 is used to control the input of the external input signal or the common-mode input signal in response to the selection control signal, and transmit the bias voltage generated according to the input external input signal or the common-mode input signal to the input stage of the rail-to-rail input operational amplifier; the bias current is generated according to the bias voltage; the common-mode input signal is the sum of the external input signal and the output signal divided by 2; wherein, when the differential input amplitude is greater than the detection threshold, the bias module 402 inputs the common-mode input signal in response to the selection control signal; when the differential input amplitude is less than or equal to the detection threshold, the bias module 402 inputs the external input signal in response to the selection control signal.

[0035] The detection module of the rail-to-rail input bias circuit of the embodiment of the present application can automatically detect the differential input amplitude of the rail-to-rail input operational amplifier and generate a selection control signal. When the differential input amplitude exceeds the detection threshold, the bias module can respond to the selection control signal to provide a bias voltage and a bias current according to the common-mode input signal of the rail-to-rail input operational amplifier, thereby avoiding input transconductance changes, so that the rail-to-rail input operational amplifier has a rail-to-rail input range when responding to large-amplitude transient inputs; when the differential input amplitude is not greater than the detection threshold, the bias module can respond to the selection control signal to provide a bias voltage and a bias current according to the external input signal of the rail-to-rail input operational amplifier, decouple the bias current from the output signal, and directly bias it by the external input signal, thereby avoiding the offset ripple generated at the output end when using the chopping technology to cause the bias current to change, so that the output offset does not change with the common-mode input signal, and the common-mode rejection ratio can be significantly improved.

[0036] For example, the rail-to-rail input bias circuit of the embodiment of the present application can be used for Figure 3 The NMOS differential input pair and the PMOS differential input pair of the input stage of the rail-to-rail input operational amplifier shown provide bias current.

[0037] Figure 5 A circuit structure diagram of a bias module of a rail-to-rail input bias circuit and a circuit structure diagram of a rail-to-rail input operational amplifier according to an embodiment of the present application are shown.

[0038] Figure 5 The rail-to-rail input op amp shown above Figure 3 The circuit structure of the rail-to-rail input operational amplifier shown in FIG. Figure 5 As shown, the input stage of the rail-to-rail input operational amplifier may include a first input NMOS tube MN_in1, a second input NMOS tube MN_in2, a first input PMOS tube MP_in1, a second input PMOS tube MP_in2, a fifth NMOS tube MN5 and a fourth PMOS tube MP4; the gate of MN_in1 is connected to the gate of MP_in1, forming the positive input terminal of the rail-to-rail input operational amplifier; the gate of MN_in2 is connected to the gate of MP_in2, forming the negative input terminal of the rail-to-rail input operational amplifier; the source of MN_in1, the source of MN_in2 and the drain of MN5 are connected; the source of MP_in1, the source of MP_in2 and the drain of MP4 are connected; the source of MP4 is connected to the positive power supply voltage VDD of the rail-to-rail input operational amplifier; the source of MN5 is connected to the negative power supply voltage VSS of the rail-to-rail input operational amplifier. MN_in1 and MN_in2 form an NMOS differential input pair tube, MP_in1 and MP_in2 form a PMOS differential input pair tube, and the NMOS differential input pair tube and the PMOS differential input pair tube form a complementary differential input pair tube.

[0039] The output end of the rail-to-rail input operational amplifier can be connected to the positive input end or the negative input end of the rail-to-rail input operational amplifier. When the rail-to-rail input operational amplifier uses the chopping technology, in the first working phase of chopping, the positive input end of the rail-to-rail input operational amplifier can input the external input signal VIN, and the output end of the rail-to-rail input operational amplifier can be connected to the negative input end, that is, the output signal VO of the output end of the rail-to-rail input operational amplifier can be fed back to the negative input end; in the second working phase of chopping, the negative input end of the rail-to-rail input operational amplifier can input the external input signal VIN, and the output end of the rail-to-rail input operational amplifier can be connected to the positive input end, that is, the output signal VO of the output end of the rail-to-rail input operational amplifier can be fed back to the positive input end. The external input signal VIN can be a low-frequency continuous-time signal.

[0040] Figure 5The bias module of the rail-to-rail input bias circuit shown may include a multiplexer (MUX), a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a first PMOS tube MP1, a second PMOS tube MP2 and a third PMOS tube MP3.

[0041] like Figure 5 As shown, the control end of MUX inputs the selection control signal SW; the first input end of MUX inputs the common mode input signal VIN_CM, wherein VIN_CM=(VIN+VO) / 2; the second input end of MUX inputs the external input signal VIN; the output end of MUX is connected to the gate of MN2, and MUX controls the common mode input signal VIN_CM of the first input end or the external input signal VIN of the second input end to be input to the gate of MN2 through the output end in response to the received selection control signal SW; the source of MN1, the source of MN2 and the drain of MN3 are connected; The drain of MN1, the drain of MP1 and the gate of MP1 are connected; the drain of MN2, the drain of MP2, the gate of MP2 and the gate of MP3 are connected; the drain of MP3, the drain of MN4 and the gate of MN4 are connected; the gate of MN1 is connected to the P / N switching threshold voltage Vr, which can be equal to (VDD-VSS) / 2; the gate of MN3 is connected to the first voltage vbn_1, and the value of vbn_1 can be set by those skilled in the art according to actual needs; the source of MP1, the source of MP2 and the source of MP3 are connected to VDD; the source of MN3 and the source of MN4 are connected to VSS. The gate of MN4 is connected to the gate of MN5 in the rail-to-rail input operational amplifier input stage; the gate of MP1 is connected to the gate of MP4 in the rail-to-rail input operational amplifier input stage. The bias module can generate a bias voltage and output the bias voltage to the gate of MP4 through the gate of MP1, and output the bias voltage to the gate of MN5 through the gate of MN4. MP4 can generate a bias current ITAILP according to the bias voltage received by the gate, and MN5 can generate a bias current ITAILN according to the bias voltage received by the gate. In this way, the bias module can provide a bias current ITAILN for the NMOS differential input pair in the input stage of the rail-to-rail input operational amplifier, and provide a bias current ITAILP for the PMOS differential input pair in the input stage of the rail-to-rail input operational amplifier.

[0042] Figure 6 A circuit structure schematic diagram of a detection module of a rail-to-rail input bias circuit according to an embodiment of the present application is shown. Figure 6The detection module of the rail-to-rail input bias circuit shown may include a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh NMOS tube MN11, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9 and an OR gate OR.

[0043] like Figure 6 As shown, the gate of MN10 inputs an external input signal VIN; the gate of MN11 inputs an output signal VO; the source of MN10, the source of MN11 and the drain of MN7 are connected; the drain of MN10, the drain of MP6, the gate of MP6 and the gate of MP8 are connected; the drain of MN11, the drain of MP7, the gate of MP7 and the gate of MP9 are connected; the gate of MN7, the gate of MN8 and the gate of MN9 are connected and connected to a second voltage vb, and the value of vb can be set by a person skilled in the art according to actual needs; the source of MP6, the source of MP7, the source of MP8 and the source of MP9 are connected to VDD; the source of MN7, the source of MN8 and the source of MN9 are connected to VSS; the drain of MN8, the drain of MP8 and the first input terminal of the OR gate are connected; the drain of MN9, the drain of MP9 and the second input terminal of the OR gate are connected; the output terminal of the OR gate outputs a selection control signal SW.

[0044] The detection module of the rail-to-rail input bias circuit can detect the differential input signal VIN and the differential input amplitude of VO (i.e., the voltage difference between VIN and VO) of the rail-to-rail input operational amplifier before the chopping switch. The gate of MN10 is input with VIN, and the gate of MN11 is input with VO. The current flowing into MN10 is denoted as IN1, and the current flowing into MN12 is denoted as IN2. IN1 is replicated as IN3 after passing through the first current mirror composed of MP6 and MP8, and IN2 is replicated as IN4 after passing through the second current mirror composed of MP7 and MP9. By setting vb, the currents of MN8, MN7, and MN9 can be biased at Ith1, ISS, and Ith2 respectively, and the ratio between Ith1, ISS, and Ith2 can be adjusted by adjusting the ratio between the aspect ratios of MN8, MN7, and MN9. IN3 is compared with Ith1, and IN4 is compared with Ith2. If IN3 < Ith1, the pull-down current between MP8 and MN8 is greater than the pull-up current, and the larger pull-down current makes the voltage VIN_H between the drain of MP8 and the drain of MN8 a low level; if IN3 > Ith1, the pull-up current between MP8 and MN8 is greater than the pull-down current, and the larger pull-up current makes VIN_H a high level; if IN4 < Ith2, the pull-down current between MP9 and MN9 is greater than the pull-up current, and the voltage VO_H between the drain of MP9 and the drain of MN9 is a low level; if IN4 > Ith2, the pull-up current between MP9 and MN9 is greater than the pull-down current, and VO_H is a high level. VIN_H and VO_H are respectively input to the first input terminal and the second input terminal of the OR gate, and the OR gate outputs a selection control signal SW according to VIN_H and VO_H.

[0045] Exemplarily, the current replication ratio of the first current mirror can be adjusted by adjusting the ratio between the aspect ratios of MP6 and MP8, so that the ratio between IN3 and IN1 can be adjusted; the current replication ratio of the second current mirror can be adjusted by adjusting the ratio between the aspect ratios of MP7 and MP9, so that the ratio between IN4 and IN2 can be adjusted; the ratio between Ith1, ISS, and Ith2 can also be adjusted by adjusting the ratio between the aspect ratios of MN8, MN7, and MN9; furthermore, the detection threshold can be flexibly adjusted so that when the differential input amplitude is greater than the detection threshold, the selection control signal SW is a high level; when the differential input amplitude is not greater than the detection threshold, the selection control signal SW is a low level. The detection threshold can be set by those skilled in the art according to actual needs.

[0046] In one embodiment, assume that the ratio between the aspect ratios of MP6 and MP8 is 1:1, the ratio between the aspect ratios of MP7 and MP9 is 1:1, and the ratio between the aspect ratios of MN8, MN7, and MN9 is m:1:m. Then, the current replication ratios of the current mirrors formed by MP6 and MP8 and by MP7 and MP9 are both 1:1, IN3 = IN1, and IN4 = IN2; Ith1 = Ith2 = m*ISS. Assume Ith1 = Ith2 = Ith. By adjusting the value of m, ISS / 2 < Ith < ISS can be achieved, and Ith is made greater than the larger one of IN1 and IN2 when the differential input amplitude does not exceed the detection threshold, and Ith is made less than the larger one of IN1 and IN2 when the differential input amplitude exceeds the detection threshold.

[0047] When the differential input amplitude is 0 (i.e., when the voltages of VIN and VO are equal), the gate voltages of MN10 and MN11 are equal. At this time, IN1 = IN2 = ISS / 2. Since IN3 = IN1 and IN4 = IN2, then IN3 = IN4 = ISS / 2. Since ISS / 2 < Ith, IN3 < Ith and IN4 < Ith. At this time, both VIN_H and VO_H are at low level, and the selection control signal SW output by the OR gate is at low level. The multiplexer of the bias module can input the external input signal VIN to the gate of MN2 in response to the low-level selection control signal SW.

[0048] When the differential input amplitude is positive (i.e., the voltage of VIN is greater than the voltage of VO) and does not exceed the detection threshold, the gate voltage of MN10 is greater than the gate voltage of MN11, IN1 > IN2. At this time, IN1 > ISS / 2 and IN2 < ISS / 2, that is, IN3 > ISS / 2 and IN4 < ISS / 2. Since ISS / 2 < Ith < ISS and Ith is greater than the larger one of IN1 and IN2 when the differential input amplitude does not exceed the detection threshold (i.e., Ith > IN1), then IN3 < Ith and IN4 < Ith. At this time, both VIN_H and VO_H are at low level, and the selection control signal SW output by the OR gate is at low level. The multiplexer of the bias module can input the external input signal VIN to the gate of MN2 in response to the low-level selection control signal SW.

[0049] When the differential input amplitude is negative (i.e., the voltage of VIN is less than the voltage of VO) and does not exceed the detection threshold, the gate voltage of MN11 is greater than the gate voltage of MN10, IN2 > IN1. At this time, IN1 < ISS / 2, IN2 > ISS / 2, that is, IN3 < ISS / 2, IN4 > ISS / 2. Since ISS / 2 < Ith < ISS and Ith is greater than the larger one of IN1 and IN2 when the differential input amplitude does not exceed the detection threshold (i.e., Ith > IN2), then IN3 < Ith, IN4 < Ith. At this time, both VIN_H and VO_H are at low level, and the selection control signal SW output by the OR gate is at low level. The multiplexer of the bias module inputs the external input signal VIN to the gate of MN2 in response to the low-level selection control signal SW.

[0050] When the differential input amplitude is positive and exceeds the detection threshold, IN1 > IN2, IN1 > ISS / 2, IN2 < ISS / 2, that is, IN3 > ISS / 2, IN4 < ISS / 2. Since ISS / 2 < Ith < ISS and Ith is less than the larger one of IN1 and IN2 when the differential input amplitude exceeds the detection threshold (i.e., Ith < IN1), then IN3 > Ith, IN4 < Ith. At this time, VIN_H is at high level, VO_H is at low level, and the selection control signal SW output by the OR gate is at high level. The multiplexer of the bias module inputs the common-mode input signal VIN_CM to the gate of MN2 in response to the high-level selection control signal SW.

[0051] When the differential input amplitude is negative and exceeds the detection threshold, IN1 < IN2, IN1 < ISS / 2, IN2 > ISS / 2, that is, IN3 < ISS / 2, IN4 > ISS / 2. Since ISS / 2 < Ith < ISS and Ith is less than the larger one of IN1 and IN2 when the differential input amplitude exceeds the detection threshold (i.e., Ith < IN2), then IN3 < Ith, IN4 > Ith. At this time, VIN_H is at low level, VO_H is at high level, and the selection control signal SW output by the OR gate is at high level. The multiplexer of the bias module inputs the common-mode input signal VIN_CM to the gate of MN2 in response to the high-level selection control signal SW.

[0052] and Figure 3Compared with the traditional rail-to-rail input bias circuit shown in , the rail-to-rail input bias circuit of the embodiment of the present application adds a detection module and a multiplexer, and the differential input amplitude of the rail-to-rail input operational amplifier can be automatically detected by the detection module. Since the external input signal VIN is generally a low-frequency continuous time signal, when the differential input amplitude exceeds the detection threshold, it means that the output signal VO has a large jump, and the common-mode input signal VIN_CM will change significantly. At this time, the selection control signal SW output by the detection module is a high level, and the control end of the multiplexer in the bias module receives a high-level selection control signal, and the common-mode input signal VIN_CM is input to the gate of MN2. At this time, the configuration mode of the rail-to-rail input bias circuit of the embodiment of the present application is the same as the configuration mode of the traditional rail-to-rail input bias circuit, and both dynamically adjust the bias currents ITAILN and ITAILP of the complementary differential input pair tubes according to the common-mode input signal to avoid input transconductance changes. This configuration mode can be called a conventional rail-to-rail bias mode. When the output transient signal gradually builds up to the vicinity of the steady-state value, the differential input amplitude gradually approaches 0. When the detection module detects that the differential input amplitude is not greater than the detection threshold, the selection control signal SW output by the detection module is low level, and the control end of the multiplexer in the bias module receives the low level selection control signal, and the external input signal VIN is input to the gate of MN2. At this time, the rail-to-rail input bias circuit of the embodiment of the present application is configured to adjust the bias current of the complementary differential input pair tube according to the external input signal VIN. Because before the transient response of the rail-to-rail input operational amplifier ends, the bias currents ITAILN and ITAILP of the input stage are determined by the external input signal VIN, rather than by the common-mode input signal VIN_CM, the offset ripple caused by chopping at the output of the rail-to-rail input operational amplifier will not cause a change in the bias current provided by the rail-to-rail input bias circuit. In addition, since the output signal VO has been established near the steady-state value at the end of the transient response, VIN=VO is approximately established. At this time, the external input signal VIN is almost equal to the common-mode input signal (VIN+VO) / 2 of the actual circuit. Therefore, while eliminating the influence of the offset ripple, it will not affect the normal operation of the rail-to-rail input operational amplifier.

[0053] The embodiment of the present application proposes a simple rail-to-rail input bias circuit, which can detect the differential input amplitude change of the rail-to-rail input operational amplifier in real time and dynamically adjust the bias current of the complementary differential input pair of tubes in the input stage. When the input differential amplitude is large, the rail-to-rail input bias circuit is configured in the conventional rail-to-rail bias mode, and the common-mode input signal is input into the bias module, so that the bias current of the complementary differential input pair of tubes can be dynamically adjusted according to the output transient response, so that the input range of the rail-to-rail input operational amplifier is maximized and can respond normally to large-amplitude transient signals. When the transient input signal is established near the steady-state value and the differential input amplitude is small, the bias current of the complementary differential input pair of tubes is allocated according to the external input signal, and the bias current of the complementary differential input pair of tubes is decoupled from the output signal, and is completely biased by the external input signal, so as to avoid the offset ripple caused by chopping at the output end from affecting the bias current, so that the output offset does not change with the input signal amplitude, and significantly improves the common-mode rejection ratio of the rail-to-rail input operational amplifier.

[0054] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A rail-to-rail input bias circuit, characterized in that: Used to provide a bias voltage for the input stage of a rail-to-rail input operational amplifier; the rail-to-rail input bias circuit includes a detection module and a bias module; The detection module is used to generate a selection control signal according to the differential input amplitude and output it to the bias module; The differential input amplitude is the voltage difference between the external input signal and the output signal of the rail-to-rail input operational amplifier; The bias module is used to control the input of the external input signal or the common-mode input signal in response to the selection control signal, and transmit the bias voltage generated according to the input external input signal or the common-mode input signal to the input stage of the rail-to-rail input operational amplifier; the common-mode input signal is the sum of the external input signal and the output signal divided by 2; When the differential input amplitude is greater than the detection threshold, the bias module inputs the common mode input signal in response to the selection control signal; when the differential input amplitude is less than or equal to the detection threshold, the bias module inputs the external input signal in response to the selection control signal. The bias module includes a multiplexer, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube and a third PMOS tube; The control end of the multiplexer inputs the selection control signal; the first input end of the multiplexer inputs the common mode input signal; the second input end of the multiplexer inputs the external input signal; The output end of the multiplexer is connected to the gate of the second NMOS tube, and the multiplexer controls the common-mode input signal of the first input end of the multiplexer or the external input signal of the second input end to be input to the gate of the second NMOS tube through the output end in response to the received selection control signal; the source of the first NMOS tube, the source of the second NMOS tube and the drain of the third NMOS tube are connected; the drain of the first NMOS tube, the drain of the first PMOS tube and the gate of the first PMOS tube are connected; the drain of the second NMOS tube, the drain of the second PMOS tube, the gate of the second PMOS tube and the third PMOS tube are connected. The gate of the first PMOS tube is connected; the drain of the third PMOS tube, the drain of the fourth NMOS tube and the gate of the fourth NMOS tube are connected; the gate of the first NMOS tube is connected to the P / N switching threshold voltage; the gate of the third NMOS tube is connected to the first voltage; the source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to the positive power supply voltage of the rail-to-rail input operational amplifier; the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the negative power supply voltage of the rail-to-rail input operational amplifier; the gate of the first PMOS tube and the gate of the fourth NMOS tube are used to output a first bias voltage and a second bias voltage respectively, The detection module includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube and an OR gate; The gate of the tenth NMOS tube inputs the external input signal; the gate of the eleventh NMOS tube inputs the output signal; the source of the tenth NMOS tube, the source of the eleventh NMOS tube and the drain of the seventh NMOS tube are connected; the drain of the tenth NMOS tube, the drain of the sixth PMOS tube, the gate of the sixth PMOS tube and the gate of the eighth PMOS tube are connected; the drain of the eleventh NMOS tube, the drain of the seventh PMOS tube, the gate of the seventh PMOS tube and the gate of the ninth PMOS tube are connected; the gate of the seventh NMOS tube, the gate of the eighth NMOS tube and the gate of the ninth NMOS tube are connected The second voltage is connected and connected; the source of the sixth PMOS tube, the source of the seventh PMOS tube, the source of the eighth PMOS tube and the source of the ninth PMOS tube are connected to the positive power supply voltage of the rail-to-rail input operational amplifier; the source of the seventh NMOS tube, the source of the eighth NMOS tube and the source of the ninth NMOS tube are connected to the negative power supply voltage of the rail-to-rail input operational amplifier; the drain of the eighth NMOS tube, the drain of the eighth PMOS tube and the first input end of the OR gate are connected; the drain of the ninth NMOS tube, the drain of the ninth PMOS tube and the second input end of the OR gate are connected; the output end of the OR gate outputs the selection control signal.

2. The rail-to-rail input bias circuit according to claim 1, characterized in that: The input stage of the rail-to-rail input operational amplifier includes a first input NMOS tube, a second input NMOS tube, a first input PMOS tube, a second input PMOS tube, a fifth NMOS tube and a fourth PMOS tube; The gate of the first input NMOS tube is connected to the gate of the first input PMOS tube to form the positive input terminal of the rail-to-rail input operational amplifier; the gate of the second input NMOS tube is connected to the gate of the second input PMOS tube to form the negative input terminal of the rail-to-rail input operational amplifier; the source of the first input NMOS tube, the source of the second input NMOS tube and the drain of the fifth NMOS tube are connected; the source of the first input PMOS tube, the source of the second input PMOS tube and the drain of the fourth PMOS tube are connected; the gate of the fifth NMOS tube is connected to the gate of the fourth NMOS tube to receive the second bias voltage; the gate of the fourth PMOS tube is connected to the gate of the first PMOS tube to receive the first bias voltage; the source of the fourth PMOS tube is connected to the positive power supply voltage of the rail-to-rail input operational amplifier; the source of the fifth NMOS tube is connected to the negative power supply voltage of the rail-to-rail input operational amplifier.

3. The rail-to-rail input bias circuit according to claim 2, characterized in that: The output end of the rail-to-rail input operational amplifier is connected to the positive input end or the negative input end of the rail-to-rail input operational amplifier; wherein, when the output end of the rail-to-rail input operational amplifier is connected to the negative input end of the rail-to-rail input operational amplifier, the positive input end of the rail-to-rail input operational amplifier inputs the external input signal; when the output end of the rail-to-rail input operational amplifier is connected to the positive input end of the rail-to-rail input operational amplifier, the negative input end of the rail-to-rail input operational amplifier inputs the external input signal.

4. The rail-to-rail input bias circuit according to claim 1, characterized in that: When the differential input amplitude is greater than the detection threshold, the selection control signal is at a high level, and the multiplexer inputs the common-mode input signal to the gate of the second NMOS tube in response to the selection control signal; when the differential input amplitude is less than or equal to the detection threshold, the selection control signal is at a low level, and the multiplexer inputs the external input signal to the gate of the second NMOS tube in response to the selection control signal.

5. The rail-to-rail input bias circuit according to claim 1, characterized in that: The detection threshold is adjusted and set according to at least one of the width-to-length ratio of the seventh NMOS tube, the width-to-length ratio of the eighth NMOS tube, the width-to-length ratio of the ninth NMOS tube, the width-to-length ratio of the sixth PMOS tube, the width-to-length ratio of the seventh PMOS tube, the width-to-length ratio of the eighth PMOS tube, or the width-to-length ratio of the ninth PMOS tube.

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