Synchronous clock signal generation circuit and method

Abstract

The invention provides a synchronous clock signal generation circuit and method, and the circuit comprises an asynchronous clock sampling circuit, a first-stage high-level pulse edge expansion circuit, a second-stage high-level pulse edge expansion circuit, and a waveform integration circuit which are electrically connected in sequence. And the output end of the asynchronous clock sampling circuit is also connected with the input end of the waveform integration circuit. An asynchronous clock sampling circuit converts an input multi-path asynchronous clock signal into a pulse signal, then two-stage high-level pulse edge expansion is performed on the pulse signal to obtain a pulse signal with a preset pulse width, and the pulse signal after edge expansion is integrated with an initial pulse signal to obtain a pulse signal with a preset pulse width. Therefore, the pulse width of the last clock pulse signal in one clock period can be widened, and a synchronous clock signal which meets the clock pulse width condition and meets the time sequence unit building time and holding time requirements can be obtained.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a synchronous clock signal generation circuit and method. Background Art

[0002] Integrated circuits can be divided into synchronous circuits and asynchronous circuits. Asynchronous circuits are widely used in asynchronous SRAM, asynchronous FIFO, etc. The characteristics of asynchronous circuits are low power consumption and high speed. Power consumption is only generated when the signal jumps, and the control signal of the synchronous circuit is not flipped. However, asynchronous circuits will have design difficulties such as delays in the arrival paths of multiple asynchronous signals, signal competition, large workload of asynchronous timing analysis, and EDA tools do not support asynchronous timing and require manual analysis. Therefore, asynchronous signals can be converted into synchronous signals for synchronous control. However, in the process of converting asynchronous signals into synchronous signals, in order to ensure that the signals can be completely sampled in the clock synchronization system, it is necessary to widen the synchronous signals, that is, directly expand the pulse width of the synchronous signals. However, when the various timing units in the synchronous signals are directly widened, waveform abnormalities may result. When the abnormal synchronous signals are used for signal sampling, the signals in the clock domain cannot be completely sampled. Summary of the invention

[0003] The main purpose of the present application is to provide a synchronous clock signal generation circuit and method to ensure that a synchronous signal that meets the pulse width requirements and the pulse establishment and holding time requirements can be generated.

[0004] To achieve the above-mentioned purpose, the first aspect of the present application provides a synchronous clock signal generating circuit, including: an asynchronous clock sampling circuit, a first-level high-level pulse edge expansion circuit, a second-level high-level pulse edge expansion circuit and a waveform integration circuit; the input end of the asynchronous clock sampling circuit is used to be electrically connected to an external asynchronous clock signal generator, and the output end of the asynchronous clock sampling circuit is respectively electrically connected to the input end of the first-level high-level pulse edge expansion circuit and the input end of the waveform integration circuit; the asynchronous clock sampling circuit is used to sample the multi-channel asynchronous clock signals transmitted by the asynchronous clock signal generator to generate a pulse signal; the first-level high-level pulse edge expansion circuit is used to sample the pulse width of the high-level signal in the pulse signal. The second-level high-level pulse extension circuit is used to extend the pulse width of the high-level signal in the first high-level pulse extension signal to obtain a second high-level pulse extension signal; the input end of the second-level high-level pulse extension circuit is electrically connected to the output end of the first-level high-level pulse extension circuit, and the output end of the second-level high-level pulse extension circuit is electrically connected to the input end of the waveform integration circuit. The second-level high-level pulse extension circuit is used to extend the pulse width of the high-level signal in the first high-level pulse extension signal to obtain a second high-level pulse extension signal; the output end of the waveform integration circuit is used to be electrically connected to an external synchronous clock signal receiver, and the waveform integration circuit is used to integrate the pulse signal and the second high-level pulse extension signal, and output a synchronous clock signal to the synchronous clock signal receiver.

[0005] The second aspect of the present application provides a synchronous clock signal generation method, which is applied to the synchronous clock signal generation circuit as described in the first aspect of the present application, and the synchronous clock signal generation method includes: an asynchronous clock sampling circuit samples multiple asynchronous clock signals transmitted by an asynchronous clock signal generator to generate a pulse signal; a first-level high-level pulse extension circuit extends the pulse width of the high-level signal in the pulse signal to obtain a first high-level pulse extension signal; a second-level high-level pulse extension circuit extends the pulse width of the high-level signal in the first high-level pulse extension signal to obtain a second high-level pulse extension signal; a waveform integration circuit integrates the pulse signal and the second high-level pulse extension signal, and outputs a synchronous clock signal to the synchronous clock signal receiver.

[0006] From the above description, it can be seen that the present application converts the input multi-channel asynchronous clock signals into pulse signals through an asynchronous clock sampling circuit, and then performs two-level high-level pulse edge expansion on the pulse signal to obtain a pulse signal with a preset pulse width, and integrates the pulse signal after the edge expansion with the initial pulse signal, so as to widen the pulse width of the last clock pulse signal in a clock cycle, thereby obtaining a synchronous clock signal that meets the clock pulse width conditions and the requirements of the timing unit setup time and hold time. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 is a structural schematic diagram of a synchronous clock signal generating circuit according to an embodiment of the present application; Figure 2 It is a schematic diagram of an abnormal waveform of an asynchronous-to-synchronous signal according to an embodiment of the present application; Figure 3 This is a schematic diagram of a normal waveform of an asynchronous-to-synchronous signal according to an embodiment of the present application; Figure 4 is a circuit schematic diagram of an asynchronous clock sampling circuit according to an embodiment of the present application; Figure 5 is a waveform diagram of each output signal in a synchronous clock signal generating circuit according to an embodiment of the present application; Figure 6 It is a circuit schematic diagram of a first-level high-level pulse edge extension circuit in an embodiment of the present application; Figure 7 It is a circuit schematic diagram of a two-stage high-level pulse extension circuit according to an embodiment of the present application; Figure 8 It is a circuit schematic diagram of another secondary high-level pulse edge extension circuit of an embodiment of the present application; Fig. 9 is a circuit schematic diagram of a pulse width modulation circuit according to an embodiment of the present application; Fig.10 is a circuit schematic diagram of a waveform integration circuit according to an embodiment of the present application; Fig.11 It is a basic flow chart of a synchronous clock signal generation method according to an embodiment of the present application; Fig.12 It is a circuit schematic diagram of a synchronous clock signal generating circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0009] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0010] Since directly widening each sequential unit in the synchronization signal may cause waveform anomalies, when the abnormal synchronization signal is used for signal sampling, the signal in the clock domain cannot be completely sampled. To this end, an embodiment of the present application provides a synchronization clock signal generation circuit.

[0011] like Figure 1 The figure shows a structural schematic diagram of a synchronous clock signal generating circuit provided by an embodiment of the present application, wherein the synchronous clock signal generating circuit comprises: an asynchronous clock sampling circuit 100, a first-level high-level pulse extension circuit 200, a second-level high-level pulse extension circuit 300 and a waveform integration circuit 400; the input end of the asynchronous clock sampling circuit 100 is used to be electrically connected to an external asynchronous clock signal generator 500, the output end of the asynchronous clock sampling circuit 100 is electrically connected to the input ends of the first-level high-level pulse extension circuit 200 and the waveform integration circuit 400 respectively, the input end of the second-level high-level pulse extension circuit 300 is electrically connected to the output end of the first-level high-level pulse extension circuit 200, the output end of the second-level high-level pulse extension circuit 300 is electrically connected to the input end of the waveform integration circuit 400, and the output end of the waveform integration circuit 400 is used to be electrically connected to an external synchronous clock signal receiver 600.

[0012] Specifically, the asynchronous clock sampling circuit 100 is used to: sample the multiple asynchronous clock signals transmitted by the asynchronous clock signal generator 500 to generate a pulse signal; the first-level high-level pulse extension circuit 200 is used to: extend the pulse width of the high-level signal in the received pulse signal to obtain a first high-level pulse extension signal; the second-level high-level pulse extension circuit 300 is used to: extend the pulse width of the high-level signal in the received first high-level pulse extension signal to obtain a second high-level pulse extension signal; the waveform integration circuit 400 is used to: integrate the received pulse signal and the second high-level pulse extension signal, and output a synchronous clock signal to the synchronous clock signal receiver 600.

[0013] It should be noted that when converting an asynchronous clock signal to a synchronous clock signal, the resulting synchronous clock signal needs to meet the following conditions: Condition a is that the generated clock pulse width is greater than the minimum pulse width min_pulse of all sequential units in the clock domain; Condition b is that the generated sequential unit meets the requirements of the setup and hold time of the corresponding sequential unit. If the above two conditions are not met, the converted clock signal is abnormal, for example Figure 2The abnormal waveform diagram of the asynchronous-to-synchronous signal is shown in the figure, where "ABCD" represents the pulse signals corresponding to the address, chip select, read / write enable, and output enable signals respectively (address, chip select, read / write enable, and output enable are key control signals of asynchronous SRAM, used to control the read / write operations of asynchronous SRAM). Since the synchronous clock signal is generated at the falling edge of the A pulse signal, the synchronous clock signal meets the required condition a, but because the synchronous clock signal is generated too early, it does not meet the setup and hold time requirements (i.e. condition b) in the subsequent timing units. However, as Figure 3 In the normal waveform diagram of the asynchronous-to-synchronous signal shown in FIG, the synchronous clock signal is generated at the falling edge of each input pulse signal, and when each pulse signal arrives, the previously generated synchronous clock signal is cleared at its rising edge, and the synchronous clock signal is regenerated at the falling edge of its pulse signal, thereby Figure 3 The synchronous clock generated by the A BC pulse signal does not meet condition a or condition b, while the synchronous clock generated by the D pulse signal meets both condition a and condition b. That is, the pulse width of the D pulse signal is greater than the pulse width of the A, B, and C pulse signals, and at the same time, the timing unit generated by the D pulse signal meets the requirements of the establishment and hold time of the corresponding timing unit (that is, the D timing unit in the IN signal). When using this type of synchronous clock signal for sampling, it can ensure that all signals within the clock cycle are sampled. If the pulse width of other clock pulses is widened, the signal before this clock pulse can be sampled, but the signal after this clock pulse cannot be sampled. For example Figure 2As shown in the CLK signal, the widened signal is the A clock pulse, and the B, C, and D clock pulses are filtered out. If this type of synchronous clock is used to sample the signal, only the A signal can be sampled, and the B, C, and D signals cannot be sampled. Similarly, if the widened signal is the B clock pulse, and the timing unit generated by the B clock pulse meets the requirements of the establishment and hold time of the corresponding timing unit, if this synchronous clock is used to sample the signal, only the A and B signals can be sampled, and the C and D signals cannot be sampled. Only when the D clock pulse satisfies the requirements that the generated clock pulse width is greater than the min_pulse of all timing units in the clock domain and the generated timing unit meets the requirements of the establishment and hold time of the corresponding timing unit, can the A, B, C, and D signals be sampled using such synchronous clock information sampling. Even if the A, B, and C clock pulses all meet the conditions a and b required by the synchronous clock, the D clock pulse does not meet the conditions a and b required by the synchronous clock. Using this synchronous clock for sampling, the A, B, and C signals can be sampled, but the D signal cannot be sampled. If among the A, B, C, and D clock pulses, only the D clock pulse meets the conditions a and b required for the synchronous clock, even if the A, B, and C clock pulses do not meet the conditions a and b required for the synchronous clock, the A, B, C, and D signals can be sampled when this signal is used for sampling. Therefore, the synchronous clock needs to focus on the last clock pulse in a clock cycle, and at the same time requires that the pulse width of this clock pulse is greater than the min_pulse of all sequential units in the clock domain and that the generated sequential units meet the requirements of the setup and hold time of the corresponding sequential units.

[0014] In this embodiment, the asynchronous clock sampling circuit 100 samples the input multi-channel asynchronous clock signals to generate a pulse signal, that is, converts the input asynchronous clock signal into a pulse signal, and then performs two-level high-level pulse edge expansion on the pulse signal to obtain a pulse signal with a preset pulse width. The pulse signal after the edge expansion is integrated with the initial pulse signal, so that the pulse width of the last clock pulse signal in a clock cycle can be widened, thereby obtaining a synchronous clock signal that satisfies the clock pulse width condition and the timing unit setup time and hold time requirements.

[0015] like Figure 4 FIG. 1 is a circuit schematic diagram of an asynchronous clock sampling circuit provided in this embodiment. Figure 4The asynchronous clock sampling circuit 100 includes a first OR gate circuit, which includes a first PMOS transistor PM0, a second PMOS transistor PM1, a third PMOS transistor PM3, a first NMOS transistor NM0, a second NMOS transistor NM1 and a third NMOS transistor NM3; the source and substrate of the first PMOS transistor PM0 and the second PMOS transistor PM1 are electrically connected to the positive power supply VDD, the drain of the first PMOS transistor PM0 is electrically connected to the source of the third PMOS transistor PM3, the drain of the third PMOS transistor PM3 is electrically connected to the drain of the first NMOS transistor NM0, the substrate of the third PMOS transistor PM3 is electrically connected to the positive power supply VDD, the first NMOS transistor NM0, the second NMOS transistor NM1 are electrically connected to the positive power supply VDD, and the first NMOS transistor NM0 and the second NMOS transistor NM1 are electrically connected to the positive power supply VDD. The source and substrate of the third NMOS tube NM3 are electrically connected to the negative power supply VSS, the drain of the third NMOS tube NM3 is electrically connected to the drain of the first NMOS tube NM0, the gates of the first PMOS tube PM0 and the third NMOS tube NM3 are interconnected and serve as the first input end of the asynchronous clock sampling circuit 100, the third PMOS tube PM3 and the gate of the first NMOS tube NM0 are interconnected and serve as the second input end of the asynchronous clock sampling circuit 100, the gates of the second PMOS tube PM1 and the second NMOS tube NM1 are electrically connected to the drain of the third NMOS tube NM3, the drains of the second PMOS tube PM1 and the second NMOS tube NM1 are interconnected and serve as the output end of the asynchronous clock sampling circuit 100.

[0016] Specifically, in this embodiment, the asynchronous clock sampling circuit 100 is mainly composed of a two-input OR gate circuit. The asynchronous clock sampling circuit 100 generates a high-level narrow pulse signal (for example, Figure 5 The signal net3 in the figure). Among them, for the asynchronous clock signal input to the two-input OR gate circuit, it is required that when one of the signals is at a high level, the other signal is at a low level to prevent sampling signal conflicts. The two-input OR gate circuit in this embodiment is mainly composed of three PMOS tubes and three NMOS tubes. The NMOS tubes have four ports of source, drain, gate, and substrate. The substrates of the NMOS tubes are all connected to the negative power supply VSS; the PMOS tubes have four ports of source, drain, gate, and substrate. The substrates of the PMOS tubes are all connected to the positive power supply VDD.

[0017] like Figure 6 The circuit schematic diagram of a first-level high-level pulse edge extension circuit provided by this embodiment is shown in FIG. Figure 6The first-level high-level pulse extension circuit 200 includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fourth NMOS tube NM22 and a fifth NMOS tube NM23; the first end of the first inverter and the gate of the fifth NMOS tube NM23 are both electrically connected to the output end of the asynchronous clock sampling circuit 100, the second end of the first inverter is electrically connected to the first end of the second inverter, the second end of the second inverter is electrically connected to the first end of the third inverter, the second end of the third inverter is electrically connected to the first end of the fourth inverter, and the second end of the fourth inverter is electrically connected to the second-level high-level pulse extension circuit 200. The input end of the level pulse extension circuit 300 is electrically connected, the third end and the fourth end of the first inverter, the second inverter, the third inverter and the fourth inverter are electrically connected to the positive power supply VDD and the negative power supply VSS respectively, the gate of the fourth NMOS tube NM22 is electrically connected to the second end of the second inverter, the source, the drain and the substrate of the fourth NMOS tube NM22 are electrically connected to the negative power supply VSS, the drain of the fifth NMOS tube NM23 is electrically connected to the second end of the third inverter, and the source and the substrate of the fifth NMOS tube NM23 are electrically connected to the negative power supply VSS.

[0018] For further information, see Figure 6 The first inverter, the second inverter, the third inverter and the fourth inverter all include a fourth PMOS tube and a sixth NMOS tube; the source and substrate of the fourth PMOS tube are both electrically connected to the positive power supply VDD, the gates of the fourth PMOS tube and the sixth NMOS tube are interconnected and serve as the first end of the inverter, the drain of the fourth PMOS tube and the drain of the sixth NMOS tube are interconnected and serve as the second end of the inverter, and the source and substrate of the sixth NMOS tube are both electrically connected to the negative power supply VSS.

[0019] Specifically, the first inverter is mainly composed of an NMOS tube NM2 and a PMOS tube PM2, the gate of the PMOS tube PM2 is connected to the gate of the NMOS tube NM2 and serves as the input end of the first inverter (i.e., the first end net3), the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM2 and serves as the output end of the first inverter (i.e., the second end net4), the source and substrate of the PMOS tube PM2 are connected to VDD, and the source and substrate of the NMOS tube NM2 are connected to VSS; the second inverter is mainly composed of an NMOS tube NM4 and a PMOS tube PM4, the gate of the PMOS tube PM4 is connected to the gate of the NMOS tube NM4 and serves as the input end of the second inverter (i.e., net4), the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM4 and serves as the output end of the second inverter (i.e., net5), the source and substrate of the PMOS tube PM4 are connected to VDD, and the source and substrate of the NMOS tube NM4 are connected to VSS. connected to VSS; the third inverter is mainly composed of an NMOS tube NM5 and a PMOS tube PM5, the gate of the PMOS tube PM5 and the gate of the NMOS tube NM5 are connected and serve as the input end (i.e., net5) of the third inverter, the drain of the PMOS tube PM5 and the drain of the NMOS tube NM5 are connected and serve as the output end (i.e., net6) of the third inverter, the source and substrate of the PMOS tube PM5 are connected to VDD, and the source and substrate of the NMOS tube NM5 are connected to VSS; the fourth inverter is mainly composed of an NMOS tube NM6 and a PMOS tube PM6, the gate of the PMOS tube PM6 and the gate of the NMOS tube NM6 are connected and serve as the input end (i.e., net6) of the fourth inverter, the drain of the PMOS tube PM6 and the drain of the NMOS tube NM6 are connected and serve as the output end (i.e., net7) of the fourth inverter, the source and substrate of the PMOS tube PM6 are connected to VDD, and the source and substrate of the NMOS tube NM6 are connected to VSS.

[0020] In this embodiment, since the pulse width of the pulse signal obtained by the asynchronous clock sampling circuit 100 is narrow, it can be pre-widened by the first-level high-level pulse expansion circuit 200. The first-level high-level pulse expansion circuit 200 is mainly composed of four inverters and two NMOS tubes, one of which NMOS tube NM22 can be equivalent to a capacitor. When the pulse signal changes from a high level to a low level, the NMOS capacitor NM22 discharges to keep the pulse signal at a high level, thereby achieving the expansion of the high-level pulse; the other NMOS tube NM23 is used to reduce the high-level signal jump delay and the signal change in advance. Each inverter in this embodiment includes a PMOS tube and an NMOS tube.

[0021] In the first-stage high-level pulse extension circuit 200 of this embodiment, when a high-level narrow pulse signal is input from net3, after passing through the first inverter, the high level of the signal changes to a low level, and the low level changes to a high level (for example Figure 5 The signal net4 in the figure). When passing through the second inverter, the low level of the signal becomes a high level, and the high level becomes a low level; because the output net5 of the second inverter is connected to the NMOS capacitor NM22, when the high level passes through the second inverter and the signal is about to become a low level, the NMOS capacitor NM22 will discharge, so that the high level signal remains at a high level after passing through the second inverter, and at the same time, the delay time of the falling edge of the output signal of the second inverter is increased. Therefore, after the high-level narrow pulse signal passes through the second inverter, the pulse signal becomes a high-level signal with a relatively gentle falling edge (for example Figure 5 After the signal passes through the third inverter, the high level of the signal becomes a low level, and the low level becomes a high level. Since the output net6 of the third inverter is connected to the NMOS tube NM23, the input signal will jump from a high level to a low level in advance; at the same time, after the signal passes through the third inverter, the originally gentle edge becomes steeper (for example Figure 5 When the signal passes through the fourth inverter, the high level of the signal will become a low level, and the low level will become a high level. At the same time, the rising and falling edges of the signal will become steeper (for example, Figure 5 After passing through the fourth inverter, the signal changes from a high-level narrow pulse signal to a high-level signal and is output through net7.

[0022] like Figure 7 The circuit schematic diagram of a two-stage high-level pulse extension circuit provided by this embodiment is shown in FIG. Figure 7The secondary high-level pulse extension circuit 300 includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a seventh NMOS tube NM27, an eighth NMOS tube NM28 and a resistor R1R1; the first end of the fifth inverter and the gate of the eighth NMOS tube NM28 are electrically connected to the output end of the primary high-level pulse extension circuit 200, the second end of the fifth inverter is electrically connected to the first end of the sixth inverter, the second end of the sixth inverter is electrically connected to the first end of the seventh inverter, the second end of the seventh inverter is electrically connected to the first end of the eighth inverter, the second end of the eighth inverter is electrically connected to the first end of the ninth inverter, and the second end of the ninth inverter is electrically connected to the waveform integration circuit 200. The input end of the circuit 400 is electrically connected, the third end and the fourth end of the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter and the ninth inverter are electrically connected to the positive power supply VDD and the negative power supply VSS respectively, the gate of the seventh NMOS tube NM27 is electrically connected to the second end of the sixth inverter, the source, the drain and the substrate of the seventh NMOS tube NM27 are electrically connected to the negative power supply VSS, the drain of the eighth NMOS tube NM28 is electrically connected to the second end of the seventh inverter, the source and the substrate of the eighth NMOS tube NM28 are electrically connected to the negative power supply VSS, one end of the resistor R1 is electrically connected to the second end of the sixth inverter, and the other end of the resistor R1 is electrically connected to the negative power supply VSS.

[0023] Each inverter in this embodiment includes a PMOS transistor and an NMOS transistor, and the structure of each inverter is the same as the structure of the inverter in the first-stage high-level pulse extension circuit 200 .

[0024] Specifically, the fifth inverter is mainly composed of an NMOS tube NM7 and a PMOS tube PM7, the gate of the PMOS tube PM7 is connected to the gate of the NMOS tube NM7 and serves as the input end (i.e., net7) of the fifth inverter, the drain of the PMOS tube PM7 is connected to the drain of the NMOS tube NM7 and serves as the output end (i.e., net8) of the fifth inverter, the source and substrate of the PMOS tube PM7 are connected to VDD, and the source and substrate of the NMOS tube NM7 are connected to VSS; the sixth inverter is mainly composed of an NMOS tube NM9 and a PMOS tube PM9, the gate of the PMOS tube PM9 and the NM The gate of the OS transistor NM9 is connected and serves as the input end (i.e., net8) of the sixth inverter. The drain of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM9 and serves as the output end (i.e., CAP) of the sixth inverter. The source and substrate of the PMOS transistor PM9 are connected to VDD. The source and substrate of the NMOS transistor NM9 are connected to VSS. The seventh inverter is mainly composed of the NMOS transistor NM11 and the PMOS transistor PM11. The gate of the PMOS transistor PM11 is connected to the gate of the NMOS transistor NM11 and serves as the input end (i.e., CAP) of the seventh inverter. The drain of the PMOS transistor PM11 and the NMOS transistor NM11 are connected to the drain of the PMOS transistor PM11 and serve as the output end (i.e., CAP) of the seventh inverter. The drain of the MOS tube NM11 is connected and serves as the output end (i.e., net9) of the seventh inverter, the source and substrate of the PMOS tube PM11 are connected to VDD, and the source and substrate of the NMOS tube NM11 are connected to VSS; the eighth inverter is mainly composed of the NMOS tube NM12 and the PMOS tube PM12, the gate of the PMOS tube PM12 is connected to the gate of the NMOS tube NM12 and serves as the input end (i.e., net9) of the eighth inverter, the drain of the PMOS tube PM12 is connected to the drain of the NMOS tube NM12 and serves as the output end (i.e., net10) of the eighth inverter, and the PMOS tube The source and substrate of PM12 are connected to VDD, and the source and substrate of NMOS tube NM12 are connected to VSS; the ninth inverter is mainly composed of NMOS tube NM14 and PMOS tube PM14, the gate of PMOS tube PM14 is connected to the gate of NMOS tube NM14 and serves as the input end (i.e., net10) of the ninth inverter, the drain of PMOS tube PM14 is connected to the drain of NMOS tube NM14 and serves as the output end (i.e., net11) of the ninth inverter, the source and substrate of PMOS tube PM14 are connected to VDD, and the source and substrate of NMOS tube NM14 are connected to VSS.

[0025] In this embodiment, the secondary high-level pulse extension circuit 300 is mainly composed of five inverters, two NMOS tubes and a resistor R1, wherein one NMOS tube NM27 can be equivalent to a capacitor. When the pulse signal changes from a high level to a low level, the NMOS capacitor NM27 discharges to make the falling edge of the pulse signal smooth, thereby achieving the extension of the signal pulse width; the other NMOS tube NM28 is used to reduce the high-level signal jump delay and the early change of the signal. The resistor R1 is used to introduce the excess current of the capacitor discharge into the ground line when the MOS tubes of the first two inverters are not turned on, so as to avoid the MOS tube turn-on condition fluctuating up and down due to the capacitor discharge and affecting the turn-on of the MOS tube.

[0026] In the two-stage high-level pulse extension circuit 300 of this embodiment, the input signal is the output signal of the one-stage high-level pulse extension circuit 200. When passing through the first inverter (i.e., the fifth inverter), the high level of the signal changes to a low level, and the low level changes to a high level. When the signal passes through the second inverter (i.e., the sixth inverter), the high level of the signal changes to a low level, and the low level changes to a high level. However, the output CAP of the second inverter is connected to an NMOS capacitor NM27, which discharges when the signal changes from a high level to a low level, resulting in a smooth falling edge from a high level to a low level (for example, Figure 5 The signal CAP in the circuit can avoid the situation where the two pulses may become one pulse when the interval between the two pulses is short, because the gentle falling edge of the previous pulse will extend to the rising edge of the next level, causing the pulse to be cleared. After the signal passes through the third inverter (i.e. the seventh inverter), the high level of the signal becomes a low level, and the low level becomes a high level. At the same time, the gentle edge of the signal becomes steeper (for example Figure 5 The signal net9 in the figure is because the output net9 of the third inverter is connected to the NMOS tube NM28, which makes the input signal jump from high level to low level in advance, reducing the jump delay of the high level signal. The fourth and fifth inverters (i.e. the eighth inverter and the ninth inverter) will make the high level of the signal change to low level and the low level change to high level. At the same time, it is also a further optimization of the smooth edge of the signal, making the smooth edge of the signal steeper. After the signal passes through the fifth inverter, it outputs a level signal with a steep edge and a wide pulse width (for example Figure 5 signal net11 in the output).

[0027] like Figure 8 , Fig. 9 The following are the circuit schematic diagrams of another secondary high-level pulse extension circuit and a pulse width modulation circuit provided in this embodiment, see Figure 8 and Fig. 9The synchronous clock signal generating circuit also includes a pulse width modulation circuit 700, and the secondary high-level pulse extension circuit 300 also includes a ninth NMOS tube NM24, a tenth NMOS tube NM25 and an eleventh NMOS tube NM26; the drain, source and substrate of the ninth NMOS tube NM24, the tenth NMOS tube NM25 and the eleventh NMOS tube NM26 are all electrically connected to the negative power supply VSS, the gates of the ninth NMOS tube NM24, the tenth NMOS tube NM25 and the eleventh NMOS tube NM26 are all electrically connected to the first end of the pulse width modulation circuit 700, and the second end of the pulse width modulation circuit 700 is electrically connected to the second end of the sixth inverter.

[0028] Specifically, in the present embodiment, the secondary high-level pulse extension circuit 300 further includes three selected NMOS capacitors NM24, NM25, and NM26, which are connected to the secondary high-level pulse extension circuit 300 through a pulse width modulation circuit. By selecting the corresponding NMOS capacitor to be connected to the circuit through the pulse width modulation circuit 700, the capacitance of the capacitor connected to the secondary high-level pulse extension circuit 300 can be adjusted, thereby realizing the speed adjustment of the discharge process, and further realizing the adjustment of the pulse width.

[0029] For further information, see Fig. 9 The pulse width modulation circuit 700 includes a first selection circuit 710, a second selection circuit 720 and a third selection circuit 730. The first selection circuit 710 corresponds to the ninth NMOS tube NM24, the second selection circuit 720 corresponds to the tenth NMOS tube NM25, and the third selection circuit 730 corresponds to the eleventh NMOS tube NM26. The first selection circuit 710, the second selection circuit 720 and the third selection circuit 730 all include a transmission gate and a tenth inverter. The first end of the tenth inverter is electrically connected to the first end of the transmission gate, and the first end of the tenth inverter is also used to be electrically connected to an external selection signal generator. The second end of the tenth inverter is electrically connected to the second end of the transmission gate. The third end and the fourth end of the tenth inverter are electrically connected to the positive power supply VDD and the negative power supply VSS, respectively. The third end of the transmission gate is electrically connected to the second end of the sixth inverter. The fourth end of the transmission gate is electrically connected to the gate of the corresponding NMOS tube. The third end and the fourth end of the transmission gate are electrically connected to the positive power supply VDD and the negative power supply VSS, respectively.

[0030] For further information, see Fig. 9The transmission gate includes a fifth PMOS tube and a twelfth NMOS tube; the gate of the twelfth NMOS tube is electrically connected to the first end of the tenth inverter, the gate of the fifth PMOS tube is electrically connected to the second end of the tenth inverter, the drain of the fifth PMOS tube and the source of the twelfth NMOS tube are both electrically connected to the second end of the sixth inverter, the source of the fifth PMOS tube and the drain of the twelfth NMOS tube are both electrically connected to the gate of the corresponding NMOS tube, the substrate of the fifth PMOS tube is electrically connected to the positive power supply VDD, and the substrate of the twelfth NMOS tube is electrically connected to the negative power supply VSS.

[0031] In this embodiment, the pulse width modulation circuit 700 is mainly composed of three selection circuits corresponding to the selection of NMOS capacitors, each of which includes a transmission gate and an inverter. The transmission gate is mainly composed of a PMOS tube and an NMOS tube. The structure of the inverter is the same as the structure of the inverter in the first-level high-level pulse expansion circuit 200.

[0032] Specifically, the transmission gate of the first selection circuit is mainly composed of a PMOS tube PM8 and an NMOS tube NM8. The source of the PMOS tube PM8 and the drain of the NMOS tube NM8 are connected to CAP, the drain of the PMOS tube PM8 and the source of the NMOS tube NM8 are connected to the gate CAP0 of the NMOS tube NM24 in the secondary high-level pulse extension circuit 300, the gate of the NMOS tube NM8 is connected to S0 (i.e., a selection signal transmitted by the selection signal generator), and the substrate of the NMOS tube NM8 is connected to VSS. The gate of the PMOS tube PM8 is connected to net14, and the substrate of the PMOS tube PM8 is connected to VDD; the inverter of the first selection circuit is mainly composed of a PMOS tube PM19 and an NMOS tube NM19, the gate of the PMOS tube PM19 and the gate of the NMOS tube NM19 are connected to S0, the drain of the PMOS tube PM14 and the drain of the NMOS tube NM14 are connected to net14, the source and substrate of the PMOS tube PM19 are connected to VDD, and the source and substrate of the NMOS tube NM19 are connected to VSS. The transmission gate of the second selection circuit is mainly composed of a PMOS tube PM10 and an NMOS tube NM10. The source of the PMOS tube PM10 and the drain of the NMOS tube NM10 are connected to CAP, the drain of the PMOS tube PM10 and the source of the NMOS tube NM10 are connected to the gate CAP1 of the NMOS tube NM25 in the secondary high-level pulse extension circuit 300, the gate of the NMOS tube NM10 is connected to S1 (i.e., a selection signal transmitted by the selection signal generator), and the substrate of the NMOS tube NM10 is connected to VSS. , the gate of the PMOS tube PM10 is connected to net15, and the substrate of the PMOS tube PM10 is connected to VDD; the inverter of the second selection circuit is mainly composed of a PMOS tube PM20 and an NMOS tube NM20, the gate of the PMOS tube PM20 and the gate of the NMOS tube NM20 are connected to S1, the drain of the PMOS tube PM20 and the drain of the NMOS tube NM20 are connected to net15, the source and substrate of the PMOS tube PM20 are connected to VDD, and the source and substrate of the NMOS tube NM20 are connected to VSS.The transmission gate of the third selection circuit is mainly composed of a PMOS tube PM13 and an NMOS tube NM13. The source of the PMOS tube PM13 and the drain of the NMOS tube NM13 are connected to CAP, the drain of the PMOS tube PM13 and the source of the NMOS tube NM13 are connected to the gate CAP2 of the NMOS tube NM26 in the secondary high-level pulse extension circuit 300, the gate of the NMOS tube NM13 is connected to S2 (i.e., a selection signal transmitted by the selection signal generator), and the substrate of the NMOS tube NM13 is connected to VSS. , the gate of the PMOS tube PM13 is connected to net16, and the substrate of the PMOS tube PM13 is connected to VDD; the inverter of the third selection circuit is mainly composed of a PMOS tube PM21 and an NMOS tube NM21, the gate of the PMOS tube PM21 and the gate of the NMOS tube NM21 are connected to S2, the drain of the PMOS tube PM21 and the drain of the NMOS tube NM21 are connected to net16, the source and substrate of the PMOS tube PM21 are connected to VDD, and the source and substrate of the NMOS tube NM21 are connected to VSS.

[0033] In the pulse width modulation circuit 700 of the present embodiment, the input selection signals S0, S1, and S2 are changed into high-level signals, thereby controlling the corresponding selection of NMOS capacitors to be connected to the circuit. When the selection signal S0 is a high-level signal, the input and output of the inverter formed by the PMOS tube PM19 and the NMOS tube NM19 are the signals S0 and net14, respectively. At this time, the net14 signal is a low-level signal, so that the gate of the PMOS tube PM8 is connected to a low level, and the gate of the NMOS tube NM8 is connected to a high level. The transmission gate formed by the PMOS tube PM8 and the NMOS tube NM8 is turned on, and the CAP signal line of the transmission gate is connected to the signal line CAP0. The NMOS capacitor NM24 selected in the secondary high-level pulse extension circuit 300 is connected to the CAP line and is connected in parallel with the NMOS capacitor NM27. The capacitance connected to the CAP signal line increases, the discharge capacity of the capacitor is enhanced, the falling edge of the signal from the high level to the low level becomes smoother, and the pulse width of the signal increases (for example, Figure 5 Similarly, when S1 or S2 is a high level signal, the corresponding transmission gate is turned on, so that the CAP signal line of the transmission gate is connected to the signal line CAP1 or CAP2, and the secondary high level pulse extension circuit 300 selects NMOS capacitor NM25 or selects NMOS capacitor NM26 to be connected to the CAP line and connected in parallel with NMOS capacitor NM27, the capacitance connected to the CAP signal line increases, the discharge capacity of the capacitor is enhanced, the falling edge of the signal from high level to low level becomes smoother, and the pulse width of the signal increases.

[0034] like Fig.10 The circuit diagram of a waveform integration circuit provided by this embodiment is shown in FIG. Fig.10The waveform integration circuit 400 includes a second OR gate circuit and an eleventh inverter. The first input end of the second OR gate circuit is electrically connected to the output end of the asynchronous clock sampling circuit 100, the second input end of the second OR gate circuit is electrically connected to the output end of the secondary high-level pulse extension circuit 300, the output end of the second OR gate circuit is electrically connected to the first end of the eleventh inverter, and the second end of the eleventh inverter is used to be electrically connected to the synchronous clock signal receiver 600.

[0035] The waveform integration circuit 400 in this embodiment is mainly composed of an OR gate circuit and an inverter. The structure of the OR gate circuit is the same as that of the OR gate circuit in the asynchronous clock sampling circuit 100, and the structure of the inverter is the same as that of the inverter in the first-level high-level pulse extension circuit 200.

[0036] Specifically, in the second OR gate circuit, the PMOS tube PM16 and the PMOS tube PM15 are connected in series, the NMOS tube NM15 and the NMOS tube NM16 are connected in parallel, the gates of the PMOS tube PM16 and the NMOS tube NM16 are connected to net3, the gates of the PMOS tube PM15 and the NMOS tube NM15 are connected to net11, the drain of the PMOS tube PM16 and the source of the PMOS tube PM15 are connected to net17, the drain of the NMOS tube NM15 and the drain of the NMOS tube NM16 are connected to net12, and the drain of the PMOS tube PM15 is connected to net13. The drain of NMOS tube NM15 is connected to net12, the source and substrate of PMOS tube PM16 are connected to VDD, the substrate of PMOS tube PM15 is connected to VDD, and the source and substrate of NMOS tubes NM15 and NM16 are connected to VSS; the gate of PMOS tube PM17 and the gate of NMOS tube NM17 are connected to net12, the drain of PMOS tube PM17 and the drain of NMOS tube NM17 are connected to net13, the source and substrate of PMOS tube PM17 are connected to VDD, and the source and substrate of NMOS tube NM17 are connected to VSS. In the eleventh inverter, the gate of PMOS tube PM18 and the gate of NMOS tube NM18 are connected to net13, the drain of PMOS tube PM18 and the drain of NMOS tube NM18 are connected to OUT, the source and substrate of PMOS tube PM17 are connected to VDD, and the source and substrate of NMOS tube NM17 are connected to VSS. The input and output of the inverter are net17 and OUT respectively.

[0037] In this embodiment, the waveform integration circuit 400 converts the high-level narrow pulse signal (eg, Figure 5 The signal net3 in the secondary high level pulse extension circuit 300 transmits a second high level pulse extension signal (eg Figure 5After the signal net11 in the figure is processed by an OR operation (i.e., a combination of an NOR gate and a NOT gate), and then an inverter is used to integrate the waveform (i.e., a NOT operation is performed), the pulse widening pulse signal will be obtained, that is, a synchronous clock signal that meets the clock pulse width condition and the setup time and hold time requirements of the timing unit (e.g. Figure 5 signal OUT in the

[0038] The embodiment of the present application also provides a synchronous clock signal generation method, which is applied to the synchronous clock signal generation circuit mentioned above, see Fig.11 The basic flow chart of the synchronous clock signal generation method shown in FIG. Fig.12 The circuit schematic diagram of the synchronous clock signal generating circuit shown in the figure, the synchronous clock signal generating method includes: Step 1101: an asynchronous clock sampling circuit samples multiple asynchronous clock signals transmitted by an asynchronous clock signal generator to generate a pulse signal; Step 1102: a first-level high-level pulse edge extension circuit extends the pulse width of the high-level signal in the pulse signal to obtain a first high-level pulse edge extension signal; Step 1103, the secondary high-level pulse edge extension circuit extends the pulse width of the high-level signal in the first high-level pulse edge extension signal to obtain a second high-level pulse edge extension signal; Step 1104 , the waveform integration circuit integrates the pulse signal and the second high level pulse extension edge signal, and outputs a synchronous clock signal to a synchronous clock signal receiver.

[0039] Specifically, in the present embodiment, the asynchronous clock sampling circuit 100 can generate a high-level narrow pulse signal by sampling a plurality of asynchronous clock input signals by performing an OR operation. The first-level high-level pulse expansion circuit 200 is based on the principle of capacitor charging and discharging. When the signal changes from a high level to a low level, the signal is maintained at a high level by capacitor discharge, thereby realizing the expansion of the high-level pulse. The second-level high-level pulse expansion circuit 300 is also based on the principle of capacitor charging and discharging. When the signal changes from a high level to a low level, the falling edge of the signal is smoothed by capacitor discharge, thereby realizing the expansion of the signal pulse width. The waveform integration circuit 400 performs an OR operation on the output signal of the asynchronous clock sampling circuit 100 and the output signal of the second-level high-level pulse expansion circuit 300, and then integrates the waveform through an inverter to output a synchronous clock signal. In addition, the pulse width modulation circuit 700 can be used to select the NMOS capacitor in the secondary high-level pulse expansion circuit 300 and connect it to the secondary high-level pulse expansion circuit 300 to change the capacitance of the capacitor connected to the secondary high-level pulse expansion circuit 300, thereby changing the capacitor discharge capacity of the secondary high-level pulse expansion circuit 300, and then realizing the adjustment of the signal pulse width.

[0040] It should be noted that the various embodiments in the present application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0041] It should also be noted that, in the content of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0042] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A synchronous clock signal generating circuit, characterized in that: include: Asynchronous clock sampling circuit, primary high level pulse edge extension circuit, secondary high level pulse edge extension circuit and waveform integration circuit; The input end of the asynchronous clock sampling circuit is used to be electrically connected to an external asynchronous clock signal generator, and the output end of the asynchronous clock sampling circuit is electrically connected to the input end of the first-level high-level pulse edge expansion circuit and the waveform integration circuit respectively. The asynchronous clock sampling circuit is used to sample the multi-channel asynchronous clock signals transmitted by the asynchronous clock signal generator to generate a pulse signal; The first-level high-level pulse edge extension circuit is used to extend the pulse width of the high-level signal in the pulse signal to obtain a first high-level pulse edge extension signal; The input end of the secondary high-level pulse extension circuit is electrically connected to the output end of the primary high-level pulse extension circuit, the output end of the secondary high-level pulse extension circuit is electrically connected to the input end of the waveform integration circuit, and the secondary high-level pulse extension circuit is used to extend the pulse width of the high-level signal in the first high-level pulse extension signal to obtain a second high-level pulse extension signal; The output end of the waveform integration circuit is used to be electrically connected to an external synchronous clock signal receiver, and the waveform integration circuit is used to integrate the pulse signal and the second high-level pulse extension signal, and output the synchronous clock signal to the synchronous clock signal receiver.

2. The synchronous clock signal generating circuit according to claim 1, characterized in that: The asynchronous clock sampling circuit includes a first OR gate circuit, and the first OR gate circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor; The source and substrate of the first PMOS tube and the second PMOS tube are both electrically connected to the positive electrode of the power supply, the drain of the first PMOS tube is electrically connected to the source of the third PMOS tube, the drain of the third PMOS tube is electrically connected to the drain of the first NMOS tube, the substrate of the third PMOS tube is electrically connected to the positive electrode of the power supply, the source and substrate of the first NMOS tube, the second NMOS tube and the third NMOS tube are both electrically connected to the negative electrode of the power supply, the drain of the third NMOS tube is electrically connected to the drain of the first NMOS tube, the gates of the first PMOS tube and the third NMOS tube are interconnected and serve as the first input end of the asynchronous clock sampling circuit, the third PMOS tube and the gate of the first NMOS tube are interconnected and serve as the second input end of the asynchronous clock sampling circuit, the gates of the second PMOS tube and the second NMOS tube are both electrically connected to the drain of the third NMOS tube, the drains of the second PMOS tube and the second NMOS tube are interconnected and serve as the output end of the asynchronous clock sampling circuit.

3. The synchronous clock signal generating circuit according to claim 1, characterized in that: The first-level high-level pulse extension circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fourth NMOS tube and a fifth NMOS tube; The first end of the first inverter and the gate of the fifth NMOS tube are both electrically connected to the output end of the asynchronous clock sampling circuit, the second end of the first inverter is electrically connected to the first end of the second inverter, the second end of the second inverter is electrically connected to the first end of the third inverter, the second end of the third inverter is electrically connected to the first end of the fourth inverter, the second end of the fourth inverter is electrically connected to the input end of the secondary high-level pulse extension circuit, the third end and the fourth end of the first inverter, the second inverter, the third inverter and the fourth inverter are respectively electrically connected to the positive electrode and the negative electrode of the power supply, the gate of the fourth NMOS tube is electrically connected to the second end of the second inverter, the source, the drain and the substrate of the fourth NMOS tube are all electrically connected to the negative electrode of the power supply, the drain of the fifth NMOS tube is electrically connected to the second end of the third inverter, and the source and the substrate of the fifth NMOS tube are all electrically connected to the negative electrode of the power supply.

4. The synchronous clock signal generating circuit according to claim 3, characterized in that: The first inverter, the second inverter, the third inverter and the fourth inverter each include a fourth PMOS tube and a sixth NMOS tube; The source and substrate of the fourth PMOS tube are both electrically connected to the positive electrode of the power supply, the gate of the fourth PMOS tube and the sixth NMOS tube are interconnected and serve as the first end of the inverter, the drain of the fourth PMOS tube and the drain of the sixth NMOS tube are interconnected and serve as the second end of the inverter, and the source and substrate of the sixth NMOS tube are both electrically connected to the negative electrode of the power supply.

5. The synchronous clock signal generating circuit according to claim 1, characterized in that: The secondary high-level pulse extension circuit comprises a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a seventh NMOS tube, an eighth NMOS tube and a resistor; The first end of the fifth inverter and the gate of the eighth NMOS tube are electrically connected to the output end of the first-level high-level pulse extension circuit, the second end of the fifth inverter is electrically connected to the first end of the sixth inverter, the second end of the sixth inverter is electrically connected to the first end of the seventh inverter, the second end of the seventh inverter is electrically connected to the first end of the eighth inverter, the second end of the eighth inverter is electrically connected to the first end of the ninth inverter, the second end of the ninth inverter is electrically connected to the input end of the waveform integration circuit, the fifth inverter and the sixth inverter are electrically connected to the first end of the sixth inverter, the second end of the sixth inverter is electrically connected to the first end of the seventh inverter, the second end of the eighth inverter is electrically connected to the first end of the ninth inverter, the second end of the ninth inverter is electrically connected to the input end of the waveform integration circuit, and the fifth inverter and the sixth inverter are electrically connected to the first end of the sixth inverter. The third end and the fourth end of the seventh inverter, the eighth inverter and the ninth inverter are electrically connected to the positive electrode and the negative electrode of the power supply respectively, the gate of the seventh NMOS tube is electrically connected to the second end of the sixth inverter, the source, the drain and the substrate of the seventh NMOS tube are electrically connected to the negative electrode of the power supply, the drain of the eighth NMOS tube is electrically connected to the second end of the seventh inverter, the source and the substrate of the eighth NMOS tube are electrically connected to the negative electrode of the power supply, one end of the resistor is electrically connected to the second end of the sixth inverter, and the other end of the resistor is electrically connected to the negative electrode of the power supply.

6. The synchronous clock signal generating circuit according to claim 5, characterized in that: It also includes a pulse width modulation circuit, and the secondary high-level pulse edge extension circuit also includes a ninth NMOS tube, a tenth NMOS tube and an eleventh NMOS tube; The drain, source and substrate of the ninth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube are all electrically connected to the negative electrode of the power supply, the gates of the ninth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube are all electrically connected to the first end of the pulse width modulation circuit, and the second end of the pulse width modulation circuit is electrically connected to the second end of the sixth inverter.

7. The synchronous clock signal generating circuit according to claim 6, characterized in that: The pulse width modulation circuit includes a first selection circuit, a second selection circuit and a third selection circuit, the first selection circuit corresponds to the ninth NMOS transistor, the second selection circuit corresponds to the tenth NMOS transistor, the third selection circuit corresponds to the eleventh NMOS transistor, and the first selection circuit, the second selection circuit and the third selection circuit all include a transmission gate and a tenth inverter; The first end of the tenth inverter is electrically connected to the first end of the transmission gate, and the first end of the tenth inverter is also used to be electrically connected to an external selection signal generator, the second end of the tenth inverter is electrically connected to the second end of the transmission gate, the third end and the fourth end of the tenth inverter are electrically connected to the positive power supply and the negative power supply respectively, the third end of the transmission gate is electrically connected to the second end of the sixth inverter, the fourth end of the transmission gate is electrically connected to the gate of the corresponding NMOS tube, and the third end and the fourth end of the transmission gate are electrically connected to the positive power supply and the negative power supply respectively.

8. The synchronous clock signal generating circuit according to claim 7, characterized in that: The transmission gate includes a fifth PMOS tube and a twelfth NMOS tube; the gate of the twelfth NMOS tube is electrically connected to the first end of the tenth inverter, the gate of the fifth PMOS tube is electrically connected to the second end of the tenth inverter, the drain of the fifth PMOS tube and the source of the twelfth NMOS tube are both electrically connected to the second end of the sixth inverter, the source of the fifth PMOS tube and the drain of the twelfth NMOS tube are both electrically connected to the gate of the corresponding NMOS tube, the substrate of the fifth PMOS tube is electrically connected to the positive electrode of the power supply, and the substrate of the twelfth NMOS tube is electrically connected to the negative electrode of the power supply.

9. The synchronous clock signal generating circuit according to claim 1, characterized in that: The waveform integration circuit includes a second OR gate circuit and an eleventh inverter, wherein the first input end of the second OR gate circuit is electrically connected to the output end of the asynchronous clock sampling circuit, the second input end of the second OR gate circuit is electrically connected to the output end of the secondary high-level pulse expansion circuit, the output end of the second OR gate circuit is electrically connected to the first end of the eleventh inverter, and the second end of the eleventh inverter is used to be electrically connected to the synchronous clock signal receiver.

10. A method for generating a synchronous clock signal, characterized in that: Applied to the synchronous clock signal generating circuit according to any one of claims 1 to 9, the synchronous clock signal generating method comprises: The asynchronous clock sampling circuit samples the multi-channel asynchronous clock signals transmitted by the asynchronous clock signal generator to generate a pulse signal; The first-level high-level pulse edge extension circuit extends the pulse width of the high-level signal in the pulse signal to obtain a first high-level pulse edge extension signal; The secondary high-level pulse edge extension circuit extends the pulse width of the high-level signal in the first high-level pulse edge extension signal to obtain a second high-level pulse edge extension signal; The waveform integration circuit integrates the pulse signal and the second high-level pulse extension signal, and outputs a synchronous clock signal to the synchronous clock signal receiver.

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