Switch output circuit
By introducing logic AND gate and reset chip into the switch output circuit, controlling the conduction and turn-off of the MOS tube, the problem of the switch output circuit being out of control at high temperatures in the prior art is solved, and the switching output is realized precision control and effective protection of equipment systems.
Patent Information
- Application Number
- CN202411373605.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-03
AI Technical Summary
The existing switch output circuit based on MOS tubes is prone to out of control at high temperatures, the delay time accuracy of the RC delay circuit is difficult to control, and the equipment system lacks effective protection when powered on, which may lead to instant output.
A switch output circuit is designed, including a first resistor, a second resistor, a first MOS tube, a second MOS tube, a logic AND gate, a reset chip and a comparator, and the MOS tube is controlled through a multi-input and output mechanism of the logic AND gate. Conduct and turn off to achieve accurate control of switch output and ensure controllable reset time.
It effectively solves the control problem of switch output, ensures the stability of the circuit and the accuracy of delay time at high temperatures, provides effective protection for powering on the equipment system, and avoids instant output.
Smart Images
Figure CN119254210A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic circuits, and in particular to a switch output circuit. Background Art
[0002] Currently, various switch outputs are required in automobiles, and most of the solutions currently adopted are smart MOS tube solutions. Smart MOS tubes have problems such as high price, limited output power, and the inability to achieve domestic independent control.
[0003] MOS tube is used as the power device of the switch output, and the protection circuit is added to form the switch output. Such a circuit has the advantages of intelligent MOS tube with protection function, and is low-priced, simple and convenient.
[0004] At present, the control devices for overcurrent hiccup protection are mostly composed of low-power triodes, low-power MOSFETs, resistors, capacitors, etc., and the hiccup time is generally timed by an RC delay circuit composed of resistors and capacitors. The current switch output circuit based on MOS tubes mainly has the following problems: 1. Due to the influence of the leakage current of discrete devices, especially when the leakage current of high-temperature discrete devices is large, the circuit is prone to out-of-control. 2. The capacitance of the capacitor in the RC delay circuit is very different under high and low temperature conditions, and its delay time accuracy is difficult to control within the entire operating temperature range. 3. At the moment the device system is powered on, the switch output has no effective protection and there may be a momentary output. Therefore, there are technical problems in the prior art that the switch output cannot be effectively controlled and the hiccup time cannot be accurately controlled. Summary of the invention
[0005] In view of this, it is necessary to provide a switch output circuit to solve the technical problems in the prior art that the switch output cannot be effectively controlled and the hiccup time cannot be accurately controlled.
[0006] In order to solve the above technical problems, the present invention provides a switch output circuit method, comprising: A first resistor, a second resistor, a first MOS transistor, a second MOS transistor, a logic AND gate, a reset chip and a comparator; The first MOS transistor, the second MOS transistor, the logic AND gate, the reset chip and the comparator are connected in series in sequence; The first resistor is connected in parallel with the first MOS tube; One end of the second resistor is connected to the first resistor, and the other end of the second resistor is grounded.
[0007] In a possible implementation manner, the first MOS transistor is a PMOS transistor.
[0008] In a possible implementation manner, the first MOS is further connected to VPP.
[0009] In a possible implementation manner, the second MOS transistor is an NMOS transistor.
[0010] In a possible implementation manner, the first resistor is further connected to VPP.
[0011] In a possible implementation, the logic AND gate includes: an external input control signal interface.
[0012] In a possible implementation, the nRST terminal of the reset chip is connected to a logic AND gate.
[0013] In a possible implementation manner, the nMR terminal of the reset chip is connected to the output terminal of the comparator.
[0014] In a possible implementation manner, the positive input terminal of the comparator is connected to a current sensor.
[0015] In a possible implementation manner, a negative input terminal of the comparator is connected to a reference current sensor.
[0016] The beneficial effect of the present invention is as follows: the switch output circuit provided by the present invention comprises: a first resistor, a second resistor, a first MOS tube, a second MOS tube, a logic AND gate, a reset chip and a comparator; the first MOS tube, the second MOS tube, the logic AND gate, the reset chip and the comparator are connected in series in sequence; the first resistor is connected in parallel with the first MOS tube; one end of the second resistor is connected to the first resistor, and the other end of the second resistor is grounded. The present invention creatively proposes a switch output circuit, by connecting the first MOS tube, the second MOS tube, the logic AND gate, the reset chip and the comparator in series in sequence, wherein a logic AND gate is mainly added to the switch output circuit, and the logic AND gate has multiple input terminals and one output terminal. When all inputs are at a high level at the same time, the output is a high level, otherwise the output is a low level. When the comparator output is a high level, the reset chip also outputs a high level, and when the logic AND gate receives the high level output of the reset chip and the acquired control signal is also a high level, the logic AND gate outputs a high level, causing the first MOS tube to be turned on, and the first MOS tube being turned on also causes the second MOS tube to be turned on, so that the switch output KOUT is effective. In this process, the conduction and cutoff of the first MOS tube and the second MOS tube are controlled mainly by outputting high and low levels of the logic AND gate, thereby realizing the control of the switch output, so that the reset time of the reset chip can be controlled, and the hiccup time can also be controlled. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0018] Figure 1 A switch output circuit diagram provided by the present invention; Figure 2 A switching output circuit diagram based on a MOS tube (Metal Oxide Semiconductor Field Effect Transistor) is provided for one embodiment of the switching output circuit provided by the present invention. DETAILED DESCRIPTION
[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0020] In the description of the embodiments of the present application, unless otherwise specified, “plurality” means two or more than two.
[0021] The terms "including" and "having" and any variations thereof in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or equipment comprising a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules not clearly listed or inherent to these processes, methods, products or equipment.
[0022] The naming or numbering of the steps in the embodiments of the present invention does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved.
[0023] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0024] The present invention provides a switch output circuit, which is described below.
[0025] Figure 1 The switch output circuit diagram provided by the present invention includes: A first resistor 101, a second resistor 102, a first MOS transistor (Metal Oxide Semiconductor Field Effect Transistor) 103, a second MOS transistor 104, a logic AND gate 105, a reset chip 106 and a comparator 107; The first MOS transistor 103, the second MOS transistor 104, the logic AND gate 105, the reset chip 106 and the comparator 107 are connected in series in sequence; The first resistor 101 is connected in parallel with the first MOS tube 103; One end of the second resistor 102 is connected to the first resistor 101 , and the other end of the second resistor 102 is grounded.
[0026] It can be understood that the circuit is composed of a first resistor 101, a second resistor 102, a first MOS transistor 103, a second MOS transistor 104, a logic AND gate 105, a reset chip 106 and a comparator 107. The circuit has two output signals: the current current value Icut output by the switch obtained by the sensor, and the control signal CTL input by the external control logic. KOUT output by the switch circuit.
[0027] in, Figure 1 Q1 in the middle is a PMOS tube; Q2 is a small signal NMOS tube; R1 and R2 are resistors; U1 is a logic AND gate 105; U2 is a reset chip 106 with manual reset control, where the manual reset nMR is valid at low level and the reset output nRST is valid at low level; U3 is the comparator 107 .
[0028] It should be further explained that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, and further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0029] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0030] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0031] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0032] In some embodiments of the present invention, the first MOS transistor 103 is a high-power PMOS transistor.
[0033] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0034] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0035] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0036] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0037] In some embodiments of the present invention, the first MOS is further connected to VPP (peak-to-peak voltage).
[0038] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0039] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0040] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0041] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0042] In some embodiments of the present invention, the second MOS transistor 104 is an NMOS transistor.
[0043] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0044] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0045] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0046] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0047] In some embodiments of the present invention, the first resistor 101 is further connected to VPP.
[0048] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0049] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0050] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0051] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0052] In some embodiments of the present invention, the logic AND gate 105 includes: an external input control signal interface.
[0053] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0054] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0055] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0056] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0057] In some embodiments of the present invention, the nRST terminal of the reset chip 106 is connected to the logic AND gate 105 .
[0058] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0059] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0060] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0061] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0062] In some embodiments of the present invention, the nMR terminal of the reset chip 106 is connected to the output terminal of the comparator 107 .
[0063] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0064] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0065] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0066] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0067] In some embodiments of the present invention, the non-inverting input terminal of the comparator 107 is connected to a current sensor.
[0068] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0069] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0070] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0071] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0072] In some embodiments of the present invention, the negative input terminal of the comparator 107 is connected to a reference current sensor.
[0073] It can be understood that, when powered on, since the reset chip 106 is powered on and reset, its output nRST is low level, further, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is low level, the second MOS transistor 104 is turned off, the first MOS transistor 103 is turned off, and the switch output KOUT has no output. After power-on is completed, the nRST output is high level, releasing the control right of the logic AND gate 105, and the second MOS transistor 104 can be controlled to be turned on or off by the control signal CTL.
[0074] It should be further explained that when the system is operating normally, the current current Icut is less than the current reference, the comparator 107 outputs a high level, the reset chip 106 with manual reset control outputs a high level, and the nRST pin of the reset chip 106 with manual reset control outputs a high level. When the control signal CTL is at a high level, the logic AND gate 105 outputs a high level, the second MOS tube 104 is turned on, causing the first MOS tube 103 to be turned on, and the switch output KOUT is valid; when the control signal CTL is at a low level, the logic AND gate 105 outputs a low level, the second MOS tube 104 is turned off, the first MOS tube 103 is turned off, and the switch output KOUT is invalid.
[0075] It needs to be further explained that, when the output is overcurrent, the current current Icut is higher than the current reference, causing the comparator 107 to output a low level, which is transmitted to the nMR pin of the reset chip 106 with manual reset control, causing the nRST output of the reset chip 106 with manual reset control to output a low level. At this time, no matter what the value of the control signal CTL is, the output of the logic AND gate 105 is a low level, causing the second MOS tube 104 to be turned off and the first MOS tube 103 to be turned off.
[0076] It should be further explained that, since the reset time of the reset chip 106 with manual reset control is controllable, the hiccup time is controllable.
[0077] Figure 2 A switching output circuit diagram based on a MOS tube of one embodiment of the switching output circuit provided by the present invention includes: Understandably, Figure 2 It is the prior art, and the prior art mainly has the following problems: 1. Due to the influence of the leakage current of discrete devices, especially when the leakage current of high-temperature discrete devices is large, the circuit is prone to out-of-control.
[0078] 2. The capacitance of the capacitor in the RC delay circuit varies greatly at high and low temperatures, and the delay time accuracy is difficult to control within the entire operating temperature range.
[0079] 3. When the device system is powered on, the switch output has no effective protection and there may be momentary output.
[0080] The switching output circuit provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.
Claims
1. A switching output circuit, characterized in that: include: A first resistor, a second resistor, a first MOS transistor, a second MOS transistor, a logic AND gate, a reset chip and a comparator; The first MOS transistor, the second MOS transistor, the logic AND gate, the reset chip and the comparator are connected in series in sequence; The first resistor is connected in parallel with the first MOS tube; One end of the second resistor is connected to the first resistor, and the other end of the second resistor is grounded.
2. The switching output circuit according to claim 1, characterized in that: The first MOS tube is a PMOS tube.
3. The switch output circuit according to claim 2, characterized in that: The first MOS is also connected to VPP.
4. The switch output circuit according to claim 2, characterized in that: The second MOS tube is an NMOS tube.
5. The switch output circuit according to claim 1, characterized in that: The first resistor is also connected to VPP.
6. The switch output circuit according to claim 1, characterized in that: The logic AND gate includes: an external input control signal interface.
7. The switching output circuit according to claim 1, characterized in that: The nRST terminal of the reset chip is connected to a logic AND gate.
8. The switch output circuit according to claim 7, characterized in that: The nMR terminal of the reset chip is connected to the output terminal of the comparator.
9. The switch output circuit according to claim 1, characterized in that: The positive input terminal of the comparator is connected to the current sensor.
10. The switch output circuit according to claim 9, characterized in that: The negative input terminal of the comparator is connected to the reference current sensor.