Reconnaissance and interference integrated multichannel broadband radio frequency microsystem

Abstract

The invention relates to the technical field of radio detection, in particular to a multichannel broadband radio frequency microsystem integrating reconnaissance and interference, which comprises a radio frequency transceiving circuit, a power supply circuit, an amplifier, a filter, an interface and an antenna, the radio frequency transceiver circuit is used for receiving an external broadband radio signal and transmitting a broadband interference signal, the broadband interference signal is transmitted to the antenna after passing through the amplifier and the filter, and the antenna transmits the broadband interference signal to the antenna after receiving the external broadband radio signal. The external broadband radio signal is transmitted to the radio frequency transceiver circuit through the filter and the amplifier, and the power supply circuit is used for supplying power to the radio frequency transceiver circuit, the amplifier and the filter. According to the invention, a plurality of independent radio frequency receiving channels are adopted to receive and digitize communication signals, and a same-frequency interference cancellation technology of a digital domain and subsequent algorithm optimization and iteration can be realized.

Description

Technical Field

[0001] The present invention relates to the field of radio detection technology, and in particular to a multi-channel broadband radio frequency microsystem integrating reconnaissance and interference, which is one of the key technologies in electromagnetic signal perception and countermeasure technology. Background Art

[0002] Traditional RF modules have problems such as insufficient frequency bandwidth and insufficient integration, which requires the use of multiple sets of RF channel components to achieve ultra-wideband spectrum detection. For example, the receiving channel of traditional electromagnetic spectrum equipment usually uses multiple RF channel components of different frequency bands to achieve coverage of multiple frequency bands through board-level integration. This method brings more complex electromagnetic compatibility problems. The channels are isolated by cavity isolation, which is difficult to implement, complex in structure, and heavy. Taking into account the power amplifier components, the transmitting channel usually uses multiple RF modules to cover multiple frequency bands by physical splicing, which also leads to large volume and weight. At the same time, traditional RF channels require multiple levels of circuits to complete the RF signal to digital IQ, which is difficult to isolate digital and analog, and it is difficult to support the intelligence and adaptability of the system.

[0003] In order to realize the lightweight design of broadband RF receivers, with the continuous development of RF integrated circuit technology and CMOS process technology, broadband RF transceiver systems have gradually shifted from the original PCB circuit board level integration of discrete components to the single-chip integration solution of highly integrated SoC. In 2009, J.David Irwin's research team used 0.13um SiGe BiCMOS process to design a superheterodyne receiver that can receive 8-18GHz RF signals. The chip size is only 1.5mm×1.3mm and the power consumption is about 0.18W. In 2013, the research team of the University of Electronic Science and Technology of China developed an ultra-wideband receiver based on a superheterodyne secondary frequency conversion structure. The receiver divides the RF signal into different frequency bands through 6 frequency bands, uses RF open tubes for channel selection, and can convert the RF input signal of 10MHz-12GHZ to the intermediate frequency output of 190MHz, thereby realizing an ultra-wideband RF receiver. In 2015, Shawn SHHsu's research team designed a low-power, low-noise X-band receiver based on the 90nm COMS process. The chip integrates LNA, mixer and intermediate frequency amplifier, and can receive RF signals in the frequency range of 8-12GHz. In addition, Analog Devices, Inc., a leading foreign chip supplier, has achieved mature commercial use of 30MHz-6GHz broadband RF transceiver SoC (ADRV9003). The chip integrates an independent RF transmission channel and two multiplexed receiving channels (supporting time division multiplexing or frequency division multiplexing). The maximum communication bandwidth of the chip is 40MHz, the package size is 12mm×12mm, and the maximum power consumption at full power is 2W. In 2018, the research team of Nanjing University of Posts and Telecommunications designed a 30MHz-8GHZ ultra-wideband receiver. The receiver divides the receiving frequency into two frequency bands, 30MHz-3GHz and 3GHz-8GHz, and receives them separately through two different receiving channels. In 2021, Professor Xu Jun's team at the University of Electronic Science and Technology of China used commercial RF microwave chips and components from Analog Devices Inc. to design and develop an ultra-wideband receiver with an RF reception range of nearly 40GHz.

[0004] The above-mentioned existing technical solutions at home and abroad all use RF transceiver components and chips for PCB board-level integration, and complete the overall design of the RF transceiver system by reasonably designing the impedance matching and isolation between chips, but there are still problems such as complex structure and susceptibility to interference. Therefore, the present invention proposes a multi-channel broadband RF microsystem that integrates reconnaissance and interference, and uses domestic broadband RF transceiver device SoC to complete the research and design of electromagnetic spectrum broadband detection and interference, which greatly simplifies the design of RF channel components, and can achieve full frequency band coverage without the combination of multiple RF components, and also avoids the complex electromagnetic isolation problem, realizes the integration and miniaturization of RF channels, reduces the volume and weight of RF components, and thus realizes the miniaturization of electromagnetic spectrum equipment; at the same time, the same-frequency interference cancellation technology in the digital domain of the chip and the multi-channel phase self-calibration technology are adopted, so that the equipment always maintains good performance in different environments, and the spectrum detection accuracy is not affected by temperature, etc., eliminating the trouble of frequent calibration of spectrum equipment. Summary of the invention

[0005] The purpose of the present invention is to provide a multi-channel broadband radio frequency microsystem integrating reconnaissance and interference, which adopts multiple independent radio frequency receiving channels to receive and digitize communication signals, and can realize the same-channel interference cancellation technology in the digital domain and the subsequent algorithm optimization and iteration.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A multi-channel broadband radio frequency microsystem integrating reconnaissance and interference, comprising: a radio frequency transceiver circuit, a power supply circuit, an amplifier, a filter, an interface and an antenna, wherein the interface is used to connect to the outside, the radio frequency transceiver circuit is used to receive external broadband radio signals and transmit broadband interference signals, the broadband interference signal is transmitted to the antenna after passing through the amplifier and the filter, after the antenna receives the external broadband radio signal, it transmits the external broadband radio signal to the radio frequency transceiver circuit through the filter and the amplifier, and the power supply circuit is used to power the radio frequency transceiver circuit, the amplifier and the filter.

[0008] Optionally, the RF transceiver circuit includes a broadband RF interference subsystem and a broadband multi-channel RF receiving subsystem, wherein the broadband RF interference subsystem includes a broadband RF transmission channel for transmitting the broadband interference signal, and the broadband multi-channel RF receiving subsystem includes a plurality of independent broadband RF receiving channels for multi-channel reception of the external broadband radio signal.

[0009] Optionally, the broadband RF interference subsystem and the broadband multi-channel RF receiving subsystem are both constructed using a low phase noise phase-locked loop, an FPGA chip and a SoC chip. The low phase noise phase-locked loop is directly connected to the FPGA chip to provide a clock signal for the FPGA chip. The low phase noise phase-locked loop provides a reference clock output through ClockBuf to provide a clock signal for the SoC chip.

[0010] Optionally, the broadband radio frequency interference subsystem adopts one radio frequency transmission SoC chip, and the broadband multi-channel radio frequency receiving subsystem adopts several radio frequency receiving SoC chips.

[0011] Optionally, the FPGA chip includes a high-speed digital interface for realizing data transmission between the broadband radio frequency interference subsystem and the broadband multi-channel radio frequency receiving subsystem and the FPGA chip.

[0012] Optionally, the amplifier includes a power amplifier and a low-noise amplifier, the power amplifier is used to amplify the power of the transmitted broadband interference signal to a preset range; the low-noise amplifier is used to amplify the low-power electromagnetic waves in the received external broadband radio signal to within the sensitivity range of the RF receiving SoC chip.

[0013] Optionally, the system further comprises a phase calibration signal generating module, and the phase calibration signal generating module is used to perform phase synchronization calibration on a plurality of receiving channels in the system by transmitting a calibration signal.

[0014] The beneficial effects of the present invention are:

[0015] The present invention adopts multiple independent RF receiving channels to receive and digitize communication signals, provides a friendly digital interface and a universal hardware architecture for countering complex interference and electromagnetic countermeasure algorithms, and can realize the same-frequency interference cancellation technology in the digital domain and the subsequent algorithm optimization and iteration; relying on the studied broadband RF microsystem, a variety of electronic countermeasure strategies can be flexibly deployed to compensate for the targeted interference of small-scale non-cooperative targets outside the main lobe range of large electronic countermeasure arrays.

[0016] Compared with the traditional broadband RF communication system, the core device used in the present invention is a domestic broadband RF communication SoC, which integrates LNA / PA, filter, orthogonal mixer, ADC / DAC, digital signal conditioning and back-end high-speed digital interface and other functions, and can conveniently realize the required functions of lightweight design and test verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 This is a schematic diagram of the hardware structure of a multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming according to an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of the structure of a broadband radio frequency interference subsystem according to an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of the structure of a broadband multi-channel radio frequency receiving subsystem according to an embodiment of the present invention;

[0021] Figure 4 This is a flow chart of phase self-calibration of a multi-channel receiving system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] This embodiment provides a multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming, the hardware structure of which is as follows: Figure 1 As shown, it includes: a radio frequency transceiver circuit, a power supply circuit, an amplifier, a filter, an interface and an antenna, wherein the interface is used to connect to the outside, the radio frequency transceiver circuit is used to receive external broadband radio signals and transmit broadband interference signals, the broadband interference signal is transmitted to the antenna after passing through the amplifier and the filter, after the antenna receives the external broadband radio signal, it transmits the external broadband radio signal to the radio frequency transceiver circuit through the filter and the amplifier, and the power supply circuit is used to power the radio frequency transceiver circuit, the amplifier and the filter.

[0025] Furthermore, the RF transceiver circuit includes a broadband RF interference subsystem and a broadband multi-channel RF receiving subsystem, wherein the broadband RF interference subsystem includes a broadband RF transmission channel for transmitting broadband interference signals, and the broadband multi-channel RF receiving subsystem includes a plurality of independent broadband RF receiving channels for multi-channel reception of external broadband radio signals.

[0026] Among them, the broadband RF interference subsystem and the broadband multi-channel RF receiving subsystem are both built with low phase noise phase-locked loop, FPGA chip and SoC chip. The low phase noise phase-locked loop is directly connected to the FPGA chip to provide a clock signal for the FPGA chip. The low phase noise phase-locked loop provides a reference clock output through ClockBuf to provide a clock signal for the SoC chip.

[0027] The broadband RF jammer subsystem uses one RF transmitting SoC chip, and the broadband multi-channel RF receiving subsystem uses several RF receiving SoC chips.

[0028] The FPGA chip includes a high-speed digital interface for realizing data transmission between the broadband radio frequency interference subsystem and the broadband multi-channel radio frequency receiving subsystem and the FPGA chip.

[0029] The amplifier includes a power amplifier and a low-noise amplifier. The power amplifier is used to amplify the power of the transmitted broadband interference signal to a preset range; the low-noise amplifier is used to amplify the low-power electromagnetic waves in the received external broadband radio signal to within the sensitivity range of the RF receiving SoC chip.

[0030] Specifically, in this embodiment, the broadband multi-channel RF receiving subsystem needs to have multiple independent RF receiving channels, and the broadband RF interference subsystem has two RF transmitting channels.

[0031] Broadband RFI Subsystem:

[0032] The domestic RF transmission SoC chip is used to complete the design of the required broadband RF interference subsystem. According to the function of the SoC chip and the indicator requirements of the RF transmission link, the basic architecture of the broadband RF interference subsystem is as follows: Figure 2 As shown in the figure. The broadband RF jammer subsystem has two broadband RF transmission paths with an output power of 0dBm to transmit broadband jammer signals, namely: RFTx0 and RFTx1. At the same time, the broadband RF jammer subsystem uses FPGA to design a high-speed digital interface to realize data transmission between the digital signal processing subsystem in the FPGA and the RF transmission SoC, including chip control data, communication data, and jammer signals.

[0033] The main interface descriptions in the broadband RF interference subsystem are shown in Table 1.

[0034] Table 1

[0035]

[0036] Inside the broadband RF jammer subsystem, the crystal oscillator is connected to a low phase noise phase-locked loop (PLL) to provide a stable reference clock for the internal circuits. The PLL can also receive an external clock signal to synchronize the clock with other modules. In the internal connection, the PLL is directly connected to the FPGA to provide a clock signal for the FPGA, and a 100MHz reference clock output is provided through the ClockBuf, as well as a clock signal for the RF SoC.

[0037] This embodiment uses Xilinx's FPGA chip to design a high-speed digital interface between the broadband radio frequency microsystem and the digital signal processing subsystem. Among them, the network port of the FPGA is used to complete the control signal transmission and reception of the SoC chip, and the digital information transmitted by the broadband radio frequency microsystem is input through the optical port of the FPGA (including communication data and interference data). Xilinx's FPGA supports a standard optical fiber interface with the Aurora protocol, which can easily achieve docking with the digital signal subsystem.

[0038] The RF SoC uses a highly integrated broadband RF transmitter chip, which integrates two complete transmission channels on a single chip, including mixer (MIXER), voltage-controlled gain amplifier (VGA), digital-to-analog converter (DAC), digital up-conversion (DUC) and JESD204B interface and other functions. The chip also has a built-in low-phase noise phase-locked loop (PLL) to provide a sampling clock for the built-in DAC. The RF SoC adopts a high-intermediate frequency superheterodyne transmitter architecture with an on-chip tunable low-pass filter. The two-channel DAC can achieve 2000Msps14-bit sampling, and the maximum signal bandwidth can reach 200M.

[0039] Then, the 0.4-6 GHz link filter connected behind the SoC is designed and implemented using a multi-stage separation filter or an integrated filter to provide the necessary out-of-band suppression for the broadband RF microsystem.

[0040] After passing through the filter, there are two 0dBm microwave signals, one of which is directly output to the outside of the broadband RF interference subsystem, and is amplified by an external power amplifier module and then output to the antenna end; the other is connected to the RF receiving subsystem for phase self-calibration.

[0041] Wideband multi-channel RF receiving subsystem:

[0042] The domestic RF transmitter SoC chip is used to complete the design of the required broadband multi-channel RF receiving subsystem. According to the function of the SoC chip and the design requirements of the peripheral circuit, the basic architecture of the broadband multi-channel RF receiving subsystem is as follows: Figure 3The broadband multi-channel RF receiving subsystem can cascade multiple RF receiving SoC chips according to the number of channels required to achieve the design of the required multi-channel receiving system. Figure 3 There are 8 independent RF receiving channels, namely: RFRx0 ~ RFRx7. At the same time, the system uses FPGA to design a high-speed digital interface to realize data transmission between the digital signal processing subsystem in FPGA and the multi-channel RF receiving system, including: chip control data and communication data.

[0043] The main interface description of the broadband multi-channel RF receiving subsystem is shown in Table 2.

[0044] Table 2

[0045]

[0046] The logic and physical connection of the clock part in the receiving system are the same as those in the broadband RF interference subsystem. The RF part (RF SoC) is connected to the digital processing part (FPGA) through a high-speed digital signal interface. The network port of the FPGA is used to complete the control signal transmission and reception of the multi-channel RF receiving SoC chip, and the digital information received by the broadband multi-channel RF receiving subsystem is output to the digital signal processing subsystem through the optical port of the FPGA. The broadband multi-channel RF receiving subsystem is implemented by connecting four RF SoC receiving chips in parallel, and multi-channel reception is completed by clock synchronization of the RF SoC. There is also an LNA gain component for the RF receiving link at the receiving front end to amplify the low-power electromagnetic waves in the space to within the sensitivity range of the RF receiver.

[0047] Furthermore, the system also includes a phase calibration signal generating module, which is used to perform phase synchronization calibration on a plurality of receiving channels in the system by transmitting a calibration signal.

[0048] Specifically, channel phase self-calibration:

[0049] The system internal phase self-calibration technology relies on the generation of a dedicated phase calibration signal generation module inside the system to achieve system internal phase self-calibration by generating a known self-calibration loop. The self-calibration loop of this embodiment is as follows Figure 4 shown.

[0050] In terms of calibration, the FPGA controls the channel transmitter through a high-speed digital signal interface to transmit a signal from the internal phase self-calibration channel, and receives the signal from the receiving channel at the same time (and the distance between the transmitting channel and each receiving channel is equal to ensure that the initial phase of the signal is consistent when entering each receiving channel), and the receiving channel returns the received signal through the high-speed digital signal interface, and the FPGA completes the channel phase self-calibration through relevant algorithms.

[0051] Firstly, the self-calibration signal forms stable phase self-calibration information between the receiving channels of the system through the power distribution network and coupling design.

[0052] Then, the phase self-calibration algorithm completes the calibration of the channel phase synchronization by calibrating the signal and the phase analysis of the receiving channel. At the same time, according to the changes in the working environment of the system, the internal self-calibration loop of the system can complete the real-time calibration of the phase error between the channels of the system online to ensure the stability and accuracy of the channel phase calibration matrix.

[0053] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming, characterized in that: include: A radio frequency transceiver circuit, a power supply circuit, an amplifier, a filter, an interface and an antenna, wherein the interface is used to connect to the outside, the radio frequency transceiver circuit is used to receive external broadband radio signals and transmit broadband interference signals, the broadband interference signal is transmitted to the antenna after passing through the amplifier and the filter, after the antenna receives the external broadband radio signal, it transmits the external broadband radio signal to the radio frequency transceiver circuit through the filter and the amplifier, and the power supply circuit is used to power the radio frequency transceiver circuit, the amplifier and the filter.

2. The multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming according to claim 1 is characterized in that: The RF transceiver circuit includes a broadband RF interference subsystem and a broadband multi-channel RF receiving subsystem, wherein the broadband RF interference subsystem includes a broadband RF transmission channel for transmitting the broadband interference signal, and the broadband multi-channel RF receiving subsystem includes a plurality of independent broadband RF receiving channels for multi-channel reception of the external broadband radio signal.

3. The multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming according to claim 2 is characterized in that: The broadband RF interference subsystem and the broadband multi-channel RF receiving subsystem are both constructed using a low phase noise phase-locked loop, an FPGA chip and a SoC chip. The low phase noise phase-locked loop is directly connected to the FPGA chip to provide a clock signal for the FPGA chip. The low phase noise phase-locked loop provides a reference clock output through ClockBuf to provide a clock signal for the SoC chip.

4. The multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming according to claim 3 is characterized in that: The broadband radio frequency interference subsystem adopts one radio frequency transmission SoC chip, and the broadband multi-channel radio frequency receiving subsystem adopts several radio frequency receiving SoC chips.

5. The multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming according to claim 3 is characterized in that: The FPGA chip includes a high-speed digital interface for realizing data transmission between the broadband radio frequency interference subsystem and the broadband multi-channel radio frequency receiving subsystem and the FPGA chip.

6. The multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming according to claim 1 is characterized in that: The amplifier includes a power amplifier and a low noise amplifier. The power amplifier is used to amplify the power of the transmitted broadband interference signal to a preset range; the low noise amplifier is used to amplify the low-power electromagnetic waves in the received external broadband radio signal to within the sensitivity range of the RF receiving SoC chip.

7. The multi-channel broadband radio frequency microsystem integrating reconnaissance and jamming according to any one of claims 1 to 6, characterized in that: The system further comprises a phase calibration signal generating module, and the phase calibration signal generating module is used to perform phase synchronization calibration on a plurality of receiving channels in the system by transmitting a calibration signal.

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