Satellite-borne broadband communication transceiving system

Abstract

The invention relates to the field of spaceflight measurement and control communication, in particular to a satellite-borne broadband communication transceiving system. Comprising an interface module, an interface circuit, a radio frequency agility circuit, a high-speed ADDA circuit, a master control FPGA, a communication FPGA, a DSP, a power management circuit and a clock management circuit. The interface module is connected with the interface circuit, the radio frequency agility circuit, the master control FPGA, the communication FPGA, the DSP, the power management circuit and the clock management circuit. The interface circuit is connected with the master control FPGA; the master control FPGA is respectively connected with the communication FPGA, the DSP, the high-speed ADDA circuit, the power management circuit and the clock management circuit; the high-speed ADDA circuit is connected with the radio frequency agility circuit, the power management circuit and the clock management circuit; the communication FPGA is connected with the DSP, the power management circuit and the clock management circuit; and the DSP is connected with the power management circuit and the clock management circuit. The broadband multi-mode communication device is suitable for the frequency band of 0.7-31 GHz, broadband multi-mode communication can be selected, the clock can be configured, satellite-borne broadband radio frequency direct sampling and on-orbit refreshing reconstruction are supported, and the broadband multi-mode communication device has the advantages of multiple channels and flexible application.

Description

Technical Field

[0001] The present invention relates to the field of aerospace measurement and control communication technology, and in particular to a satellite-borne broadband communication transceiver system. Background Art

[0002] With the continuous development of satellite services, the bandwidth of high-frequency signals that need to be processed by satellite transceiver systems is getting larger and larger, which makes the satellite communication frequency band continuously increase, and also makes it more difficult to compensate for the noise and signal distortion generated by the analog-to-digital / digital-to-analog converter in the system during the conversion process from the analog domain to the digital domain (or from the digital domain to the analog domain), which seriously affects the performance of the satellite transceiver system. By moving the analog-to-digital / digital-to-analog converter in the satellite transceiver system closer to the RF end, the conversion of the signal from the analog domain to the digital domain (or from the digital domain to the analog domain) is completed earlier near the RF end, which can avoid the introduction of additional noise and signal distortion while using software algorithms to process and compensate digital signals.

[0003] At present, the sampling rate of analog-to-digital / digital-to-analog conversion technology has reached the GSPS level. The significant improvement in converter performance can provide sufficient dynamic range for satellite communications and can effectively solve targeted problems such as large mission bandwidth of payloads on satellite platforms, multiple RF transceiver channels, small space volume, and limited energy. Summary of the invention

[0004] The purpose of the present invention is to solve the shortcomings of the prior art and provide a satellite-borne broadband communication transceiver system, including an interface module, an interface circuit, a radio frequency agile circuit, a high-speed ADDA circuit, a master control FPGA, a communication FPGA, a DSP, a power management circuit and a clock management circuit:

[0005] The interface module is respectively connected to the interface circuit, the RF agile circuit, the master control FPGA, the communication FPGA, the DSP, the power management circuit, and the clock management circuit;

[0006] The interface circuit is connected to the master control FPGA;

[0007] The master control FPGA is respectively connected to the communication FPGA, the DSP, the high-speed ADDA circuit, the power management circuit, and the clock management circuit;

[0008] The high-speed ADDA circuit is respectively connected to the RF agile circuit, the power management circuit, and the clock management circuit;

[0009] The communication FPGA is connected to the DSP, the power management circuit, and the clock management circuit respectively, wherein the communication FPGA is used to process digital signals and assist the main control FPGA in completing the logic operation of the data protocol;

[0010] The DSP is connected to the power management circuit and the clock management circuit respectively, and the DSP is used to carry out algorithm operations in the data processing process to achieve high-speed data calculation.

[0011] Preferably, the interface module includes a front panel connector and a VITA backplane interface for completing remote control command input, analog telemetry output, and access to clock signals, power signals, and digital oscillator signals to achieve connectivity signals.

[0012] Preferably, the interface circuit includes a level conversion circuit and an interface, and the CAN interface, RS422 interface, LVDS interface, TTL interface and gigabit network port in the interface respectively complete interface data generation for physical layer signals and network layer data, and are used to realize physical layer interface level standard conversion and network layer data protocol transmission and reception.

[0013] Preferably, the RF agile circuit comprises a receiving channel, a transmitting channel and an electrically tunable bandpass filter, and the RF agile circuit realizes broadband mode communication based on an external local oscillator LO signal input by the VITA backplane interface, wherein the external local oscillator LO provides a carrier frequency for the transmitting channel and the receiving channel to realize broadband up-conversion and down-conversion of analog signals;

[0014] The input and output ends of the transmitting channel and the receiving channel are connected with the electrically tunable bandpass filter for completing the bandpass filtering of the channel analog signal, wherein the receiving channel is used to complete the broadband signal reception, and the electromagnetic signal interception is realized by multiplexing the receiving channel, and the transmitting channel is used to send the data information;

[0015] Among them, the electrically tunable bandpass filter supports multiple octaves and is used to realize channel bandpass filtering. The operating frequency band can cover the range of 0.7 to 31 GHz, and the instantaneous bandwidth of the filter response is narrow and the design volume is small, which effectively improves the performance and space utilization of the transceiver system.

[0016] Preferably, the main control FPGA performs protocol processing on the data information received from the onboard computer, and controls the processing and calculation flow of the data information to complete the internal input of the received data in the data information and the external output of the transmitted data in the data information. At the same time, combined with the power management circuit, the communication FPGA and the DSP are powered on and configured for management, wherein the data information includes information including mission information, tracking data, target indication data and user telemetry data.

[0017] Preferably, the power management circuit converts the external input power signal into voltage including the master FPGA, the communication FPGA, the DSP and the high-speed ADDA circuit through the VITA backplane interface, and performs current, voltage and power detection.

[0018] Preferably, the high-speed ADDA circuit includes an ADC circuit, a DAC circuit and an agile transceiver circuit:

[0019] The ADC circuit converts the received input signal from the analog domain to the digital domain;

[0020] The DAC circuit converts the transmit output signal from the digital domain to the analog domain;

[0021] The agile transceiver circuit provides channel signal reception and channel signal transmission.

[0022] Preferably, the clock management circuit includes an external clock input and a local clock input, wherein the external clock input is a clock mode in which the onboard TXCO clock is used as the clock input, and the local clock input is a clock mode in which the external clock is directly connected to the SMA radio head and the local clock is used as the working reference clock by default;

[0023] The high-speed ADDA circuit uses a clock generator as a clock input signal according to an external clock, and the master FPGA, the communication FPGA and the DSP select a local clock for direct input or an external clock combined with a clock generator to generate an input clock.

[0024] Preferably, the ADC circuit is configured in a channel mode to support high sampling frequency and line rate, and can meet wide instantaneous bandwidth applications and wide-band direct RF sampling;

[0025] The DAC circuit has a high dynamic range and fast frequency hopping capability, supports direct RF signal synthesis, can flexibly adjust the number and speed of channels, and has a fast effective DAC update rate.

[0026] Preferably, the agile transceiver circuit provides channel signal reception and channel signal transmission, and can adapt to wide bandwidth and direct RF sampling when receiving, as well as analog-to-digital conversion, power amplification and other functions, and can directly convert the output signal to the RF segment when transmitting.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1) In the power management circuit of the present invention, the external input power signal is converted into a voltage including the main control FPGA, communication FPGA, DSP and high-speed ADDA circuit through the VI TA backplane interface to achieve efficient power supply and provide current, voltage and power detection;

[0029] 2) The clock management circuit of the present invention includes an external clock input and a local clock input, and the clock can be flexibly configured through the clock management circuit;

[0030] 3) The high-speed ADDA circuit of the present invention includes an ADC circuit, a DAC circuit and an agile transceiver circuit, wherein the ADC circuit is configured in a multi-channel mode, supports high sampling frequency and line rate, can meet wide instantaneous bandwidth applications, and can realize broadband RF direct sampling;

[0031] 4) In the present invention, the main control FPGA, communication FPGA, and DSP all have the ability to be refreshed and reconstructed on-orbit, thereby enabling the on-orbit refresh and reconstruction of the satellite-borne broadband communication transceiver system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the following detailed description of the preferred embodiment.The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting the invention.

[0033] Figure 1 The present invention is a schematic diagram of a satellite-borne broadband communication transceiver system. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0035] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0036] Example

[0037] See also Figure 1 As shown, a satellite-borne broadband communication transceiver system provided in this embodiment includes an interface module, an interface circuit, a radio frequency agile circuit, a high-speed ADDA circuit, a master control FPGA, a communication FPGA, a DSP, a power management circuit, and a clock management circuit:

[0038] The interface module is respectively connected with the interface circuit, the radio frequency agile circuit, the main control FPGA, the communication FPGA, the DSP, the power management circuit, and the clock management circuit;

[0039] The interface circuit is connected to the main control FPGA;

[0040] The main control FPGA is connected to the communication FPGA, DSP, high-speed ADDA circuit, power management circuit, and clock management circuit respectively;

[0041] The high-speed ADDA circuit is respectively connected with the radio frequency agile circuit, the power management circuit, and the clock management circuit;

[0042] The communication FPGA is connected to the DSP, the power management circuit, and the clock management circuit respectively. The communication FPGA is used to process digital signals and assist the main control FPGA in completing the logic operation of the data protocol. Specifically, in this embodiment, the communication FPGA uses the XCVU9P chip to support on-track refresh and reconstruction.

[0043] The DSP is connected to the power management circuit and the clock management circuit respectively. Specifically, in this embodiment, the DSP is used to carry out algorithmic operations in the data processing process to achieve high-speed data calculation. The DSP uses the 6678 chip, which has a computing acceleration circuit, which can be used to carry out algorithmic operations in the data processing process to achieve high-speed data calculation and support on-track refresh and reconstruction.

[0044] Preferably, the interface module includes a front panel connector and a VITA backplane interface for completing remote control command input, analog telemetry output, and access to clock signals, power signals, and digital oscillator signals to achieve signal connectivity.

[0045] Preferably, the interface circuit includes a level conversion circuit and an interface, and the CAN interface, RS422 interface, LVDS interface, TTL interface and gigabit network port in the interface respectively complete interface data generation for physical layer signals and network layer data, and are used to realize physical layer interface level standard conversion and network layer data protocol transmission and reception.

[0046] Preferably, the RF agile circuit includes a receiving channel, a transmitting channel and an electrically tunable bandpass filter. The RF agile circuit realizes wideband multi-mode communication based on an external local oscillator LO signal input through a VITA backplane interface, wherein the external local oscillator LO provides a carrier frequency for the transmitting channel and the receiving channel to realize wideband up-conversion and down-conversion of analog signals. Specifically, in this embodiment, the RF agile circuit includes 4 receiving channels, 4 transmitting channels and 16 electrically tunable bandpass filters;

[0047] The input and output ends of the transmitting channel and the receiving channel are connected with an electrically tunable bandpass filter for completing the bandpass filtering of the channel analog signal, wherein the receiving channel is used to complete the broadband signal reception, and the electromagnetic signal interception is realized by multiplexing the detection channel, and the transmitting channel is used to send data information. Specifically, in this embodiment, the input and output ends of the transmitting channel and the receiving channel are all connected with an electrically tunable bandpass filter for completing the bandpass filtering of the channel analog signal, and the four receiving channels can complete the broadband signal reception, and the receiving channel 3 and the receiving channel 4 can be multiplexed as the detection channel for realizing the electromagnetic signal interception, and the transmitting channels are all used to send data information;

[0048] Among them, the electrically tunable bandpass filter supports multiple octaves and is used to realize multi-channel bandpass filtering. The operating frequency band can cover the range of 0.7 to 31 GHz, and the instantaneous bandwidth of the filter response is narrow and the design volume is small, which effectively improves the performance and space utilization of the transceiver system.

[0049] Preferably, the electrically tunable bandpass filter adopts a multi-channel YIG bandpass filter, supports multiple octaves, and the operating frequency band can cover the P~U band. The instantaneous bandwidth of the filter response is narrow and has no parasitic passband. The design is small in size but has multiple interface forms, which can greatly reduce the size and weight of the transceiver system.

[0050] Preferably, the main control FPGA performs protocol processing on the data information received from the onboard computer, and controls the processing and calculation flow of the data information to complete the internal input of the received data in the data information and the external output of the transmitted data in the data information. At the same time, the power management circuit is combined to perform power-on configuration management on the communication FPGA and DSP, wherein the data information includes information including mission information, tracking data, target indication data and user telemetry data. Specifically, in this embodiment, the main control FPGA selects the XC7VX690T chip, which is mainly used to receive data information from the onboard computer.

[0051] Preferably, the power management circuit converts the external input power signal into voltage including the main control FPGA, communication FPGA, DSP and high-speed ADDA circuit through the VITA backplane interface, and performs current, voltage and power detection. Specifically, in this embodiment, the power management circuit converts the +12V voltage provided by the secondary power supply through the VITA backplane to provide board-level input voltage for the main control FPGA, communication FPGA, DSP and high-speed ADDA circuit, and redistributes the required voltage according to the internal chip conditions of each circuit.

[0052] Preferably, the high-speed ADDA circuit includes an ADC circuit, a DAC circuit and an agile transceiver circuit:

[0053] The ADC circuit converts the received input signal from the analog domain to the digital domain;

[0054] The DAC circuit converts the transmit output signal from the digital domain to the analog domain;

[0055] The agile transceiver circuit provides multi-channel signal reception and multi-channel signal transmission.

[0056] Preferably, the clock management circuit includes an external clock input and a local clock input. The external clock input is a clock mode in which the onboard TXCO clock is used as the clock input. The local clock input is a clock mode in which the external clock is directly input through the SMA radio head and the local clock is used as the working reference clock by default. Specifically, in this embodiment, the external clock is 40MHz.

[0057] Among them, the high-speed ADDA circuit uses a clock generator as a clock input signal according to an external clock, and the master FPGA, communication FPGA and DSP select the local clock to be directly input or the external clock to be combined with the clock generator to generate the input clock. Specifically, in this embodiment, the high-speed ADDA circuit uses two HMC7044 (clock generators) as the clock input signal based on the external clock, and the master FPGA, communication FPGA and DSP use the local clock and the external clock at the same time, and select the local clock to be directly input or the external clock to be combined with the clock generator to generate the input clock as needed.

[0058] Preferably, the ADC circuit is configured with a multi-channel mode, supports high sampling frequency and line rate, can meet wide instantaneous bandwidth applications, and wide-band direct RF sampling. Specifically, in this embodiment, the ADC circuit core device uses the ADC12DJ5200 chip, which can be configured with single / dual channel modes. The sampling frequency can reach 10.4GSPS in single-channel mode and 5.2GSPS in dual-channel mode. It can support 16 serial channels and has a line rate of up to 17.16Gbps, supports an available input frequency range of up to 10GHz, can meet wide instantaneous bandwidth applications, and can perform direct RF sampling on RF signals;

[0059] The DAC circuit has a high dynamic range and fast frequency hopping capability, supports direct RF signal synthesis, can flexibly adjust the number and speed of channels, and has a fast effective DAC update rate. Specifically, in this embodiment, the core component of the DAC circuit uses the AD9164 chip, which has a high dynamic range and fast frequency hopping capability, a signal reconstruction bandwidth of up to 7.5GHz, supports 6GSPS direct RF signal synthesis, includes an 8-channel SERDES interface, can flexibly adjust the number and speed of channels, and can provide a maximum effective DAC update rate of 12GSPS.

[0060] Preferably, the agile transceiver circuit provides channel signal reception and channel signal transmission, and can adapt to wide bandwidth and direct RF sampling, as well as analog-to-digital conversion, power amplification and other functions when receiving. When transmitting, it can directly convert the output signal to the RF segment. Specifically, in this embodiment, the agile transceiver circuit uses the ADRV9009 chip, which can provide dual-channel transceiver function. The chip receiver can adapt to wide bandwidth and direct RF sampling, as well as analog-to-digital conversion, power amplification and other functions. The chip transmitter can directly convert the output signal to the RF segment while achieving high modulation accuracy and extremely low noise, and the overall performance is low power consumption.

[0061] The specific process of satellite-borne broadband communication reception and transmission in this embodiment is as follows: in the receiving channel, the analog signal connected to the interface module is first band-filtered by an electrically tuned bandpass filter, and then RF down-converted and filtered again under the control of the external input local oscillator LO. Under the control of the main control FPGA, the filtered intermediate frequency analog signal is converted to the digital domain through an analog-to-digital converter in a high-speed ADDA circuit. The obtained digital signal is forwarded to the communication FPGA and DSP through a high-speed serial port under the control of the main control FPGA for calculation and processing, so as to realize feature extraction of the digital signal, and form complete data information at the main control FPGA, which is processed by the interface circuit and transmitted to the external information processing module through the interface module to complete data processing and forwarding;

[0062] In the transmitting channel, that is, in the transmitting state, the external information processing module transmits data information to the interface circuit through the interface module, and then forwards it to the main control FPGA after processing. The main control FPGA sends the data control to the communication FPGA and DSP based on the high-speed serial port to jointly complete the data coding and modulation, and then the main control FPGA forwards it to the high-speed ADDA circuit, uses the digital-to-analog converter to obtain the intermediate frequency analog signal, and combines the external input local oscillator LO signal and the bandpass filter in the RF agile circuit to complete the frequency conversion process of the intermediate frequency signal to the RF segment and the signal filtering before and after the frequency conversion, thereby realizing the generation of the RF signal.

[0063] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A satellite-borne broadband communication transceiver system, characterized in that: Including interface module, interface circuit, RF agile circuit, high-speed ADDA circuit, master control FPGA, communication FPGA, DSP, power management circuit and clock management circuit: The interface module is respectively connected to the interface circuit, the RF agile circuit, the master control FPGA, the communication FPGA and the DSP, the power management circuit, and the clock management circuit; The interface circuit is connected to the master control FPGA; The master control FPGA is respectively connected to the communication FPGA, the DSP, the high-speed ADDA circuit, the power management circuit, and the clock management circuit; The high-speed ADDA circuit is respectively connected to the RF agile circuit, the power management circuit, and the clock management circuit; The communication FPGA is connected to the DSP, the power management circuit, and the clock management circuit respectively, wherein the communication FPGA is used to process digital signals and assist the main control FPGA in completing the logic operation of the data protocol; The DSP is connected to the power management circuit and the clock management circuit respectively, and the DSP is used to carry out algorithm operations in the data processing process to achieve high-speed data calculation.

2. The satellite-borne broadband communication transceiver system according to claim 1, characterized in that: The interface module includes a front panel connector and a VITA backplane interface, which are used to complete remote control command input, analog telemetry output, and access to clock signals, power signals, and digital oscillator signals to achieve signal connectivity.

3. The satellite-borne broadband communication transceiver system according to claim 1, characterized in that: The interface circuit includes a level conversion circuit and an interface. The CAN interface, RS422 interface, LVDS interface, TTL interface and gigabit network port in the interface respectively complete interface data generation for physical layer signals and network layer data, and are used to realize physical layer interface level standard conversion and network layer data protocol transmission and reception.

4. The satellite-borne broadband communication transceiver system according to claim 1, characterized in that: The RF agile circuit comprises a receiving channel, a transmitting channel and an electrically tunable bandpass filter, and the RF agile circuit realizes broadband mode communication based on an external local oscillator LO signal input by the VITA backplane interface, wherein the external local oscillator LO provides a carrier frequency for the transmitting channel and the receiving channel to realize broadband up-conversion and down-conversion of analog signals; The input and output ends of the transmitting channel and the receiving channel are connected with the electrically tunable bandpass filter for completing the bandpass filtering of the channel analog signal, wherein the receiving channel is used to complete the broadband signal reception, and the electromagnetic signal interception is realized by multiplexing the receiving channel, and the transmitting channel is used to send the data information; Among them, the electrically tunable bandpass filter supports multiple octaves and is used to realize channel bandpass filtering. The operating frequency band can cover the range of 0.7 to 31 GHz, and the instantaneous bandwidth of the filter response is narrow and the design volume is small, which effectively improves the performance and space utilization of the transceiver system.

5. The satellite-borne broadband communication transceiver system according to claim 1, characterized in that: The main control FPGA performs protocol processing on the data information received from the onboard computer and controls the processing and calculation flow of the data information to complete the internal input of the received data in the data information and the external output of the transmitted data in the data information. At the same time, combined with the power management circuit, the communication FPGA and the DSP are powered on and configured for management, wherein the data information includes information including mission information, tracking data, target indication data and user telemetry data.

6. The satellite-borne broadband communication transceiver system according to claim 1, characterized in that: The power management circuit converts the external input power signal into voltage including the main control FPGA, the communication FPGA, the DSP and the high-speed ADDA circuit through the VITA backplane interface, and performs current, voltage and power detection.

7. The satellite-borne broadband communication transceiver system according to claim 1, characterized in that: The high-speed ADDA circuit includes an ADC circuit, a DAC circuit and an agile transceiver circuit: The ADC circuit converts the received input signal from the analog domain to the digital domain; The DAC circuit converts the transmit output signal from the digital domain to the analog domain; The agile transceiver circuit provides channel signal reception and channel signal transmission.

8. The satellite-borne broadband communication transceiver system according to claim 1, characterized in that: The clock management circuit includes an external clock input and a local clock input. The external clock input is a clock mode in which the onboard TXCO clock is used as the clock input. The local clock input is a clock mode in which the external clock is directly connected to the SMA radio head and the local clock is used as the working reference clock by default. The high-speed ADDA circuit uses a clock generator as a clock input signal according to an external clock, and the master FPGA, the communication FPGA and the DSP select a local clock for direct input or an external clock combined with a clock generator to generate an input clock.

9. The satellite-borne broadband communication transceiver system according to claim 7, characterized in that: The ADC circuit is configured in channel mode to support high sampling frequency and line rate, and can meet wide instantaneous bandwidth applications and wide-band direct RF sampling; The DAC circuit has a high dynamic range and fast frequency hopping capability, supports direct RF signal synthesis, can flexibly adjust the number and speed of channels, and has a fast effective DAC update rate.

10. The onboard digital-analog hybrid communication system based on the VPX standard according to claim 9, characterized in that: The agile transceiver circuit provides channel signal reception and channel signal transmission. When receiving, it can adapt to wide bandwidth and direct RF sampling, as well as analog-to-digital conversion, power amplification and other functions. When transmitting, it can directly convert the output signal to the RF segment.

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