Time synchronization device

Abstract

The invention relates to a time synchronization device, and the device comprises an FPGA chip which is used for dividing the clock frequency of a received initial clock synchronization signal into a first clock frequency point and a second clock frequency point; the clock chip comprises a first phase-locked loop and a second phase-locked loop, and the first phase-locked loop is used for obtaining a system clock according to the first clock frequency point and sending the system clock to the second phase-locked loop; the second phase-locked loop is used for acquiring the PTP clock offset frequency according to the system clock and sending the PTP clock offset frequency to the FPGA chip; the FPGA chip comprises a pulse generator, and the pulse generator is used for generating a pulse signal per second and adjusting the phase of the pulse signal per second according to the PTP clock offset frequency, so that the phase is consistent with the pulse phase per second of the initial clock synchronization signal, and time synchronization is completed. According to the application, clock synchronization of the application equipment and the upstream equipment is realized by utilizing the FPGA chip and the clock chip.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a time synchronization device. Background Art

[0002] Precision Time Protocol (PTP) is a protocol used to achieve clock synchronization in the network. In a large network, multiple devices are involved in the coordinated operation, and these devices require a unified time reference point. Therefore, the PTP protocol is introduced as a unified time reference point.

[0003] For a device, if it needs to synchronize the time of an upstream device with high precision, it needs to synchronize the upstream clock first. Only based on the synchronized clock can the device stably synchronize the time with the upstream device. Therefore, the device includes at least one physical interface for clock frequency synchronization and one physical interface for carrying the PTP protocol. In the prior art, a chip is often used to integrate the time information and clock information from different interfaces. The time information and clock frequency of the entire device are maintained by this chip, and the time synchronization signal is sent to other chips inside the device.

[0004] Since the chip integrates the time and clock information of different interfaces, chip manufacturers can only rely on this chip for secondary opening. Chip manufacturers can only rely on the support of the chip manufacturer and cannot find other chips to replace. Therefore, how to achieve clock synchronization between two devices has become an urgent problem to be solved. Summary of the invention

[0005] The embodiment of the present application provides a time synchronization device to at least solve the problem of how to achieve clock synchronization between two devices in the related art.

[0006] In a first aspect, an embodiment of the present application provides a time synchronization device, characterized in that it includes: an FPGA chip and a clock chip electrically connected; The FPGA chip is used to divide the clock frequency of the received initial clock synchronization signal into a first clock frequency point and a second clock frequency point; The clock chip includes a first phase-locked loop and a second phase-locked loop. The first phase-locked loop is used to obtain a system clock according to the first clock frequency point, and send the system clock to the second phase-locked loop; The second phase-locked loop is used to obtain the PTP clock offset frequency according to the system clock, and send the PTP clock offset frequency to the FPGA chip; The FPGA chip includes a pulse generator, which is used to generate a pulse signal per second. The phase of the pulse signal per second is adjusted according to the PTP clock offset frequency to make the phase consistent with the pulse phase per second of the initial clock synchronization signal to complete time synchronization.

[0007] In one embodiment, the clock chip further includes: a third phase-locked loop, The third phase-locked loop is used to receive the second clock frequency and transmit the second clock frequency to the FPGA chip, so that the FPGA chip converts the second clock frequency into the first clock frequency and transmits the first clock frequency to the first phase-locked loop.

[0008] In one embodiment, the FPGA chip includes: a pulse signal compensator, a frequency controller, a register, The pulse signal compensator is electrically connected to the pulse generator, and is used to compensate for the delay of the pulse signal per second, and transmit the compensated pulse signal per second to a chip connected to the FPGA chip; A register, used to obtain the nanosecond time difference calculated by the PTP protocol message and transmit the nanosecond time difference to the frequency controller; The frequency controller is used to receive the nanosecond time difference and the pulse per second signal, and when the nanosecond time difference is less than a preset threshold, the frequency adjustment is sent to the second phase-locked loop according to the nanosecond time difference and the pulse per second signal to adjust the PTP clock offset frequency.

[0009] In one embodiment, the second phase-locked loop includes: a first oscillator and a second oscillator, A first oscillator is used to receive an adjustment frequency sent by a frequency controller and adjust the frequency according to the adjustment frequency; The second oscillator is used to obtain a PTP clock offset frequency according to the system clock and the adjusted frequency, and transmit the PTP clock offset frequency to the pulse generator.

[0010] In one embodiment, a time synchronization device further includes a device interface chip: The device interface chip includes a first rate interface and a second rate interface. A first rate interface, used to receive a clock frequency greater than or equal to a preset data transmission rate, and transmit the clock frequency to the FPGA chip, so that the FPGA chip divides the clock frequency into a first clock frequency point; The second rate interface is used to receive a clock frequency that is less than a preset data transmission rate, and transmit the clock frequency to the FPGA chip so that the FPGA chip divides the clock frequency into a second clock frequency point.

[0011] In one embodiment, a time synchronization device includes a pulse generator: The pulse generator is also used to adjust the phase of the pulse per second according to the nanosecond time difference when the nanosecond time difference is greater than or equal to a preset threshold value, so as to make the phase consistent with the pulse per second phase of the initial clock synchronization signal to complete time synchronization.

[0012] In one embodiment, the first phase-locked loop includes: a first transmission interface and a second transmission interface, A first transmission interface, used to receive a first clock frequency point so that the clock chip obtains a system clock; The second transmission interface is used to receive the first clock frequency. When the first phase-locked loop adopts the first transmission interface for receiving, the second transmission interface does not receive the first clock frequency. If the first transmission interface fails to send, the second transmission interface starts to receive the first clock frequency so that the clock chip obtains the system clock.

[0013] In one embodiment, the third phase-locked loop includes: a third transmission interface, The third transmission interface is used to receive the second clock frequency point, so that the second clock frequency point can obtain a preliminary stable second clock frequency point after being processed by the third phase-locked loop.

[0014] A time synchronization device provided by an embodiment of the present application has at least the following technical effects.

[0015] The FPGA chip divides the clock frequency of the initial clock synchronization signal received from the upstream device into the first clock frequency and the second clock frequency. The first phase-locked loop of the clock chip obtains the system clock according to the received first clock frequency, and sends the system clock system to the second phase-locked loop, obtains the PTP clock offset frequency according to the system clock, and completes the conversion from the system clock domain to the PTP clock domain on the system clock, thereby improving the clock accuracy, so that the accuracy of clock synchronization can be obtained in the sub-microsecond level, and the PTP clock offset frequency provides a basis for high-precision synchronization for clock synchronization. The pulse generator in the FPGA chip adjusts the phase of the pulse per second according to the PTP clock offset frequency, so that the phase of the generated pulse per second is the same as the phase of the pulse per second of the initial clock synchronization signal, reducing the internal time error, thereby achieving high-precision synchronization between the clock of the upstream device and the clock of this device.

[0016] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a schematic diagram of a time synchronization device according to an exemplary embodiment; Figure 2 is a schematic diagram of a time architecture according to an exemplary embodiment; Figure 3 is a schematic diagram of a clock architecture according to an exemplary embodiment.

[0018] In the above drawings, the meanings of the reference numerals are as follows: 100, initial clock synchronization signal, 101, first clock frequency, 102, second clock frequency; 200, PTP clock frequency deviation; 300, system clock; 700, FPGA chip, 701, pulse generator; 800 clock chip, 801, first phase-locked loop; 802, second phase-locked loop, 803, second phase-locked loop. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0020] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

[0021] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0022] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantity limitation, and may indicate the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0023] For any device, it often needs to work with other devices, including sharing data, transmitting data, operating coordination, and remote control. These collaborative works need to synchronize the clock of the upstream device first. Based on the synchronized clock, the device can stably and accurately synchronize the upstream time and distribute clock and time information to downstream devices, thus completing the collaborative work between devices.

[0024] In the prior art, the method for achieving clock synchronization is to integrate the collected time and clock information into a chip. The chip maintains the acquired clock information and clock frequency, and distributes the pulse signal per second to other chips in the device, thereby completing the clock synchronization of the entire device. However, with the prior art, secondary development can only be performed in the integrated chip. The chip that integrates the clock and time cannot be replaced, and first of all, the clock synchronization accuracy provided by the chip cannot achieve higher-precision clock synchronization.

[0025] Based on the above situation, an embodiment of the present application provides a time synchronization device.

[0026] In a first aspect, an embodiment of the present application provides a time synchronization device, Figure 1 is a schematic diagram of a time synchronization device according to an exemplary embodiment. Figure 1As shown, the time synchronization device includes: an FPGA chip 700 and a clock chip 800 which are electrically connected; The FPGA chip 700 is used to divide the clock frequency of the received initial clock synchronization signal 100 into a first clock frequency point 101 and a second clock frequency point 102 .

[0027] The clock chip 800 includes a first phase-locked loop 801 and a second phase-locked loop 802. The first phase-locked loop 801 is used to obtain the system clock 300 according to the first clock frequency 101 , and send the system clock 300 to the second phase-locked loop 802 .

[0028] The second phase-locked loop 802 is used to obtain the PTP clock offset 200 according to the system clock 300 and send the PTP clock offset 200 to the FPGA chip 700 .

[0029] The FPGA chip 700 includes a pulse generator 701, which is used to generate a pulse signal per second and adjust the phase of the pulse signal per second according to the PTP clock offset 200 to make the phase consistent with the pulse phase of the initial clock synchronization signal 100 per second to complete time synchronization.

[0030] This embodiment is described with an application device, which includes an FPGA chip 700 and a clock chip 800. The FPGA chip 700 includes a pulse generator 701, and the clock chip 800 includes a first phase-locked loop 801 and a second phase-locked loop 802. The upstream device sends an initial clock synchronization signal 100 to the application device, and the FPGA chip 700 in the application device receives the initial clock synchronization signal 100, and divides the clock frequency in the initial clock synchronization signal 100 into a first clock frequency 101 and a second clock frequency 102. Among them, the first clock frequency 101 and the second clock frequency 102 are numerically the same, but the first clock frequency 101 is used to transmit to the clock chip 800 to obtain the system clock 300. The specific role of the second clock frequency 102 will be described in detail later.

[0031] The clock chip 800 includes a first phase-locked loop 801 and a second phase-locked loop 802. The clock chip 800 receives the first clock frequency 101 transmitted by the FPGA chip 700, and transmits the first clock frequency 101 to the first phase-locked loop 801. Through the first phase-locked loop 801, the received first clock frequency 101 is subjected to pressure stabilization processing, that is, the output frequency is maintained at a constant level, and on the other hand, the stable output frequency is divided to meet the needs of different chips. Therefore, after the first clock frequency 101 passes through the first phase-locked loop 801, a stable system clock 300 is obtained. The system clock 300 is a time reference for synchronization of various components in the entire device. Therefore, each chip in the application device performs time synchronization based on the system clock 300.

[0032] The clock chip 800 obtains the system clock 300 from the first phase-locked loop 801, and transmits the system clock 300 to the second phase-locked loop 802. In the second phase-locked loop 802, the PTP clock offset 200 is obtained according to the system clock 300, and the conversion from the system clock domain to the PTP clock domain is realized, which provides a basis for subsequent high-precision time synchronization. The second phase-locked loop 802 sends the PTP clock offset 200 to the pulse generator 701 in the FPGA chip 700.

[0033] For the time synchronization of the application device, there are two times that need to be synchronized, one is the second information of the current moment, and the other is the nanosecond information under the current second information. Among them, the second information is generally maintained by the software of the application device or the FPGA chip 700. The nanosecond information requires the FPGA chip 700 to transmit the nanosecond information to other chips in the device through a pulse signal per second. The other chips in the device determine the 0 nanosecond moment of the current second information moment through the rising edge of the received pulse signal per second.

[0034] The pulse generator 701 is used to generate a pulse signal with specific characteristics. In the present embodiment, the pulse generator 701 is used to generate a pulse signal per second, that is, the time interval between each pulse signal is 1 second. The pulse generator 701 in the FPGA chip 700 adjusts the phase of the generated pulse signal per second according to the received PTP clock offset 200. The pulse generator 701 adjusts the phase of the pulse signal per second so that the phase of the pulse signal per second is consistent with the phase of the pulse signal per second of the initial clock synchronization signal 100, so that, in the same time period, at any time, the pulse signal in the application device is consistent with the pulse signal of the upstream device, thereby reducing the internal time difference and completing the clock synchronization.

[0035] More specifically, Figure 2 is a schematic diagram of a time architecture according to an exemplary embodiment. Figure 2As shown, the second phase-locked loop 802 of the clock chip 800 includes: a first oscillator and a second oscillator. The FPGA chip 700 includes: a pulse generator 701, a pulse signal compensator, a frequency controller, and a register. The clock chip 800 and the FPGA chip 700 jointly adjust the phase of the pulse signal per second, specifically including: The pulse signal compensator is electrically connected to the pulse generator 701 and is used to compensate for the delay of the pulse signal per second and transmit the compensated pulse signal per second to a chip connected to the FPGA chip 700 .

[0036] The register is used to obtain the nanosecond time difference calculated by the PTP protocol message and transmit the nanosecond time difference to the frequency controller.

[0037] The frequency controller is used to receive the nanosecond time difference and the pulse per second signal, and when the nanosecond time difference is less than a preset threshold, send an adjustment frequency to the second phase-locked loop 802 according to the nanosecond time difference and the pulse per second signal to adjust the PTP clock offset frequency 200.

[0038] The software of the application device calculates the time difference between the application device and the upstream device through the PTP protocol message. The time difference includes the time difference in seconds and the time difference in nanoseconds. Since the accuracy of the system clock 300 is a sub-second clock, the accuracy of sub-seconds is higher than the accuracy of seconds. If the time difference calculated is the time difference in seconds, it is synchronized to each chip in the application device through the software, and each chip can adjust the time difference in seconds through the system clock 300 to eliminate the time difference in seconds. If the time difference is a nanosecond time difference, the accuracy requirement of the nanosecond time difference is high. If the nanosecond time difference is greater than the preset threshold, the FPGA chip 700 adjusts the output phase of the pulse per second in the pulse generator 701 according to the nanosecond time difference. If the nanosecond time difference is less than or equal to the preset threshold, the frequency controller sends the adjustment frequency to the second phase-locked loop 802 of the clock chip 800 according to the received nanosecond time difference and the pulse per second signal of the pulse generator to obtain the PTP clock offset frequency 200.

[0039] For the second phase-locked loop 802, the second phase-locked loop 802 includes: a first oscillator and a second oscillator, A first oscillator is used to receive an adjustment frequency sent by a frequency controller and adjust the frequency according to the adjustment frequency; The second oscillator is used to obtain the PTP clock offset frequency 200 according to the system clock 300 and the adjusted frequency, and transmit the PTP clock offset frequency 200 to the pulse generator 701.

[0040] After the clock chip 800 generates the system clock 300, the system clock 300 of the preset frequency is sent to the second phase-locked loop 802 in the clock chip 800. When the frequency controller in the FPGA chip 700 sends the adjusted frequency to the first oscillator, the first oscillator adjusts the frequency according to the received adjusted frequency. For example, the initial frequency of the first oscillator is 5GHz, and the frequency is increased to 5.1GHz according to the frequency increase instruction sent by the frequency generator. The second oscillator obtains the PTP clock offset 200 according to the system clock 300 and the adjusted frequency, and transmits the PTP clock offset 200 to the pulse generator 701 of the FPGA chip 700. Based on the system clock 300, the second oscillator is in the same system clock 300 as the upstream device, and then adjusts the output frequency. The pulse generator 701 then fine-tunes the phase of the output pulse per second according to the PTP clock offset 200 to complete time synchronization.

[0041] In one embodiment, the preset threshold is 50 nanoseconds. If the nanosecond time difference is less than 50 nanoseconds, the register of the FPGA chip 700 transmits the nanosecond time difference of 50 nanoseconds to the frequency controller, so that the frequency controller sends a frequency increase instruction to the first oscillator in the second phase-locked loop 802 according to the 50 nanosecond time difference. The first oscillator increases the frequency and obtains the adjusted frequency. The second phase-locked loop 802 also receives the 125Mhz system clock 300, and transmits the adjusted frequency and the 125Mhz system clock 300 to the second oscillator. The second oscillator adjusts the output frequency based on the system clock 300, and sends the PTP clock offset 200 to the pulse generator 701 of the FPGA chip 700. The pulse generator 701 adjusts the phase of the pulse signal per second according to the PTP clock offset 200, so that the phase of the pulse signal per second is consistent with the phase of the initial clock synchronization signal 100 sent by the upstream device to the application device, thereby achieving time synchronization.

[0042] It should be noted that when the pulse generator 701 outputs a pulse signal per second to other chips, a pulse signal compensator is connected in series on each output path, and the pulse signal compensator is electrically connected to the pulse generator 701. The function of the pulse signal compensator is to compensate for the pin delay of the chip and the delay of the physical line in the PCB board. The delay of the hardware connection part is compensated by the pulse signal compensator, so that the clock and time of the transmission are consistent with the clock and time of the upstream device. In addition, the pulse signal compensator can also reduce the nanosecond time difference generated in the circuit when the hardware performs isochronous control on the pin delay during the PCB wiring stage, thereby ensuring time synchronization during the transmission process.

[0043] In the above manner, according to the calculated time difference, the frequency sent by the frequency controller controls the clock step, the system clock 300 is adjusted by the clock step and the PTP clock offset 200 is obtained, and the phase of the pulse per second is adjusted according to the PTP clock offset 200, so that the nanosecond information and high-precision clock synchronization are controlled by frequency. Since the phase is adjusted by frequency, the time change will not be too abrupt, so that the time change is smooth.

[0044] In order to achieve clock synchronization between the application device and the upstream device, the application device needs to receive the clock synchronization signal sent by the upstream device. However, when the application device receives the clock synchronization signal of the upstream device, the clock jitter recovered from the interface chip is large and the recovered clock is uneven, which cannot be applied to the entire application device system. Therefore, the clock synchronization signal received from the upstream device needs to be processed to obtain a stable system clock. The present application also provides a method for obtaining a stable system clock in the time synchronization device. Figure 3 is a schematic diagram of a clock architecture according to an exemplary embodiment. Figure 3 As shown, a time synchronization device includes an FPGA chip 700, a clock chip 800 and a device interface chip. The first phase-locked loop 801 of the clock chip 800 includes: a first transmission interface and a second transmission interface. The device interface chip includes a first rate interface and a second rate interface.

[0045] The first rate interface is used to receive a clock frequency greater than or equal to a preset data transmission rate, and transmit the clock frequency to the FPGA chip 700 so that the FPGA chip 700 divides the clock frequency into a first clock frequency point 101.

[0046] The second rate interface is used to receive a clock frequency that is less than a preset data transmission, and transmit the clock frequency to the FPGA chip 700 so that the FPGA chip 700 divides the clock frequency into a second clock frequency point 102.

[0047] The first phase-locked loop 801 includes: a first transmission interface and a second transmission interface, A first transmission interface, used for receiving a first clock frequency point 101, so that the clock chip 800 obtains a system clock 300; The second transmission interface is used to receive the first clock frequency 101. When the first phase-locked loop 801 uses the first transmission interface for receiving, the second transmission interface does not receive the first clock frequency 101. If the first transmission interface fails to send, the second transmission interface starts to receive the first clock frequency 101, so that the clock chip 800 obtains the system clock 300. Specifically, obtaining a stable system clock 300 specifically includes: Since the data transmission rate is greater than or equal to the preset data transmission rate, the clock recovered by the first rate interface has good stability and can be directly used for transmission. The FPGA chip 700 divides the clock recovered by the first rate interface into the first clock frequency point, and transmits it to the first phase-locked loop 801 of the clock chip 800 through the first transmission interface or the second transmission interface. A stable system clock 300 is obtained in the first phase-locked loop 801 according to the first clock frequency point 101. The stable system clock 300 can be used for the entire application device.

[0048] When the data transmission rate is lower than the preset data transmission rate, the clock recovered by the second rate interface has large jitter and the clock distribution is uneven, indicating that the stability of the clock recovered by the second rate interface is poor and cannot be directly used for transmission. Therefore, the FPGA chip 700 divides the clock recovered by the second rate interface into a second clock frequency 102, and transmits the second clock frequency 102 to the third phase-locked loop 803 of the clock chip 800 through the third transmission interface. After the second clock frequency 102 is stabilized by the third phase-locked loop 803, the stable second clock frequency 102 is transmitted to the FPGA chip 700. The FPGA chip 700 divides the stabilized second clock frequency 102 into the first clock frequency 101 again, and transmits the first clock frequency 101 to the first phase-locked loop 801 of the clock chip 800 through the first transmission interface or the second transmission interface, thereby obtaining a stable system clock 300.

[0049] In one embodiment, the preset data transmission rate is 1 Gbps. When the data transmission rate of the upstream device transmitting the initial clock synchronization signal 100 to the application device is greater than or equal to 1 Gbps, the initial clock synchronization signal 100 is transmitted to the FPGA chip 700 of the application device through the first rate interface, and the recovered clock is divided into the first clock frequency 101, and the first clock frequency 101 is transmitted to the first phase-locked loop 801 of the clock chip 800 through the first transmission interface or the second transmission interface to obtain a stable system clock 300.

[0050] When the data transmission rate of the initial clock synchronization signal 100 transmitted by the upstream device to the application device is less than 1 Gbps, the initial clock synchronization signal 100 is transmitted to the FPGA chip 700 of the application device through the first rate interface, and the recovered clock is divided into the second clock frequency 102, and the first clock frequency 101 is transmitted to the third phase-locked loop 803 of the clock chip 800 through the third transmission interface to obtain a stable second clock frequency 102. The clock chip 800 then transmits the stable second clock frequency 102 to the FPGA chip 700. The FPGA chip 700 divides the second clock frequency 102 into the first clock frequency 101 again, and transmits the first clock frequency 101 to the first phase-locked loop 801 of the clock chip 800 through the first transmission interface or the second transmission interface to obtain a stable system clock 300.

[0051] For the first transmission interface and the second transmission interface in the first phase-locked loop 801, both transmission interfaces are used to transmit the first clock frequency 101, but the two transmission interfaces are not transmitted at the same time. The first transmission interface and the second transmission interface are used for clock source switching of the application equipment, that is, when a running transmission interface fails, it switches to another transmission interface for transmission, thereby ensuring the stable operation of the clock. For example, the first transmission interface is used as the main transmission interface, and the first clock frequency 101 is transmitted through the first transmission interface, and the second transmission interface does not work at this time. When the first transmission interface fails and cannot operate, it switches smoothly to the second transmission interface, and continues to transmit the first clock frequency 101 to the first phase-locked loop 801. The switching of the third transmission interface is determined by the FPGA chip 700 and the software.

[0052] For the clock recovered when the data transmission rate is lower than the preset data transmission rate, the second clock frequency 102 is initially stabilized by the second phase-locked loop 802, and then the second clock frequency 102 is divided into the first clock frequency 101 and transmitted to the first phase-locked loop 801 for further stabilization. The unstable clock is processed by the two-stage phase-locked loop, so that the clock reaches a stable state after two stabilization processes, thereby obtaining a stable system clock 300, which can be applied to the entire application device.

[0053] On the other hand, the time synchronization device of the present application uses an FPGA chip 700 and a clock chip 800. These two chips are produced by various manufacturers and are interchangeable. In actual application, engineers can flexibly replace and update them according to actual application requirements.

[0054] In summary, a time synchronization device provided by an embodiment of the present application performs two stabilization processes in a two-stage phase-locked loop on an unstable clock signal frequency obtained by transmitting at a rate less than a preset data transmission rate, and obtains a stable system clock, thereby applying the system clock to the entire application device, providing a stable basis for subsequent clock synchronization. The time difference between the application device and the upstream device is used to adjust the time difference. For the second time difference, the pulse generator in the FPGA chip adjusts the phase of the pulse per second, thereby achieving time synchronization. For the nanosecond time difference with high precision requirements, for the obtained nanosecond time difference, the frequency generator sends the adjustment frequency to the first oscillator for frequency adjustment, and obtains the PTP clock frequency in the second oscillator based on the system clock, and adjusts the phase of the pulse per second through the clock frequency, so that the phase of the pulse per second is consistent with the pulse per second of the upstream device, that is, the time is adjusted by frequency to complete time synchronization.

[0055] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A time synchronization device, characterized in that: include: An electrically connected FPGA chip and a clock chip; The FPGA chip is used to divide the clock frequency of the received initial clock synchronization signal into a first clock frequency point and a second clock frequency point; The clock chip includes a first phase-locked loop and a second phase-locked loop. The first phase-locked loop is used to obtain a system clock according to the first clock frequency, and send the system clock to the second phase-locked loop; The second phase-locked loop is used to obtain the PTP clock offset frequency according to the system clock, and send the PTP clock offset frequency to the FPGA chip; The FPGA chip includes a pulse generator, which is used to generate a pulse signal per second. The phase of the pulse signal per second is adjusted according to the PTP clock offset frequency so that the phase is consistent with the pulse phase per second of the initial clock synchronization signal to complete time synchronization.

2. The time synchronization device according to claim 1, characterized in that: The clock chip further includes: a third phase-locked loop, The third phase-locked loop is used to receive the second clock frequency and transmit the second clock frequency to the FPGA chip, so that the FPGA chip converts the second clock frequency into the first clock frequency and transmits the first clock frequency to the first phase-locked loop.

3. The time synchronization device according to claim 1, characterized in that: The FPGA chip includes: a pulse signal compensator, a frequency controller, a register, The pulse signal compensator is electrically connected to the pulse generator, and is used to compensate for the delay of the pulse signal per second, and transmit the compensated pulse signal per second to a chip connected to the FPGA chip; The register is used to obtain the nanosecond time difference calculated by the PTP protocol message and transmit the nanosecond time difference to the frequency controller; The frequency controller is used to receive the nanosecond time difference and the pulse per second signal, and when the nanosecond time difference is less than a preset threshold, send an adjustment frequency to the second phase-locked loop according to the nanosecond time difference and the pulse per second signal to adjust the PTP clock offset frequency.

4. The time synchronization device according to claim 3, characterized in that: The second phase-locked loop includes: a first oscillator and a second oscillator, The first oscillator is used to receive the adjustment frequency sent by the frequency controller and adjust the frequency according to the adjustment frequency; The second oscillator is used to obtain the PTP clock offset frequency according to the system clock and the adjusted frequency, and transmit the PTP clock offset frequency to the pulse generator.

5. The time synchronization device according to claim 1, characterized in that: The time synchronization device further includes a device interface chip: The device interface chip includes a first rate interface and a second rate interface, The first rate interface is used to receive the clock frequency greater than or equal to the preset data transmission rate, and transmit the clock frequency to the FPGA chip, so that the FPGA chip divides the clock frequency into the first clock frequency point; The second rate interface is used to receive the clock frequency that is less than the preset data transmission, and transmit the clock frequency to the FPGA chip so that the FPGA chip divides the clock frequency into the second clock frequency point.

6. The time synchronization device according to claim 3, characterized in that: The time synchronization device comprises the pulse generator: The pulse generator is also used to adjust the phase of the pulse per second according to the nanosecond time difference when the nanosecond time difference is greater than or equal to a preset threshold, so that the phase is consistent with the pulse per second phase of the initial clock synchronization signal to complete time synchronization.

7. The time synchronization device according to claim 1, characterized in that: The first phase-locked loop includes: a first transmission interface and a second transmission interface, The first transmission interface is used to receive the first clock frequency so that the clock chip obtains the system clock; The second transmission interface is used to receive the first clock frequency. When the first phase-locked loop adopts the first transmission interface for receiving, the second transmission interface does not receive the first clock frequency. If the first transmission interface fails to send, the second transmission interface starts to receive the first clock frequency so that the clock chip obtains the system clock.

8. The time synchronization device according to claim 2, characterized in that: The third phase-locked loop comprises: a third transmission interface, The third transmission interface is used to receive the second clock frequency, so that the second clock frequency obtains a preliminary stable second clock frequency after being processed by the third phase-locked loop.

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