Rate-adaptive Ethernet data sending system, method and equipment and medium

Abstract

The invention discloses a rate-adaptive Ethernet data sending system, method and device and a medium, and relates to the technical field of communication, the system comprises a sending control module, a rate reading module and a data selector; the rate reading module reads an operation rate and sends the operation rate to the sending control module and the data selector, the sending control module receives input data when the operation rate is 100M, fills the input data into output data and sends the output data to the data selector, when the rate is 1000M, the sending control module does not receive the input data, and when the rate is 1000M, the sending control module sends the output data to the data selector. A data selector receives input data and outputs the input data as output data. According to the method, the rate of 1000M and the rate of 100M can be freely switched on the FPGA chip to send Ethernet data.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a rate-adaptive Ethernet data transmission system, method, device and medium. Background Art

[0002] In the field of communication technology, commonly used copper cable Ethernet technologies, such as Ethernet systems based on twisted pair cables (such as Cat5e, Cat6 or Cat6a), generally support multiple transmission rates to meet the data transmission requirements in different scenarios. Among them, 1000Mbps (Gigabit Ethernet) and 100Mbps (100M Ethernet) are two widely used rate standards. Gigabit Ethernet, with its high bandwidth characteristics, can be applied to network environments that require fast data transmission, such as data centers and large enterprise networks; while 100M Ethernet is also widely used due to its cost-effectiveness and sufficient performance.

[0003] However, in some specific industrial applications, such as high-precision control, real-time data acquisition and transmission, traditional Ethernet hardware may not be able to meet customized requirements. At this time, the use of Field Programmable Gate Array (FPGA) chips to implement Ethernet data transmission has become a new solution. FPGA chips have high configurability and parallel processing capabilities, and can control the generation, packaging, and transmission of data packets. They are very suitable for scenarios that require low latency, high reliability, and customized protocol support.

[0004] However, when using FPGA chips to implement Ethernet data transmission, there are often limitations on rate selection. Since the Ethernet transmission modules of FPGA need to be configured according to specific hardware designs or IP cores, these modules may only support one or a few fixed transmission rates. This means that although the standard copper cable Ethernet technology itself supports a variety of rates ranging from 10M to 10G, the Ethernet transmission end implemented by the FPGA chip may only be set to a fixed 1000M or 100M rate, and cannot dynamically switch between the two. Summary of the invention

[0005] The present application provides a rate-adaptive Ethernet data transmission system, method, device and medium, which can freely switch between 1000M and 100M rates in an FPGA chip to transmit Ethernet data.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a rate-adaptive Ethernet data transmission system, a transmission control module, a rate reading module and a data selector;

[0008] The rate reading module is used to read the operation rate and send the operation rate to the sending control module;

[0009] The sending control module is used for receiving input data in the ith clock cycle if the operation rate is 100M, determining the upper 4 bits of the input data in the ith clock cycle as the upper 4 bits and lower 4 bits of the first output data, obtaining the first output data with a width of 8 bits, and then sending the first output data to the data selector;

[0010] The data selector is used to output the first output data;

[0011] The sending control module is further used to receive input data in the (i+1)th clock cycle, determine the lower 4 bits of the input data in the (i+1)th clock cycle as the upper 4 bits and lower 4 bits of the second output data, obtain the second output data with a width of 8 bits, and then send the second output data to the data selector;

[0012] The data selector is further used to output the second output data.

[0013] In some possible implementations, the transmission control module further includes: a control logic submodule, a transmission state machine submodule, a length buffer submodule, and a data buffer submodule;

[0014] The control logic submodule is used to receive input data and input control signals in the i-th clock cycle if the operation rate is 100M;

[0015] The length buffer submodule is used to buffer the data length of the input data when the input control signal changes from 1 to 0;

[0016] The data cache submodule is used to cache the input data when the input control signal changes from 1 to 0;

[0017] The sending state machine submodule is used to detect whether there is a data length of input data in the length cache submodule when in an idle state, and if the data length of the input data exists in the length cache submodule, switch to a length reading state, read the data length of the input data in the length cache module in the length reading state, and after completing the reading of the data length of the input data in the length cache module, switch to a sending state, send the first output data and the second output data to the data selector, and after completing the sending of the first output data and the second output data to the data selector, switch back to an idle state; the initial state of the sending state machine submodule is an idle state.

[0018] In some possible implementations, the rate reading module is further configured to send a reset signal to the sending control module when the operation rate changes;

[0019] The sending control module is further used to control internal data to be cleared according to the reset signal.

[0020] In some possible implementations, the rate reading module is further used to send the operation rate to the data selector; the data selector is further used to receive the input data and output the input data when the rate is 1000M.

[0021] In some possible implementations, the sending control module is further configured to not receive input data if the computing rate is 1000M.

[0022] In a second aspect, the present application provides a rate-adaptive Ethernet data transmission method, the method comprising:

[0023] The rate reading module reads the operation rate and sends the operation rate to the sending control module;

[0024] The sending control module receives input data in the i-th clock cycle if the operation rate is 100M, determines the upper 4 bits of the input data in the i-th clock cycle as the upper 4 bits and lower 4 bits of the first output data, obtains the first output data with a width of 8 bits, and then sends the first output data to the data selector;

[0025] The data selector outputs the first output data;

[0026] The sending control module also receives input data in the i+1th clock cycle, determines the lower 4 bits of the input data in the i+1th clock cycle as the upper 4 bits and lower 4 bits of the second output data, obtains 8-bit wide second output data, and then sends the second output data to the data selector; the data selector outputs the second output data.

[0027] In some possible implementations, the method further includes:

[0028] The sending control module includes a control logic submodule, a sending state machine submodule, a length buffer submodule and a data buffer submodule;

[0029] The control logic submodule receives input data and input control signals in the i-th clock cycle if the operation rate is 100M;

[0030] The length buffer submodule buffers the data length of the input data when the input control signal changes from 1 to 0;

[0031] The data cache submodule caches the input data when the input control signal changes from 1 to 0;

[0032] When the sending state machine submodule is in the idle state, it detects whether there is a data length of the input data in the length cache submodule. If the data length of the input data exists in the length cache submodule, it switches to the length reading state. In the length reading state, it reads the data length of the input data in the length cache module. After completing the reading of the data length of the input data in the length cache module, it switches to the sending state and sends the first output data and the second output data to the data selector. After completing the sending of the first output data and the second output data to the data selector, it switches back to the idle state. The initial state of the sending state machine submodule is the idle state.

[0033] In some possible implementations, the method further includes:

[0034] The rate reading module also sends the operation rate to the data selector;

[0035] When the rate is 1000M, the data selector receives the input data and outputs the input data.

[0036] In a third aspect, the present application provides a computing device, including a memory and a processor;

[0037] One or more computer programs are stored in the memory, and the one or more computer programs include instructions; when the instructions are executed by the processor, the computing device executes the method as described in any one of the first aspects.

[0038] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store a computer program, and the computer program is used to execute the method as described in any one of the first aspects.

[0039] It can be seen from the above technical solution that the present application has at least the following beneficial effects:

[0040] In the present application, a rate-adaptive Ethernet data transmission system is provided, which includes: a transmission control module, a rate reading module and a data selector; the rate reading module reads the operation rate, sends the operation rate to the transmission control module and the data selector, the transmission control module receives the input data when the operation rate is 100M, fills the input data as output data and sends it to the data selector, when the rate is 1000M, the transmission control module does not receive the input data, the data selector receives the input data, and outputs the input data as output data. In the traditional scheme, the standard copper cable Ethernet technology itself supports a variety of rates ranging from 10M to 10G, but at the Ethernet transmitting end implemented by the FPGA chip, it may only be set to a fixed 1000M or 100M rate, and cannot be dynamically switched between the two. It can be seen that the present application fills the input data when the operation rate is 100M by adding a transmission control module to obtain the output data, and then sends the output data to the data selector, and the data selector sends the output data out. It can be seen that the present application can freely switch between 1000M and 100M rates in the FPGA chip to send Ethernet data.

[0041] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of features or beneficial effects means that specific technical features, technical solutions or beneficial effects are included in at least one embodiment. Therefore, the description of technical features, technical solutions or beneficial effects in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be realized without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in a specific embodiment that does not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of a rate-adaptive Ethernet data transmission system provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of a sending control module provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The terms "first", "second", "third", etc. in the specification of this application and the accompanying drawings are used to distinguish different objects rather than to limit a specific order.

[0047] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0048] At present, facing the needs of specific industrial applications such as high-precision control, real-time data acquisition and transmission, traditional Ethernet hardware may not be able to meet the customized needs. Therefore, the use of FPGA chips to implement Ethernet data transmission has become a new solution. FPGA chips have high configurability and parallel processing capabilities, and can control the generation, packaging, and transmission of data packets. They are very suitable for scenarios that require low latency, high reliability, and customized protocol support.

[0049] However, when using FPGA chips to implement Ethernet data transmission, there are often limitations in rate configuration. Since the Ethernet transmission module of FPGA is limited by a specific hardware architecture or pre-integrated IP core, it often only supports one or a few fixed transmission rates. This means that although the standard copper cable Ethernet technology itself supports a variety of rates ranging from 10M to 10G, the Ethernet transmission end implemented by the FPGA chip may only be set to a fixed 1000M or 100M rate, and cannot dynamically switch between the two.

[0050] In view of this, the embodiment of the present application provides a rate-adaptive Ethernet data transmission system, in which the rate reading module reads the operation rate, sends the operation rate to the transmission control module and the data selector, the transmission control module receives the input data when the operation rate is 100M, fills the input data as output data and sends it to the data selector, when the rate is 1000M, the transmission control module does not receive the input data, the data selector receives the input data, and outputs the input data as output data. It can be seen that the present application fills the input data when the operation rate is 100M by adding a transmission control module to obtain the output data, and then sends the output data to the data selector, and the data selector sends the output data. It can be seen that the present application can freely switch between 1000M and 100M rates in the FPGA chip to send Ethernet data.

[0051] In order to make the technical solution of the present application clearer and easier to understand, the application scenarios of the technical solution of the present application are introduced below in conjunction with the accompanying drawings. Figure 1 As shown, the figure is a schematic diagram of an application scenario provided by an embodiment of the present application.

[0052] In this application scenario, the processing device sends input data and input control signals to the system.

[0053] To this end, the present application adds a sending control module to fill in the input data when the operating rate is 100M, obtains output data, and then sends the output data to the data selector, which sends the output data. It can be seen that the present application can freely switch between 1000M and 100M rates in the FPGA chip to send Ethernet data.

[0054] In order to make the technical solution of the present application clearer and easier to understand, the following describes a rate-adaptive Ethernet data transmission system provided by an embodiment of the present application in combination with the above application scenario. Figure 2 As shown, this figure is a schematic diagram of a rate-adaptive Ethernet data transmission system provided in an embodiment of the present application.

[0055] The system includes: a rate reading module 201, a sending control module 202 and a data selector 203.

[0056] The rate reading module 201 is used to read the operation rate and send the operation rate to the sending control module 202 .

[0057] The rate reading module 201 reads the operation rate in the physical layer chip (PHY) 204, and sends the reading result to the sending control module 202 and the data selector 203. If the operation rate is 1000M, the sending control module 202 will not receive input data, and the input data will be directly sent to the data selector 203, and the output data will be output to the subsequent circuit module 205 through the data selector. If the operation rate is 100M, the sending control module 202 will receive the input data, fill the input data, and then send the first output data and the second output data to the data selector 203, and the data selector will output the output data to the subsequent circuit module 205.

[0058] Among them, the input data is 8-bit data, and the post-stage circuit module 205 receives 8-bit data. When the operating rate is 1000M, the input data outputs 8-bit data in one clock cycle, but when the operating rate is 100M, the input data can only output 4-bit data in one clock cycle. Therefore, it is necessary to send the control module 202 to fill the input data.

[0059] The sending control module 202 is used to receive input data in the i-th clock cycle if the operation rate is 100M, determine the high 4 bits of the input data in the i-th clock cycle as the high 4 bits and low 4 bits of the first output data, obtain the first output data with a width of 8 bits, and then send the first output data to the data selector 203.

[0060] The data selector 203 is used to output the first output data.

[0061] The sending control module 202 is also used to receive input data in the i+1th clock cycle, determine the lower 4 bits of the input data in the i+1th clock cycle as the upper 4 bits and lower 4 bits of the second output data, obtain the 8-bit wide second output data, and then send the second output data to the data selector 203.

[0062] The data selector 203 is further configured to output the second output data.

[0063] The sending control module 202 is described in detail below. Figure 3 As shown, this figure is a schematic diagram of a sending control module provided in an embodiment of the present application.

[0064] As can be seen in the figure, the sending control module 202 includes: a control logic submodule 301, a sending state machine submodule 302, a length buffer submodule 303 and a data buffer submodule 304;

[0065] The control logic submodule 301 is used to receive input data and input control signals in the ith clock cycle if the operation rate is 100M. The input control signals are used to help the length cache submodule 303 and the data cache submodule 304 read valid input data.

[0066] The length buffer submodule 303 is used to buffer the data length of the input data when the input control signal changes from 1 to 0.

[0067] When the input control signal changes from 0 to 1, the length buffer submodule 303 starts to record the length of the input data. At this time, the input data is valid data. When the input control signal changes from 1 to 0, the length buffer submodule 303 stops recording, because after the input control signal changes to 0, the input data is not valid data and does not need to be recorded. The length buffer submodule 303 caches the data length recording result.

[0068] The data buffering submodule 304 is used to buffer the input data when the input control signal changes from 1 to 0.

[0069] When the input control signal changes from 0 to 1, the data cache submodule 304 starts to record the input data. At this time, the input data is valid data. When the input control signal changes from 1 to 0, the data cache submodule 304 stops recording, because after the input control signal changes to 0, the input data is not valid data and does not need to be recorded. The data cache submodule 304 caches the data recording results.

[0070] The sending state machine submodule 302 is used to detect whether there is a data length of the input data in the length cache submodule 303 when in the idle state 311. If the data length of the input data exists in the length cache submodule 303, it is switched to the length reading state 312. In the length reading state 312, the data length of the input data in the length cache module 303 is read. After completing the reading of the data length of the input data in the length cache module 303, it is switched to the sending state 313. In the sending state 313, the length of the sending data frame is twice the data length of the input data read in the length cache submodule 303, the output control signal is set to 1, and the counter data_cnt starts counting. When data_cnt is an even number, the input data in a data cache submodule 304 is read. When data_cnt is an even number again, the upper 4 bits of the input data read last time are filled into the lower 4 bits and upper 4 bits of the 8-bit transmission data as the first output result and sent to the data selector 203. When data_cnt is an odd number, the lower 4 bits of the input data read last time are filled into the lower 4 bits and upper 4 bits of the 8-bit transmission data as the second output result and sent to the data selector 203. data_cnt is incremented by 1 every clock. When condition 2 is met, that is, data_cnt is equal to the transmission data frame length, the first output data and the second output data are sent to the data selector 203. After the first output data and the second output data are sent to the data selector 203, the state is switched back to the idle state 311.

[0071] The initial state of the sending state machine submodule 302 is the idle state 311, condition 1 is that the length buffer submodule 303 contains the data length of the input data, and condition 2 is that data_cnt is equal to the sending data frame length.

[0072] The rate reading module 201 is further used to send a reset signal to the sending control module 202 when the operation rate changes. The sending control module 202 is further used to control internal data to be cleared according to the reset signal.

[0073] When the operation rate changes, the rate reading module 201 sends a reset signal to the sending control module 202. When the sending control module 202 receives the reset signal, it clears the data cached in the length cache submodule 303 and the data cache submodule 304 to prepare for the next reception of input data.

[0074] Based on the above content, the embodiment of the present application provides a rate-adaptive Ethernet data transmission system, in which the rate reading module reads the operation rate, sends the operation rate to the transmission control module and the data selector, the transmission control module receives the input data when the operation rate is 100M, fills the input data as output data and sends it to the data selector, when the rate is 1000M, the transmission control module does not receive the input data, the data selector receives the input data, and outputs the input data as output data. It can be seen that the present application fills the input data when the operation rate is 100M by adding a transmission control module to obtain the output data, and then sends the output data to the data selector, and the data selector sends the output data. It can be seen that the present application can freely switch between 1000M and 100M rates in the FPGA chip to send Ethernet data.

[0075] The embodiment of the present application also provides a rate-adaptive Ethernet data transmission method, the method comprising:

[0076] The rate reading module reads the operation rate and sends the operation rate to the sending control module;

[0077] The sending control module receives input data in the i-th clock cycle if the operation rate is 100M, determines the upper 4 bits of the input data in the i-th clock cycle as the upper 4 bits and lower 4 bits of the first output data, obtains the first output data with a width of 8 bits, and then sends the first output data to the data selector;

[0078] The data selector outputs the first output data;

[0079] The sending control module also receives input data in the (i+1)th clock cycle, determines the lower 4 bits of the input data in the (i+1)th clock cycle as the upper 4 bits and lower 4 bits of the second output data, obtains the second output data with a width of 8 bits, and then sends the second output data to the data selector;

[0080] The data selector outputs the second output data.

[0081] In some possible implementations, the method further includes:

[0082] The sending control module includes a control logic submodule, a sending state machine submodule, a length buffer submodule and a data buffer submodule;

[0083] The control logic submodule receives input data and input control signals in the i-th clock cycle if the operation rate is 100M;

[0084] The length buffer submodule buffers the data length of the input data when the input control signal changes from 1 to 0;

[0085] The data cache submodule caches the input data when the input control signal changes from 1 to 0;

[0086] When the sending state machine submodule is in the idle state, it detects whether there is a data length of the input data in the length cache submodule. If the data length of the input data exists in the length cache submodule, it switches to the length reading state. In the length reading state, it reads the data length of the input data in the length cache module. After completing the reading of the data length of the input data in the length cache module, it switches to the sending state and sends the first output data and the second output data to the data selector. After completing the sending of the first output data and the second output data to the data selector, it switches back to the idle state. The initial state of the sending state machine submodule is the idle state.

[0087] In some possible implementations, the method further includes:

[0088] The rate reading module also sends the operation rate to the data selector; when the rate is 1000M, the data selector receives the input data and outputs the input data.

[0089] In some possible implementations, the rate reading module is further used to send a reset signal to the sending control module when the operation rate changes; the sending control module is further used to control internal data clearing according to the reset signal.

[0090] In some possible implementations, the sending control module is further configured to not receive input data if the computing rate is 1000M.

[0091] The present application also provides a computing device. Figure 4 As shown, this figure is a schematic diagram of a computing device provided in an embodiment of the present application, and the computing device 400 includes a bus 401, a processor 402, a communication interface 403 and a memory 404. The processor 402, the memory 404 and the communication interface 403 communicate with each other through the bus 401.

[0092] The bus 401 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0093] The processor 402 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0094] The communication interface 403 is used for communicating with the outside.

[0095] The memory 404 may include a volatile memory, such as a random access memory (RAM). The memory 404 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0096] The memory 404 stores executable codes, and the processor 402 executes the executable codes to perform the aforementioned rate adaptive Ethernet data sending method.

[0097] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the above-mentioned rate-adaptive Ethernet data transmission method.

[0098] The embodiment of the present application further provides a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part.

[0099] The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer or data center to another website, computer or data center via wired (e.g., coaxial cable, optical fiber) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0100] When the computer program product is executed by a computer, the computer executes any of the aforementioned rate-adaptive Ethernet data transmission methods. The computer program product may be a software installation package, and when any of the aforementioned rate-adaptive Ethernet data transmission methods is required, the computer program product may be downloaded and executed on a computer.

[0101] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0102] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A rate-adaptive Ethernet data transmission system, characterized in that: The system comprises: a transmission control module, a rate reading module and a data selector; The rate reading module is used to read the operation rate and send the operation rate to the sending control module; The sending control module is used for receiving input data in the ith clock cycle if the operation rate is 100M, determining the upper 4 bits of the input data in the ith clock cycle as the upper 4 bits and lower 4 bits of the first output data, obtaining the first output data with a width of 8 bits, and then sending the first output data to the data selector; The data selector is used to output the first output data; The sending control module is further used to receive input data in the (i+1)th clock cycle, determine the lower 4 bits of the input data in the (i+1)th clock cycle as the upper 4 bits and lower 4 bits of the second output data, obtain the second output data with a width of 8 bits, and then send the second output data to the data selector; The data selector is further used to output the second output data.

2. The system according to claim 1, characterized in that The sending control module also includes: a control logic submodule, a sending state machine submodule, a length buffer submodule and a data buffer submodule; The control logic submodule is used to receive input data and input control signals in the i-th clock cycle if the operation rate is 100M; The length buffer submodule is used to buffer the data length of the input data when the input control signal changes from 1 to 0; The data cache submodule is used to cache the input data when the input control signal changes from 1 to 0; The sending state machine submodule is used to detect whether there is a data length of input data in the length cache submodule when in an idle state, and if the data length of the input data exists in the length cache submodule, switch to a length reading state, read the data length of the input data in the length cache module in the length reading state, and after completing the reading of the data length of the input data in the length cache module, switch to a sending state, send the first output data and the second output data to the data selector, and after completing the sending of the first output data and the second output data to the data selector, switch back to an idle state; the initial state of the sending state machine submodule is an idle state.

3. The system according to claim 1, characterized in that The rate reading module is further used to send a reset signal to the sending control module when the operation rate changes; The sending control module is further used to control internal data to be cleared according to the reset signal.

4. The system according to claim 1, characterized in that The rate reading module is further used to send the operation rate to the data selector; The data selector is also used to receive the input data and output the input data when the rate is 1000M.

5. The system according to claim 1, characterized in that The sending control module is also used for not receiving input data if the operation rate is 1000M.

6. A rate-adaptive Ethernet data transmission method, characterized in that: The method comprises: The rate reading module reads the operation rate and sends the operation rate to the sending control module; The sending control module receives input data in the i-th clock cycle if the operation rate is 100M, determines the upper 4 bits of the input data in the i-th clock cycle as the upper 4 bits and lower 4 bits of the first output data, obtains the first output data with a width of 8 bits, and then sends the first output data to the data selector; The data selector outputs the first output data; The sending control module also receives input data in the i+1th clock cycle, determines the lower 4 bits of the input data in the i+1th clock cycle as the upper 4 bits and lower 4 bits of the second output data, obtains 8-bit wide second output data, and then sends the second output data to the data selector; the data selector outputs the second output data.

7. The method according to claim 6, characterized in that The method further comprises: The sending control module includes a control logic submodule, a sending state machine submodule, a length buffer submodule and a data buffer submodule; The control logic submodule receives input data and input control signals in the i-th clock cycle if the operation rate is 100M; The length buffer submodule buffers the data length of the input data when the input control signal changes from 1 to 0; The data cache submodule caches the input data when the input control signal changes from 1 to 0; When the sending state machine submodule is in the idle state, it detects whether there is a data length of the input data in the length cache submodule. If the data length of the input data exists in the length cache submodule, it switches to the length reading state. In the length reading state, it reads the data length of the input data in the length cache module. After completing the reading of the data length of the input data in the length cache module, it switches to the sending state and sends the first output data and the second output data to the data selector. After completing the sending of the first output data and the second output data to the data selector, it switches back to the idle state. The initial state of the sending state machine submodule is the idle state.

8. The method according to claim 6, characterized in that The method further comprises: The rate reading module also sends the operation rate to the data selector; When the rate is 1000M, the data selector receives the input data and outputs the input data.

9. A computing device, characterized in that including memory and processor; One or more computer programs are stored in the memory, and the one or more computer programs include instructions; when the instructions are executed by the processor, the computing device executes the method as claimed in any one of claims 6 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store a computer program, and the computer program is used to execute the method according to any one of claims 6 to 8.

Images