Data transmission method and device based on FPGA (Field Programmable Gate Array) and network equipment

Abstract

The invention provides a data transmission method and device based on an FPGA (Field Programmable Gate Array) and network equipment. According to the method, first IO processing is carried out on the obtained SerDes data corresponding to each second FPGA through the first IO transmission module in the first FPGA deployed in the network equipment to obtain multiple groups of target user data, and the SerDes data corresponding to each second FPGA are subjected to first IO processing to obtain multiple groups of target user data; according to the determined transmission rate of the single IO pin, the obtained target user data are transmitted to the second FPGA through the determined N IO pins, a second IO transmission module of the second FPGA processes and restores the target user data into SerDes data corresponding to the second FPGA, the SerDes data are sent through SerDes in the second FPGA, and the SerDes total rate which cannot be achieved by the single FPGA is achieved through splicing of the multiple FPGAs. And high-speed data transmission is achieved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method, device and network equipment based on FPGA. Background Art

[0002] High-bandwidth data transmission through field-programmable gate arrays (FPGAs) is usually achieved through serial transceivers (SerDes: Serializer-Deserializer). However, the total rate of SerDes in FPGAs cannot exceed the limit of 500Gbps, and higher-speed data transmission cannot be achieved through FPGAs. Summary of the invention

[0003] In view of this, the present application provides a data transmission method, apparatus and network equipment based on FPGA to achieve high-speed data transmission through FPGA.

[0004] The technical solutions provided by this application are as follows:

[0005] According to an embodiment of the first aspect of the present application, a data transmission method based on FPGA is proposed, and the method is applied to a network device; the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each of the second FPGAs is deployed with a second IO transmission module; the method includes:

[0006] For each obtained SerDes data corresponding to the second FPGA, the first IO transmission module deployed in the first FPGA performs a first IO processing on the SerDes data corresponding to the second FPGA to obtain multiple groups of target user data; the first IO processing refers to: packing the SerDes data corresponding to the second FPGA and adding the check information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data and grouping the scrambled reference user data to obtain multiple groups of target user data;

[0007] Determine the transmission rate of a single IO pin and determine the N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode;

[0008] Through N IO pins, each target user data is sent to the second FPGA corresponding to the SerDes data according to the transmission rate of the single IO pin, so that the second IO transmission module in the second FPGA performs second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA; the second IO processing is the reverse process of the first IO processing.

[0009] Optionally, the first FPGA is further configured with an Ethernet processing module; the Ethernet processing module is configured to convert user-side data into SerDes data that is allowed to be transmitted through a serial transceiver SerDes; the method further comprises:

[0010] The received user-side data is converted into target SerDes data through the Ethernet processing module in the first FPGA, and the SerDes data corresponding to the first FPGA in the target SerDes data is sent through the SerDes in the first FPGA; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA;

[0011] The SerDes data corresponding to each second FPGA in the target SerDes data is forwarded to the first IO transmission module through the Ethernet processing module in the first FPGA.

[0012] Optionally, the maximum amount of data allowed to be transmitted at a single time by the SerDes in the first FPGA is M, the data size of the target SerDes data is greater than M, and the data size of the SerDes data corresponding to the first FPGA is M.

[0013] Optionally, the SerDes data corresponding to the second FPGA is packaged and verification information corresponding to the SerDes data is added to obtain reference user data, including:

[0014] Packing the SerDes data corresponding to the second FPGA according to the obtained data bit width and clock frequency to obtain parallel signal data;

[0015] The parallel signal data are grouped according to a preset size, and each group of data is encoded to obtain a check code corresponding to the group of data;

[0016] Each set of data and the check code corresponding to each set of data are concatenated and reorganized to obtain reference user data.

[0017] Optionally, grouping the scrambled reference user data to obtain multiple groups of target user data includes:

[0018] Determine the number of groups of target user data according to the number of IO pins included in the first FPGA;

[0019] Grouping the scrambled reference user data according to the number of groups of the target user data;

[0020] For each group of data, insert an alignment mark of a second specified length every data of a first specified length to obtain target user data;

[0021] The alignment mark is used to align each group of target user data when transmitting the target user data. Different groups of target user data have different alignment marks inserted, while the same group of target user data has the same alignment marks inserted.

[0022] Optionally, determining the transmission rate of a single IO pin and determining N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode includes:

[0023] Determine the transmission rate of each group of target user data according to the target total rate and the number of groups of the target user data; the target total rate is determined according to the sum of the data sizes of the SerDes data corresponding to each second FPGA;

[0024] Determine the transmission rate of a single IO pin according to the transmission rate of each group of target user data and the number of IOs corresponding to each group of target user data; the number of IOs included in each group of target user data is determined according to the number of groups of the target user data, the maximum transmission rate of the IO pin of the first FPGA, and the target total rate;

[0025] The N IO pins that the SerDes data corresponding to the second FPGA needs to occupy are determined according to the IO quantity corresponding to each group of target user data and the IO data transmission mode.

[0026] Optionally, the second IO processing refers to:

[0027] Combining the received multiple groups of target user data to obtain scrambled reference user data, and descrambling the scrambled reference user data to obtain reference user data;

[0028] Verify the verification information included in the reference user data, and if the verification succeeds, restore the reference user data to SerDes data corresponding to the second FPGA.

[0029] Optionally, the step of combining the received multiple groups of target user data to obtain scrambled reference user data includes:

[0030] Setting a designated mark at the start bit position of the alignment mark of each group of target user data, and deleting the alignment mark of each group of target user data;

[0031] Cache the target user data where the alignment mark is deleted;

[0032] When all target user data are cached, multiple groups of target user data are merged according to the positions of the designated marks to obtain scrambled reference user data.

[0033] According to an embodiment of the second aspect of the present application, a data transmission device based on FPGA is proposed, and the device is applied to a network device; the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each of the second FPGAs is deployed with a second IO transmission module; the device includes:

[0034] a processing unit, configured to perform a first IO processing on the SerDes data corresponding to each second FPGA obtained by using a first IO transmission module deployed in the first FPGA to obtain multiple groups of target user data; the first IO processing refers to: performing a packing process on the SerDes data corresponding to the second FPGA and adding check information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data and grouping the scrambled reference user data to obtain multiple groups of target user data;

[0035] A determination unit, used to determine a transmission rate of a single IO pin and determine N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode;

[0036] A transmission unit is used to send each target user data to a second FPGA corresponding to the SerDes data through N IO pins according to the transmission rate of the single IO pin, so that a second IO transmission module in the second FPGA performs a second IO processing on the received target user data to obtain SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA; the second IO processing is the reverse process of the first IO processing.

[0037] According to an embodiment of the third aspect of the present application, a network device is proposed, wherein a first FPGA and at least one second FPGA are deployed on the network device; the first FPGA is connected to each second FPGA via an IO pin; a first IO transmission module is deployed on the first FPGA; and a second IO transmission module is deployed on each second FPGA, and the network device is used to execute the method described in the first aspect.

[0038] It can be seen from the above technical scheme that the present application performs a first IO processing on the SerDes data corresponding to each second FPGA that has been obtained through the first IO transmission module in the first FPGA deployed in the network device to obtain multiple groups of target user data. For each SerDes data corresponding to the second FPGA, the transmission rate of a single IO pin and the number of pins N that need to be occupied are determined. Further, according to the transmission rate of the single IO pin, the obtained target user data is transmitted to the second FPGA through the determined N IO pins, and the second IO transmission module of the second FPGA processes and restores it to the SerDes data corresponding to the second FPGA, and sends the SerDes data through the SerDes in the second FPGA. The total SerDes rate that cannot be achieved by a single-chip FPGA is achieved by splicing multiple FPGAs, thereby achieving high-speed data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] Figure 1 A schematic diagram of connecting a first FPGA and a plurality of second FPGAs through IO pins in a network device provided in an embodiment of the present application;

[0041] Figure 2 A flowchart of a data transmission method based on FPGA provided in an embodiment of the present application;

[0042] Figure 3 A schematic diagram of a solution for implementing 800Gbps Ethernet using two FPGAs provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of a first IO transmission module and a second IO transmission module provided in an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the IO transmission module structure provided in an embodiment of the present application;

[0045] Figure 6 A schematic diagram of the structure of the IO transmission module in the transmission layer provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of the structure of the IO transmission module in the link layer provided in an embodiment of the present application;

[0047] Figure 8 A schematic diagram of an alignment mark insertion method provided in an embodiment of the present application;

[0048] Fig. 9 A schematic diagram of the processing process of the IO transmission module in the link layer receiving direction provided in an embodiment of the present application;

[0049] Fig.10 A schematic diagram of the structure of a network device provided in an embodiment of the present application;

[0050] Fig.11 A structural diagram of a data transmission device based on FPGA provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application and to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0052] Please refer to Figure 1 , Figure 1 A schematic diagram of connecting a first field programmable gate array (FPGA) and multiple second FPGAs through input / output (IO) pins in a network device provided in an embodiment of the present application.

[0053] like Figure 1 As shown, the network device is deployed with a first FPGA and multiple second FPGAs, wherein the first FPGA is connected to each second FPGA through an IO pin, the first FPGA is deployed with a first IO transmission module, and each second FPGA is deployed with a second IO transmission module.

[0054] Based on the connection method between the first FPGA and multiple second FPGAs in the above-mentioned network device, an embodiment of the present application proposes an FPGA-based data transmission method to achieve high-speed data transmission through the FPGA.

[0055] Please refer to Figure 2 , Figure 2 A flowchart of a data transmission method based on FPGA is provided in an embodiment of the present application.

[0056] In this embodiment, the method is applied to Figure 1 The network devices shown.

[0057] As an embodiment, the above-mentioned network devices may include data center switches, routers, network interface cards, network acceleration cards and other network devices that require FPGA to support high-speed data transmission, and this application does not limit this.

[0058] like Figure 2 As shown, the specific steps of the method may include:

[0059] Step 201 : for each obtained serial transceiver SerDes data corresponding to the second FPGA, a first IO transmission module deployed in the first FPGA performs a first IO processing on the SerDes data corresponding to the second FPGA to obtain multiple groups of target user data.

[0060] In this embodiment, when the SerDes rate supported by the single-chip FPGA cannot reach the target total rate to be achieved, the SerDes data to be transmitted can be forwarded to multiple second FPGAs through the first FPGA, and the first FPGA will obtain the SerDes data corresponding to each second FPGA. The SerDes data corresponding to each second FPGA actually refers to the SerDes data sent through the second FPGA.

[0061] As an embodiment, the SerDes data corresponding to each second FPGA may be determined according to a desired total target rate and a SerDes rate supported by each second FPGA.

[0062] Before executing the FPGA-based data transmission method proposed in the embodiment of the present application, the type and number of second FPGAs to be deployed can be determined in advance based on the SerDes rate supported by each second FPGA and the target total rate to be achieved.

[0063] For example, assuming that the current target total rate is 800 Gbps, and the maximum SerDes total rate supported by the first type of FPGA is 448 Gbps, and the maximum SerDes total rate supported by the second type of FPGA is 224 Gbps, it means that if the first type of FPGA is selected, two first type FPGAs need to be deployed as the second FPGA to send SerDes data to achieve the target total rate of 800 Gbps. If the second type of FPGA is selected, four FPGAs need to be deployed as the second FPGA to send SerDes data to achieve the target total rate of 800 Gbps.

[0064] In this embodiment, the target total rate is 800Gbps, that is, 800G bits of SerDes data are transmitted per second. The 800G bits of SerDes data to be transmitted per second are distributed to multiple second FPGAs for transmission, and each second FPGA corresponds to a part of the SerDes data.

[0065] As a preferred embodiment, the SerDes data corresponding to each second FPGA may be configured for the second FPGA according to the maximum capability threshold of each second FPGA in transmitting SerDes data, so as to fully utilize the resources of each second FPGA.

[0066] In this embodiment, the first FPGA is also deployed with an Ethernet processing module; the Ethernet processing module is used to convert user-side data into SerDes data that allows transmission through the serial transceiver SerDes, and the first IO transmission module is deployed between the Ethernet processing module and the IO pin of the first FPGA.

[0067] In this embodiment, the Ethernet processing module may specifically include a media access control (MAC) module and a physical coding sublayer (PCS) module, wherein the MAC module may be used to encapsulate user-side data (such as IP data packets) into Ethernet frames, add necessary header information (such as source address, destination address and frame type) and control information (such as flow control, error detection code), etc.; the PCS module may be used to encode the Ethernet frames to ensure the validity of the signal and improve the transmission rate.

[0068] As an embodiment, the Ethernet processing module may further include a forward error correction module (FEC: Forward Error Correction) for adding redundant information to data to detect and correct errors in transmission.

[0069] In this embodiment, the process of processing user-side data by the Ethernet processing module is a common method in the related art and will not be described in detail here.

[0070] When data transmission is implemented through FPGA, FPGA processes the received user-side data through the Ethernet processing module to obtain SerDes data that can be transmitted through the physical medium, and sends it through the SerDes in the FPGA. In this embodiment, due to the limitation of the total SerDes rate of the single-chip FPGA, the processing of SerDes data cannot be completed through the single-chip FPGA, and needs to be processed through multiple FPGAs.

[0071] In this embodiment, after the first FPGA converts the user-side data into SerDes data through the Ethernet processing module, the first FPGA can serve as a forwarding device for the SerDes data, that is, the received SerDes data is forwarded to other second FPGAs through the first FPGA, and the SerDes data is sent through the serial transceiver SerDes in each second FPGA.

[0072] As an embodiment, the first FPGA itself may also have a SerDes data transmission function, that is, the first FPGA itself also has a serial transceiver SerDes. In this case, the method may further include:

[0073] The received user-side data is converted into target SerDes data through the Ethernet processing module in the first FPGA, and the SerDes data corresponding to the first FPGA in the target SerDes data is sent through the SerDes in the first FPGA; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA;

[0074] The SerDes data corresponding to each second FPGA in the target SerDes data is forwarded to the first IO transmission module through the Ethernet processing module in the first FPGA.

[0075] In this embodiment, after the received user-side data is converted into target SerDes data through the Ethernet processing module in the first FPGA, the target SerDes data is divided into two parts, namely, the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA.

[0076] In this embodiment, the SerDes data corresponding to the first FPGA in the target SerDes data can be sent through the SerDes in the first FPGA, and the SerDes data corresponding to each second FPGA in the target SerDes data can be forwarded to the first IO transmission module through the Ethernet processing module to achieve high-speed data transmission through the first FPGA and at least one second FPGA.

[0077] As an embodiment, the maximum amount of data allowed to be transmitted at a single time by the SerDes in the first FPGA is M, the data size of the target SerDes data is greater than M, the data size of the SerDes data corresponding to the first FPGA is M, and the SerDes data corresponding to each second FPGA is the target SerDes data except the SerDes data corresponding to the first FPGA.

[0078] It is easy to understand that when the data size of the target SerDes data is larger than the maximum data amount M that the SerDes in the first FPGA is allowed to transmit at a single time, the processing and transmission of the SerDes data cannot be completed only by the first FPGA. At this time, the SerDes data with a data amount of M (that is, the SerDes data corresponding to the first FPGA) can be transmitted through the first FPGA, and the target SerDes data except the SerDes data corresponding to the first FPGA is used as the SerDes data corresponding to each second FPGA and transmitted through each second FPGA.

[0079] As an embodiment, the maximum amount of data allowed to be transmitted at a single time by the SerDes in the first FPGA is M, the data size of the SerDes data corresponding to the first FPGA is not greater than M, and the SerDes data other than the SerDes data corresponding to the first FPGA is used as the SerDes data corresponding to each second FPGA and transmitted through the second FPGA.

[0080] In this embodiment, the first FPGA and the second FPGA may also be pre-configured with the size of the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA that need to be transmitted. It is only necessary that the size of the SerDes data corresponding to the first FPGA is not greater than the maximum amount of data M allowed to be transmitted in a single time by the SerDes in the first FPGA.

[0081] In this embodiment, for each SerDes data corresponding to the second FPGA, the first FPGA may perform the first IO processing on the SerDes data corresponding to the second FPGA through the deployed first IO transmission module to obtain multiple groups of target user data.

[0082] In this embodiment, the first IO processing refers to packing the SerDes data corresponding to the second FPGA and adding the verification information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data and grouping the scrambled reference user data to obtain multiple groups of target user data.

[0083] In this embodiment, the first IO module and the second IO module both support three layers, namely, the Transport layer, the Link layer, and the PHY IO physical interface layer.

[0084] In the transport layer, the first IO module may package the SerDes data corresponding to each second FPGA and add verification information corresponding to the SerDes data to obtain reference user data.

[0085] As an embodiment, a specific method of packaging the SerDes data corresponding to each second FPGA and adding verification information corresponding to the SerDes data to obtain reference user data may include:

[0086] For each SerDes data corresponding to the second FPGA, the SerDes data corresponding to the second FPGA is packaged according to the obtained data bit width and clock frequency to obtain parallel signal data;

[0087] The parallel signal data is grouped according to a preset size, each group of data is encoded, and a check code corresponding to the group of data is obtained;

[0088] Each set of data and the check code corresponding to each set of data are concatenated and reorganized to obtain reference user data.

[0089] In this embodiment, in the transmission layer, the SerDes data corresponding to each second FPGA can be packaged according to the obtained data bit width and clock frequency to obtain parallel signal data, and the parallel signal data can be grouped according to a preset size.

[0090] As an embodiment, for the SerDes data corresponding to each second FPGA, a data bit width of 1024 bits and a clock frequency of 402.83203125 MHz can be used in the transmission layer. All the SerDes data corresponding to the second FPGA can be packaged together to form a parallel signal data, that is, 1024 bits of data are processed each time, and 402.83203125M times are processed in 1 second.

[0091] For each 1024-bit data processed, it can be grouped according to a preset size, such as 64 bits per group, and divided into 16 groups in total. The specific grouping method can be to divide the 0th bit of data in the 1024-bit data into the data included in the first group, the 1st bit of data into the data included in the second group, ..., the 15th bit of data into the data included in the 16th group, the 16th bit of data into the data included in the first group, and so on.

[0092] After the grouping is completed, each group of data can be encoded according to a specified encoding method to obtain a check code corresponding to each group of data.

[0093] As an embodiment, the encoding method may be an error correction code (ECC), a cyclic redundancy check code (CRC), or a convolutional code, etc., and the present application does not impose any limitation on this.

[0094] Furthermore, the parallel signal data can be reorganized by splicing each group of data with the check code corresponding to each group of data. For example, the original parallel signal data can be reorganized into group 1 + check code corresponding to group 1 + group 2 + check code corresponding to group 2 + ... + group 16 + check code corresponding to group 16 to obtain reference user data.

[0095] In the link layer, the first IO module may scramble the reference user data and group the scrambled reference user data to obtain multiple groups of target user data.

[0096] In this embodiment, long 0s and long 1s may appear in the reference user data, which will cause DC imbalance of the data transmitted on the final IO pin. To avoid long 0s or long 1s in the reference user data, the reference user data needs to be scrambled.

[0097] In this embodiment, the reference user data may be processed according to a preset method to avoid the situation where long 0s and long 1s appear in the reference user data.

[0098] As an embodiment, a self-synchronous scrambler may be used to scramble the reference user data, for example, the reference user data may be processed in the form of a polynomial to obtain the scrambled reference user data.

[0099] As an embodiment, a specific method for grouping the scrambled reference user data to obtain multiple groups of target user data may include:

[0100] Determine the number of groups of target user data according to the number of IO pins included in the first FPGA;

[0101] Grouping the scrambled reference user data according to the number of target user data groups;

[0102] For each group of data, insert an alignment mark of a second specified length every data of a first specified length to obtain target user data;

[0103] The alignment mark is used to align each group of target user data when transmitting the target user data. Different groups of target user data have different alignment marks inserted, while the same group of target user data has the same alignment marks inserted.

[0104] In this embodiment, the number of target user data groups may be determined first according to the number of IO pins included in the first FPGA. Specifically, the number of target user data groups ranges from 1 to the number of IO pins included in the first FPGA.

[0105] As an embodiment, the number of IO pins included in the first FPGA is 500, and the number of groups of the target user data ranges from [1, 500]. When determining the number of groups, you can first select an integer from [1, 500] as the number of groups, such as selecting 64 as the number of groups.

[0106] It should be noted that after selecting the number of groups, the selected number of groups needs to be further verified to determine whether the selected number of groups is appropriate. Taking 64 as the number of groups as an example, 64 groups of target user data are finally obtained. The average transmission rate of each group of target user data can be determined based on the obtained target total rate (taking 400Gbps as an example), that is, 400 / 64=6.25Gbps. Further, the maximum transmission rate of a single IO pin of the first FPGA (taking 2Gbps as an example) can be used to determine how many IO pins each group of target user data needs to be transmitted through, that is, 6.25 / 2=3.125, which is rounded up to 4.

[0107] For FPGA devices, it is guaranteed that the data of up to 64 IOs can be directly aligned. To ensure that the data in each target user data group is aligned, each target user data group can only be transmitted through a maximum of 64 IO pins.

[0108] It can be seen that in the above example, the number of IO pins corresponding to each group of target user data should be selected in [4,64]. If the minimum number of IO pins required for the transmission data finally determined based on the pre-selected number of groups is greater than 64, it indicates that the selection of the number of groups is inappropriate and needs to be adjusted.

[0109] In this embodiment, after the selection of the number of groups is completed, the scrambled reference user data may be grouped according to the number of groups of the target user data;

[0110] Further, for each group of data, an alignment mark of a second specified length is inserted every data of a first specified length to obtain target user data.

[0111] In this embodiment, an alignment mark corresponding to the group of data is configured for each group of data. The alignment mark is a piece of identification data of a specified length, which is used to align each group of target user data when transmitting the target user data. Different alignment marks are inserted into different groups of target user data, and the same alignment marks are inserted into the same group of target user data.

[0112] In this embodiment, for each group of scrambled reference user data, an alignment marker may be inserted into the group of data at intervals of a first specified length.

[0113] It should be noted that the second specified length cannot be too short to avoid duplication with the scrambled reference user data, thereby causing misrecognition of the alignment mark.

[0114] At the same time, attention should be paid to the length settings of the first specified length and the second specified length to avoid the effective data bandwidth percentage in the target user data being too low. Specifically, the minimum value of the effective data bandwidth in the target user data can be inferred in advance based on the IO pin number calculation formula. The IO pin number calculation formula is:

[0115]

[0116] Where S is the amount of SerDes data corresponding to each second FPGA, M is the number of IO pins required, K is the transmission rate of a single IO pin, and P is the percentage of effective data bandwidth. Where S*1.03125 is the above target total rate.

[0117] Substituting the maximum transmission rate of a single IO pin and the total number of FPGA IO pins into the above formula, the minimum value of P can be solved. min It is easy to understand that when setting the first specified length and the second specified length, it should be noted that the effective data bandwidth percentage in the target user data finally obtained cannot be lower than P min .

[0118] The selection and insertion of the alignment mark will be described below through specific embodiments and will not be repeated here.

[0119] At this point, the description of step 201 ends, and step 202 is executed next.

[0120] Step 202, determining the transmission rate of a single IO pin and determining the N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode.

[0121] In the physical interface layer, for each SerDes data corresponding to the second FPGA, the first IO module can determine the transmission rate of a single IO pin and determine the N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode.

[0122] Specifically, the transmission rate of each group of target user data is determined according to the target total rate and the number of groups of target user data; the target total rate is determined according to the sum of the data sizes of the SerDes data corresponding to each second FPGA;

[0123] Determine the transmission rate of a single IO pin according to the transmission rate of each group of target user data and the number of IOs corresponding to each group of target user data; the number of IOs included in each group of target user data is determined according to the number of groups of target user data, the maximum transmission rate of the IO pin of the first FPGA, and the target total rate;

[0124] The N IO pins that the SerDes data corresponding to the second FPGA needs to occupy are determined according to the IO quantity corresponding to each group of target user data and the IO data transmission mode.

[0125] In this embodiment, the process of determining the transmission rate of each group of target user data according to the target total rate and the number of groups of target user data has been described above and will not be repeated here.

[0126] Furthermore, the transmission rate of a single IO pin can be determined by dividing the transmission rate of each group of target user data by the number of IOs included in each group of target user data, wherein the method for determining the number of IOs included in each group of target user data has been described in detail above and will not be repeated here.

[0127] In addition, the N IO pins that the SerDes data corresponding to each second FPGA needs to occupy can be determined based on the IO quantity corresponding to each group of target user data and the IO data transmission mode, wherein the IO data transmission mode can be determined based on the percentage of the effective data bandwidth.

[0128] As an embodiment, if the IO data transmission adopts DDR mode according to the percentage of effective data bandwidth, each group of target user data includes a pair of differential clocks CK and 16 pairs of differential data DQ during transmission, requiring a total of 34 IO pins, and 16 groups of target user data require 34*16 IO pins.

[0129] At this point, the description of step 202 ends, and step 203 is executed next.

[0130] Step 203, through N IO pins, each target user data is sent to the second FPGA corresponding to the SerDes data according to the transmission rate of a single IO pin, so that the second IO transmission module in the second FPGA performs a second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA.

[0131] In this embodiment, for the SerDes data corresponding to each second FPGA, after determining the transmission rate of a single IO pin and the N IO pins that the SerDes data corresponding to the second FPGA needs to occupy through the first IO module, each target user data can be sent to the corresponding second FPGA through the N IO pins according to the transmission rate of the single IO pin, so that the second IO transmission module in the second FPGA will perform second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and send the SerDes data corresponding to the second FPGA through the SerDes in the second FPGA.

[0132] In this embodiment, the second IO processing is generally the reverse process of the first IO processing.

[0133] Specifically, the second IO processing may include:

[0134] For each SerDes data corresponding to the second FPGA, the received multiple groups of target user data are combined to obtain scrambled reference user data, and the scrambled reference user data is descrambled to obtain reference user data;

[0135] The verification information included in the reference user data is verified, and if the verification succeeds, the reference user data is restored to the SerDes data corresponding to the second FPGA.

[0136] As an embodiment, a method for combining multiple groups of received target user data to obtain scrambled reference user data may include:

[0137] Setting a designated mark at the start bit position of the alignment mark of each group of target user data, and deleting the alignment mark of each group of target user data;

[0138] Cache the target user data where the alignment mark is deleted;

[0139] When all target user data are cached, multiple groups of target user data are merged according to the positions of designated markers to obtain scrambled reference user data.

[0140] The method of combining the received multiple groups of target user data to obtain the scrambled reference user data will be described in the specific embodiments below and will not be repeated here.

[0141] This concludes the description of step 203.

[0142] This ends the Figure 2 Description of the FPGA-based data transfer method.

[0143] The present application performs a first IO processing on the obtained SerDes data corresponding to each second FPGA through a first IO transmission module in a first FPGA deployed in a network device to obtain multiple groups of target user data. For each SerDes data corresponding to the second FPGA, the transmission rate of a single IO pin and the number of pins N that need to be occupied are determined. Further, according to the transmission rate of the single IO pin, the obtained target user data is transmitted to the second FPGA through the determined N IO pins. The second IO transmission module of the second FPGA processes and restores the data to the SerDes data corresponding to the second FPGA. The SerDes data is sent through the SerDes in the second FPGA, and the total SerDes rate that cannot be achieved by a single-chip FPGA is achieved by splicing multiple FPGAs, thereby achieving high-speed data transmission.

[0144] The following is an introduction to a specific embodiment of the solution provided by the present application for implementing a single-port 800 Gbps Ethernet through two FPGAs.

[0145] Example 1

[0146] Please refer to Figure 3 , Figure 3 Schematic diagram of the 800Gbps Ethernet solution implemented by two FPGAs provided in the embodiment of the present application.

[0147] like Figure 3 As shown, taking the data transmission rate that needs to be achieved as 800Gbps as an example, that is, 800G bits of data need to be transmitted per second, in this embodiment, the 800G data that needs to be transmitted per second is divided into two parts, of which 400G data is sent and received by the SerDes of one FPGA (recorded as the first FPGA), and the other 400G data is transmitted to another FPGA (recorded as the second FPGA) through the IO pin of the first FPGA, and forwarded by the SerDes of the second FPGA, that is, this embodiment adopts a method in which the first FPGA itself can also perform SerDes transmission.

[0148] Before data is transferred through the IO pins, the type and number of FPGAs to be used can be determined in advance.

[0149] Specifically, depending on the SerDes rate supported by the FPGA, there are generally 56G and 112G SerDes. An FPGA requires 4 (112G) or 8 (56G) SerDes to splice a complete 800G Ethernet interface. The number of SerDes required can determine the type and number of FPGAs that need to be spliced.

[0150] Among them, the first FPGA converts the user-side data into SerDes data that allows transmission through the serial transceiver SerDes through the 800G Ethernet processing module, and sends 400G (SerDes data corresponding to the first FPGA) of the data through the SerDes in the first FPGA; the other 400G (SerDes data corresponding to the second FPGA) of the data is sent to the first IO transmission module, so that the SerDes data corresponding to the second FPGA is processed by the first IO transmission module and then forwarded to the second FPGA through the IO pin, and sent by the SerDes of the second FPGA.

[0151] The following introduces the process of transmitting data through IO pins.

[0152] In this embodiment, the data conversion between the user-side data and the physical IO pins is implemented through the first IO transmission module in the FPGA to ensure the correctness of data transmission.

[0153] Please refer to Figure 4 , Figure 4 A schematic diagram of a first IO transmission module and a second IO transmission module provided in an embodiment of the present application.

[0154] like Figure 4 As shown, the first FPGA and the second FPGA are both deployed with IO transmission modules, the IO transmission module deployed on the first FPGA is recorded as the first IO transmission module, and the IO transmission module deployed on the second FPGA is recorded as the second IO transmission module.

[0155] For further information, please refer to Figure 5 , Figure 5 This is a schematic diagram of the IO transmission module structure provided in an embodiment of the present application.

[0156] like Figure 5 As shown, the IO transmission module supports the Transport layer, Link layer and PHY IO physical interface layer.

[0157] Among them, in the data sending direction, in the Transport layer, the data on the user side can be combined and the corresponding verification information can be added; in the Link layer, the received data can be scrambled, channeled, etc.; in the PHY IO physical layer, the data can be distributed to the interfaces of each IO pin and sent out.

[0158] The specific implementation mechanism of the sending direction is described below.

[0159] 1) Transport layer

[0160] Please refer to Figure 6 , Figure 6 A schematic diagram of the structure of the IO transmission module in the transmission layer provided in an embodiment of the present application.

[0161] like Figure 6 As shown, when the SerDes data is received, all the SerDes data are packaged together to form a parallel signal data.

[0162] In this embodiment, a data bit width of 1024 bits is adopted, and a clock frequency of 402.83203125 MHz is adopted, so each beat of data is 1024 bits.

[0163] Each beat of data (1024 bits) is grouped into 64-bit groups to obtain 16 groups. The data in each group is ECC encoded separately. The 64-bit data in each group will generate an 8-bit wide ECC check code. Therefore, a total of 16 groups of 128-bit ECC check codes will be generated.

[0164] The method for grouping data is as follows:

[0165] Group 1: bit[0,16,32,16*n,...]

[0166] Group 2: bit[1,17,33,16*n+1,...] ...

[0168] Group m: bit[m-1,16+m-1,32+m-1,16*n+m-1,...]

[0169] Here, m is the number of groups. In this embodiment, m is 16, and the value range of the integer n is [0,63].

[0170] When the groups and the ECC check code corresponding to each group are determined, the generated ECC check code is reorganized with the beat data, and each group of data and the ECC check data corresponding to the group are organized together to merge into 1152 bits of data (recorded as original data).

[0171] Exemplarily, the structure of the 1152-bit data finally merged is: the first group of 64-bit data, the first group of 8-bit check code, the second group of 64-bit data, the second group of 8-bit check code, ..., the sixteenth group of 64-bit data, the sixteenth group of 8-bit check code.

[0172] Based on this, 1152 bits of data are obtained by combining the group data and the check code.

[0173] 2) Link layer

[0174] Please refer to Figure 7 , Figure 7 A schematic diagram of the structure of the IO transmission module in the link layer provided in an embodiment of the present application.

[0175] like Figure 7 As shown, after receiving 1152-bit original data, since the original data may include long 0s and long 1s, this will cause DC imbalance in the data transmitted on the final IO pin. In order to avoid long 0s or long 1s in the original data, the original data needs to be scrambled.

[0176] Exemplarily, a self-synchronous scrambler may be used for scrambling, and the scrambling code generating polynomial may be:

[0177] G(x)=1+x 39 +x 58

[0178] After the original data is scrambled, the scrambled data is obtained. Further, the scrambled data is grouped.

[0179] Since there are many IO pins, data needs to be distributed to each IO pin. For FPGA devices, generally, up to 64 IO data can be directly aligned. In this example, combined with the actual data transmission bandwidth requirements, the data is divided into 16 groups, each with 72 bits, and each group includes 16 IOs.

[0180] It should be noted that since each group includes 16 IOs, which is less than 64 IOs, alignment can be performed automatically, and the data between groups can be aligned through alignment markers. Specifically, a 72-bit alignment marker can be inserted every 20480*8 bytes of data in each group of data, and subsequently, only the alignment markers at the same position in different groups need to be sent at the same time to ensure the alignment of the sent data.

[0181] Please refer to Figure 8 , Figure 8 A schematic diagram of an alignment mark insertion method provided in an embodiment of the present application.

[0182] like Figure 8 As shown, for each set of data, a 72-bit alignment marker is inserted every 20480*8 bytes of data.

[0183] Exemplarily, the definitions of sixteen groups of data alignment marks may be as shown in Table 1:

[0184]

[0185]

[0186] Table 1

[0187] It should be noted that the above-mentioned definition of the alignment mark is only exemplary, and the value of the alignment mark and the corresponding relationship with the group number can be defined according to actual needs, and the present application does not limit this.

[0188] Based on this, data with alignment marks added is obtained.

[0189] 3) PHY IO physical interface layer

[0190] Since the 1152-bit (1024-bit data + 128-bit check) data is divided into 16 groups, each with 72 bits, the bandwidth of each group is about 29 Gbps (400*1.03125*(1152 / 1024) / 16), and the number of IOs in each group is 16, the IO rate can be about 1.82 Gbps (29 / 16). IO data transmission adopts DDR method: each group contains a pair of differential clocks CK, 16 pairs of differential data DQ, and a total of 34 (1*2+16*2) IO pins are required. The SerDes data corresponding to the second FPGA is further sent to the second FPGA through the corresponding IO pins.

[0191] At this point, the SerDes data sending process of the first FPGA is completed.

[0192] After receiving the data sent by the first FPGA from the IO pin, the second FPGA can merge the received multiple groups of target user data to obtain scrambled reference user data, and descramble the scrambled reference user data to obtain reference user data.

[0193] Please refer to Fig. 9 , Fig. 9 A schematic diagram of the processing process of the IO transmission module in the link layer receiving direction provided in an embodiment of the present application.

[0194] like Fig. 9 As shown in the figure, in the link layer, the specific processing process of each module is as follows:

[0195] First, the received data is processed by bit slip. Since the position of the parallel bit is not necessarily consistent with the transmission when the received data is serial-to-parallel at the physical layer (i.e., the start bits of each group of alignment markers are aligned and sent at the same time, but they may not be received at the same time), it is necessary to perform bit slip according to the alignment marker so that the start bit positions of each group of alignment markers are at the same position.

[0196] Furthermore, the alignment marker is detected through marker check, and the start bit position of the detected alignment marker is returned to the previous bit slip module for bit slip operation to ensure that the start bit position of the alignment marker is at the highest bit of the output parallel data. At the same time, the alignment marker is deleted, and a corresponding mark is added to the start bit position of the alignment marker, and data is cached through the buffer module.

[0197] The out control module detects the marks of all group data in the cache to determine whether all group data have arrived and are aligned. When the conditions are met, all group data are output in parallel at the same time to obtain the scrambled reference user data.

[0198] After obtaining the scrambled reference user data, the scrambled reference user data is descrambled according to the above scrambling method to obtain the reference user data.

[0199] The verification information included in the reference user data is further verified, and if the verification is successful, the reference user data is restored to the SerDes data corresponding to the second FPGA.

[0200] The SerDes data corresponding to the second FPGA is sent through the SerDes of the second FPGA, and the first FPGA and the second FPGA send and receive data at the same time, realizing 800Gbps transmission of Ethernet.

[0201] This concludes the description of Embodiment 1.

[0202] Please refer to Fig.10 , Fig.10 Schematic diagram of a network device proposed in an embodiment of the present application. Fig.10 As shown, the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; a first IO transmission module is deployed in the first FPGA; and a second IO transmission module is deployed in each second FPGA. The network device can be used to execute the method proposed in the above embodiment.

[0203] Please refer to Fig.11 , Fig.11 This is a structural diagram of a data transmission device based on FPGA proposed in an embodiment of the present application. The device is applied to a network device; the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each second FPGA is deployed with a second IO transmission module. Fig.11As shown, the FPGA-based data transmission device may include a processing unit 1101, a determining unit 1102, and a transmitting unit 1103. Specifically, the device includes:

[0204] The processing unit 1101 is configured to perform a first IO processing on the SerDes data corresponding to each second FPGA obtained by using a first IO transmission module deployed in the first FPGA to obtain multiple groups of target user data; the first IO processing refers to: packing the SerDes data corresponding to the second FPGA and adding verification information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data and grouping the scrambled reference user data to obtain multiple groups of target user data;

[0205] A determining unit 1102 is used to determine a transmission rate of a single IO pin and determine N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode;

[0206] The transmission unit 1103 is used to send each target user data to the second FPGA corresponding to the SerDes data through N IO pins according to the transmission rate of a single IO pin, so that the second IO transmission module in the second FPGA performs a second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA; the second IO processing is the inverse process of the first IO processing.

[0207] Optionally, the first FPGA is further configured with an Ethernet processing module; the Ethernet processing module is used to convert the user-side data into SerDes data that can be transmitted through the serial transceiver SerDes; the processing unit 1101 is also used to:

[0208] The received user-side data is converted into target SerDes data through the Ethernet processing module in the first FPGA, and the SerDes data corresponding to the first FPGA in the target SerDes data is sent through the SerDes in the first FPGA; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA;

[0209] The SerDes data corresponding to each second FPGA in the target SerDes data is forwarded to the first IO transmission module through the Ethernet processing module in the first FPGA.

[0210] Optionally, the maximum amount of data allowed to be transmitted at a single time by the SerDes in the first FPGA is M, the data size of the target SerDes data is greater than M, and the data size of the SerDes data corresponding to the first FPGA is M.

[0211] Optionally, the processing unit 1101 is specifically configured to:

[0212] Packing the SerDes data corresponding to the second FPGA according to the obtained data bit width and clock frequency to obtain parallel signal data;

[0213] The parallel signal data is grouped according to a preset size, each group of data is encoded, and a check code corresponding to the group of data is obtained;

[0214] Each set of data and the check code corresponding to each set of data are concatenated and reorganized to obtain reference user data.

[0215] Optionally, the processing unit 1101 is specifically configured to:

[0216] Determine the number of groups of target user data according to the number of IO pins included in the first FPGA;

[0217] Grouping the scrambled reference user data according to the number of target user data groups;

[0218] For each group of data, insert an alignment mark of a second specified length every data of a first specified length to obtain target user data;

[0219] The alignment mark is used to align each group of target user data when transmitting the target user data. Different groups of target user data have different alignment marks inserted, while the same group of target user data has the same alignment marks inserted.

[0220] Optionally, the determining unit 1102 is specifically configured to:

[0221] Determine the transmission rate of each group of target user data according to the target total rate and the number of groups of target user data; the target total rate is determined according to the sum of the data sizes of the SerDes data corresponding to each second FPGA;

[0222] Determine the transmission rate of a single IO pin according to the transmission rate of each group of target user data and the number of IOs corresponding to each group of target user data; the number of IOs included in each group of target user data is determined according to the number of groups of target user data, the maximum transmission rate of the IO pin of the first FPGA, and the target total rate;

[0223] The N IO pins that the SerDes data corresponding to the second FPGA needs to occupy are determined according to the IO quantity corresponding to each group of target user data and the IO data transmission mode.

[0224] Optionally, the second IO processing is:

[0225] Combining the received multiple groups of target user data to obtain scrambled reference user data, and descrambling the scrambled reference user data to obtain reference user data;

[0226] The verification information included in the reference user data is verified, and if the verification succeeds, the reference user data is restored to the SerDes data corresponding to the second FPGA.

[0227] Optionally, the transmission unit 1103 is specifically configured to:

[0228] Setting a designated mark at the start bit position of the alignment mark of each group of target user data, and deleting the alignment mark of each group of target user data;

[0229] Cache the target user data where the alignment mark is deleted;

[0230] When all target user data are cached, multiple groups of target user data are merged according to the positions of designated markers to obtain scrambled reference user data.

[0231] So far, completed Fig.11 Description of the FPGA-based data transmission device.

[0232] Correspondingly, in this embodiment, the embodiment of the present application also provides a computer-readable storage medium, on which a number of computer instructions are stored. When the computer instructions are executed, the method disclosed in the above example of the present application can be implemented.

[0233] Exemplarily, the computer-readable storage medium may be any electronic, magnetic, optical or other physical storage device that may contain or store information, such as executable instructions, data, etc. For example, the computer-readable storage medium may be: RAM (Radom Access Memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard disk drive), solid state drive, any type of storage disk (such as optical disk, DVD, etc.), or similar storage medium, or a combination thereof.

[0234] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A data transmission method based on FPGA, characterized in that: The method is applied to a network device; the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; Each of the second FPGAs is equipped with a second IO transmission module; the method includes: For each obtained SerDes data corresponding to the second FPGA, the first IO transmission module deployed in the first FPGA performs the first IO processing on the SerDes data corresponding to the second FPGA to obtain multiple groups of target user data; the first IO processing refers to: packing the SerDes data corresponding to the second FPGA and adding the check information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data and grouping the scrambled reference user data to obtain multiple groups of target user data; Determine the transmission rate of a single IO pin and determine the N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode; Through N IO pins, each target user data is sent to the second FPGA corresponding to the SerDes data according to the transmission rate of the single IO pin, so that the second IO transmission module in the second FPGA performs second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA; the second IO processing is the reverse process of the first IO processing.

2. The method according to claim 1, characterized in that: The first FPGA is also equipped with an Ethernet processing module; the Ethernet processing module is used to convert the user-side data into SerDes data that can be transmitted through the serial transceiver SerDes; the method further includes: The received user-side data is converted into target SerDes data through the Ethernet processing module in the first FPGA, and the SerDes data corresponding to the first FPGA in the target SerDes data is sent through the SerDes in the first FPGA; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA; The SerDes data corresponding to each second FPGA in the target SerDes data is forwarded to the first IO transmission module through the Ethernet processing module in the first FPGA.

3. The method according to claim 2, characterized in that The maximum amount of data allowed to be transmitted at a single time by the SerDes in the first FPGA is M, the data size of the target SerDes data is greater than M, and the data size of the SerDes data corresponding to the first FPGA is M.

4. The method according to claim 1, characterized in that: Packaging the SerDes data corresponding to the second FPGA and adding verification information corresponding to the SerDes data to obtain reference user data, including: Packing the SerDes data corresponding to the second FPGA according to the obtained data bit width and clock frequency to obtain parallel signal data; The parallel signal data are grouped according to a preset size, and each group of data is encoded to obtain a check code corresponding to the group of data; Each set of data is concatenated with the checksum corresponding to each set of data and then reorganized to obtain reference user data.

5. The method according to claim 1, characterized in that The step of grouping the scrambled reference user data to obtain multiple groups of target user data includes: Determine the number of groups of target user data according to the number of IO pins included in the first FPGA; Grouping the scrambled reference user data according to the number of groups of the target user data; For each group of data, insert an alignment mark of a second specified length every data of a first specified length to obtain target user data; The alignment mark is used to align each group of target user data when transmitting the target user data. Different groups of target user data have different alignment marks inserted, while the same group of target user data has the same alignment marks inserted.

6. The method according to claim 5, characterized in that The determining of the transmission rate of a single IO pin and determining the N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode includes: Determine the transmission rate of each group of target user data according to the target total rate and the number of groups of the target user data; the target total rate is determined according to the sum of the data sizes of the SerDes data corresponding to each second FPGA; Determine the transmission rate of a single IO pin according to the transmission rate of each group of target user data and the number of IOs corresponding to each group of target user data; the number of IOs included in each group of target user data is determined according to the number of groups of the target user data, the maximum transmission rate of the IO pin of the first FPGA, and the target total rate; The N IO pins that the SerDes data corresponding to the second FPGA needs to occupy are determined according to the IO quantity corresponding to each group of target user data and the IO data transmission mode.

7. The method according to claim 5, characterized in that The second IO processing refers to: Combining the received multiple groups of target user data to obtain scrambled reference user data, and descrambling the scrambled reference user data to obtain reference user data; Verify the verification information included in the reference user data, and if the verification succeeds, restore the reference user data to SerDes data corresponding to the second FPGA.

8. The method according to claim 7, characterized in that The step of combining the received multiple groups of target user data to obtain scrambled reference user data includes: Setting a designated mark at the start bit position of the alignment mark of each group of target user data, and deleting the alignment mark of each group of target user data; Cache the target user data where the alignment mark is deleted; When all target user data are cached, multiple groups of target user data are merged according to the positions of the designated marks to obtain scrambled reference user data.

9. A data transmission device based on FPGA, characterized in that: The device is applied to a network device; the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; Each of the second FPGAs is equipped with a second IO transmission module; the device comprises: a processing unit, configured to perform a first IO processing on the SerDes data corresponding to each second FPGA obtained by the first IO transmission module deployed in the first FPGA to obtain multiple groups of target user data; the first IO processing refers to: packing the SerDes data corresponding to the second FPGA and adding the check information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data and grouping the scrambled reference user data to obtain multiple groups of target user data; A determination unit, used to determine a transmission rate of a single IO pin and determine N IO pins that the SerDes data corresponding to the second FPGA needs to occupy based on the IO data transmission mode; A transmission unit is used to send each target user data to a second FPGA corresponding to the SerDes data through N IO pins according to the transmission rate of the single IO pin, so that a second IO transmission module in the second FPGA performs a second IO processing on the received target user data to obtain SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA; the second IO processing is the reverse process of the first IO processing.

10. A network device, characterized in that: The network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each second FPGA is deployed with a second IO transmission module, and the network device is used to execute the method as described in any one of claims 1 to 8.

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