Audio-video data synchronization device and audio-video data synchronization method

Abstract

The invention discloses an audio-video data synchronization device and an audio-video data synchronization method, and relates to the technical field of audio-video data synchronization. The audio-video data synchronization device comprises an audio input circuit, an image input circuit, a processor, an audio output circuit and an image output circuit. The audio input circuit receives an audio input according to a first clock signal. The processor is configured to: store an audio input memory according to a write indicator; processing the image input received by the image input circuit to generate an image output and storing the image output to the memory; an audio input is processed to produce an audio output and stored to a memory. The audio output circuit outputs sub-audio data in the audio output according to the reading index and the second clock signal, and adjusts the second clock signal. The image output circuit reads out the picture frame data in the image output from the memory. The processor determines whether to control the image output circuit to stop outputting according to the timestamp difference between the image frame data and the sub-audio data.

Description

Technical Field

[0001] The present application relates to the technical field of audio and video data synchronization, and in particular to an audio and video data synchronization device and an audio and video data synchronization method. Background Art

[0002] In some related technologies, the audio and video processing device introduces a fixed delay time to a corresponding data in the input image data or audio data so that the corresponding data is synchronized with another data. However, with different application scenarios, the signal processing of the image data or audio data may also change, and the signal processing may introduce delays of different lengths for the image data or the audio data. In this way, the fixed delay time may not be applicable to the needs of different application scenarios. Summary of the invention

[0003] One of the purposes of the present application is to provide an audio and video data synchronization device and an audio and video data synchronization method applicable to multiple scenarios, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, the audio and video data synchronization device includes an audio input circuit, an image input circuit, a processor, an audio output circuit, and an image output circuit. The audio input circuit receives an audio input data from an input interface according to a first clock signal. The image input circuit receives an image input data from the input interface. The processor is used to control the following operations: storing the audio input data to a storage space in a memory according to a write indicator; performing an image processing according to the image input data to generate an image output data, and storing the image output data to the memory; and performing an audio processing according to the audio input data to generate an audio output data, and storing the audio output data to the storage space of the memory. The audio output circuit reads out a plurality of sub-audio data in the audio output data from the storage space according to a read indicator and a second clock signal, and adjusts the second clock signal according to the write indicator, the read indicator and the first clock signal. The image output circuit reads out a plurality of image frame data in the image output data from the memory in sequence. The processor also determines whether to control the image output circuit to stop outputting the current image frame data according to a first difference between an image timestamp corresponding to a current image frame data among the multiple image frame data and an audio timestamp corresponding to a current sub-audio data among the multiple sub-audio data.

[0005] In some embodiments, the audio-visual data synchronization method performed by the audio-visual data synchronization device includes the following operations: receiving an image input data from an input interface, and receiving an audio input data from the input interface according to a first clock signal; storing the audio input data to a storage space in a memory according to a write pointer; performing an image processing according to the image input data to generate an image output data, and storing the image output data to the memory; and performing an audio processing according to the audio input data to generate an audio output data, and storing the audio output data to the storage space of the memory; reading out a plurality of sub-audio data in the audio output data from the storage space according to a read pointer and a second clock signal, and adjusting the second clock signal according to the write pointer, the read pointer and the first clock signal; reading out a plurality of frame data in the image output data from the memory in sequence; and determining whether to stop outputting the current frame data according to a first difference between an image timestamp corresponding to a current frame data in the plurality of frame data and an audio timestamp corresponding to a current sub-audio data in the plurality of sub-audio data.

[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an audio and video data synchronization device according to some embodiments of the present application;

[0008] Figure 2 According to some embodiments of the present application Figure 1 A schematic diagram of the storage space in ;

[0009] Figure 3A According to some embodiments of the present application Figure 1 A flowchart of an audio and video synchronization operation performed by a processor;

[0010] Figure 3B According to some embodiments of the present application Figure 3A a schematic diagram of the first numerical range, the second numerical range and the third numerical range mentioned; and

[0011] Figure 4 A flowchart of a method for synchronizing audio and video data is drawn according to some embodiments of the present application.

[0012] 100: audio and video data synchronization device;

[0013] 101: input interface;

[0014] 102: memory;

[0015] 102A: Storage space;

[0016] 110: audio input circuit;

[0017] 120: image input circuit;

[0018] 130: processor;

[0019] 140: audio output circuit;

[0020] 150: image output circuit;

[0021] 160: audio processing circuit;

[0022] 170: image processing circuit;

[0023] 2[1]~2[m]: sub-storage space;

[0024] 400: audio and video data synchronization method;

[0025] AD1: audio input data;

[0026] AD2: audio output data;

[0027] ATS: audio timestamp;

[0028] CLK1: clock signal;

[0029] CLK2: clock signal;

[0030] EUS: difference;

[0031] ID1: image input data;

[0032] ID2: image output data;

[0033] IF: image frame data;

[0034] ITS: image timestamp;

[0035] L(t): difference;

[0036] LT: target value;

[0037] NS1: first value range;

[0038] NS2: second numerical range;

[0039] NS3: third numerical range;

[0040] RP, RP(t): reading index;

[0041] S310: Operation;

[0042] S320: Operation;

[0043] S330: Operation;

[0044] S340: Operation;

[0045] S350: Operation;

[0046] S360: Operation;

[0047] S410: Operation;

[0048] S420: operation;

[0049] S430: operation;

[0050] S440: Operation;

[0051] S450: Operation;

[0052] S460: Operation;

[0053] S470: Operation;

[0054] SA: sub-audio data;

[0055] TH1, TH1', TH2: critical value;

[0056] WP, WP(t): write indicator. DETAILED DESCRIPTION

[0057] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0058] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0059] Figure 1A schematic diagram of an audio and video data synchronization device 100 is drawn according to some embodiments of the present application. The audio and video data synchronization device 100 includes an audio input circuit 110, an image input circuit 120, a processor 130, an audio output circuit 140, an image output circuit 150, an audio processing circuit 160, and an image processing circuit 170. The audio input circuit 110 and the image input circuit 120 are coupled to an input interface 101 to receive audio input data AD1 and image input data ID1, respectively. In some embodiments, the input interface 101 may be, but is not limited to, a high definition multimedia interface (HDMI), which may provide mixed audio signals and image signals. The audio input circuit 110 and the image input circuit 120 may receive the above signals from the input interface 101, separate the audio input data AD1 and the image input data ID1 from the signals, and store these data in the memory 102.

[0060] The processor 130 may configure a plurality of audio time stamps ATS for the audio input data AD1 according to the relevant information of the audio input data AD1 and the time stamp corresponding to the clock signal received by the processor 130, and store the audio input data AD1 and the audio time stamp ATS in the memory 102. In some embodiments, the memory 102 may be, but is not limited to, a dynamic random access memory. For example, the processor 130 may obtain information related to the sampling rate, data width, number of data items per frame, etc. of the audio input data AD1 from the audio input circuit 110, and configure a plurality of audio time stamps ATS of the audio input data AD1 according to the information and the time stamp corresponding to the processor 130 itself.

[0061] Similarly, the processor 130 may receive the image input data ID1 from the image input circuit 120, and configure multiple image timestamps ITS of the image input data ID1 according to the relevant information of the image input data ID1 and the timestamp corresponding to the processor 130 itself. For example, the processor 130 may obtain information such as the timing of the image frames related to the image input data ID1 from the image input circuit 120, and configure multiple image timestamps ITS corresponding to multiple frames of the image input data ID1 according to this information and the timestamp corresponding to the processor 130 itself. The processor 130 may store the image input data ID1 and the multiple image timestamps ITS in the memory 102.

[0062] In some embodiments, the processor 130 may perform image processing on the image input data ID1 stored in the memory 102 to generate the image output data ID2. In some embodiments, the processor 130 may execute the corresponding image processing software or start the image processing circuit 170 to perform the image processing according to the image input data ID1. In some embodiments, the aforementioned image processing may include, but is not limited to, resolution conversion, format conversion, scaling, cropping, rotation, etc. Similarly, in some embodiments, the processor 130 may perform audio processing on the audio input data AD1 stored in the memory 102 to generate the audio output data AD2. In some embodiments, the processor 130 may execute the corresponding audio processing software or start the audio processing circuit 160 to perform the audio processing according to the audio input data AD1. In some embodiments, the aforementioned audio processing may include, but is not limited to, noise reduction, dynamic range compression, equalization, etc.

[0063] In some embodiments, the processor 130 may store the audio input data AD1 in the storage space 102A of the memory 102 according to the write pointer WP, and store the audio output data AD2 in the storage space 102A. In some embodiments, the storage space 102A may be configured as a first-in-first-out buffer, but the present application is not limited thereto.

[0064] The audio input circuit 110 can receive audio input data AD1 from the input interface 101 according to the clock signal CLK1. For example, the audio input circuit 110 includes a phase-locked loop circuit (not shown), which can generate a clock signal CLK1 with a fixed frequency. The audio output circuit 140 reads out multiple sub-audio data SA of the audio output data AD2 from the aforementioned storage space 102A in sequence according to the read index RP and the clock signal CLK2, and adjusts the clock signal CLK2 according to the write index WP, the read index RP and the clock signal CLK1. For example, the audio output circuit 140 includes a phase-locked loop circuit (not shown), which can generate a frequency-adjustable clock signal CLK2, wherein the frequency of the clock signal CLK2 can be adjusted according to the control of the audio output circuit 140. In this way, it can be ensured that the storage space 102A can store sufficient audio data to be played during the audio output process, so that the audio output process will not be interrupted or lost, so that the user will not experience an intermittent sound experience. The relevant operations here will be referred to below. Figure 2 In some embodiments, the audio output circuit 140 can be implemented by one or more digital circuits, register circuits, and the aforementioned phase-locked loop circuit, but the present application is not limited thereto.

[0065] In some embodiments, information related to the write pointer WP and the read pointer RP may also be stored in the storage space 102A, or in other preset spaces in the memory 102. Similarly, in some embodiments, information related to multiple image timestamps ITS and multiple audio timestamps ATS may also be stored in the memory 102 for use by the processor 130, the audio output circuit 140, the image output circuit 150 and / or other circuits (e.g., including, but not limited to, the audio processing circuit 160, the image processing circuit 170, etc.).

[0066] The image output circuit 150 can read the image output data ID2 from the memory 102 in sequence, and output the multiple frame data in the image output data ID2 in sequence. On the other hand, the processor 130 can also perform a preset operation to synchronize the multiple frame data IF of the image output data ID2 output by the image output circuit 150 with the multiple sub-audio data SA of the audio output data AD2 output by the audio output circuit 140. Specifically, in some embodiments, the processor 130 can determine whether to control the image output circuit 150 to stop outputting the current frame data based on a first difference between an image timestamp corresponding to a current frame data in the multiple frame data IF (for example, a corresponding one of the aforementioned multiple image timestamps ITS) and an audio timestamp corresponding to a current sub-audio data in the multiple sub-audio data SA (for example, a corresponding one of the aforementioned multiple audio timestamps ATS). In this way, the processor 130 can dynamically and in real time adjust the timing and adjustment amount of the image output circuit 150 outputting the frame data, so that the user can experience the audio and video synchronization playback effect. The relevant operations here will be referred to below. Figure 3A In some embodiments, the image output circuit 150 may be implemented by one or more digital circuits, register circuits, image processing modules, etc., but the present application is not limited thereto.

[0067] Figure 2 According to some embodiments of the present application, Figure 1 As can be seen from the above, in some embodiments, the storage space 102A can be configured as a first-in-first-out buffer. Figure 2As shown, the storage space 102A can be divided into a plurality of sub-storage spaces 2[1] to 2[m]. The write pointer WP at time t can be noted as WP(t), and the read pointer RP at time t can be noted as RP(t). The read pointer RP(t) can be used to indicate that the audio output circuit 140 reads out the corresponding sub-audio data from a corresponding sub-storage space (e.g., sub-storage space 2[2]) at time t, and the write pointer WP(t) can be used to indicate that the processor 130 writes the corresponding part of the audio input data AD1 from another corresponding sub-storage space (e.g., sub-storage space 2[m-2]) at time t. In order to ensure that the audio data in the storage space 102A is not read empty, the audio output circuit 140 can read the audio data from the sub-storage space 102A according to the difference L(t) and the sub-storage space 2[m-2]. Figure 1 The target value LT determines the bias value bias(t) corresponding to the current time (e.g., time t), and adjusts the frequency of the clock signal CLK2 according to the bias value bias(t) and the frequency of the clock signal CLK1, wherein the difference value L(t) is the difference between the write index WP(t) and the read index RP(t) corresponding to the current time. In other words, the difference value L(t) can be expressed as: L(t)=WP(t)-RP(t), and the bias value bias(t) can be expressed as: bias(t)=L(t)-LT.

[0068] Further, the audio output circuit 140 may determine the bias value i_bias(t) and the bias value d_bias(t) corresponding to the current time according to the bias value bias(t), and determine the frequency of the clock signal CLK2 at the current time according to the sum of the bias value i_bias(t), the bias value d_bias(t) and the frequency of the clock signal CLK1. In some embodiments, the bias value i_bias(t) corresponding to the current time is the sum of the bias value bias(t) corresponding to the current time and the bias value i_bias(t-1) corresponding to the previous time (e.g., time t-1), which can be expressed as i_bias(t)=bias(t)+i_bias(t-1). On the other hand, the bias value d_bias(t) corresponding to the current time is the difference between the bias value bias(t) corresponding to the current time and the bias value bias(t-1) corresponding to the previous time, which can be expressed as d_bias(t)=bias(t)-bias(t-1). In some embodiments, the audio output circuit 140 can determine the frequency of the clock signal CLK2 at the next time according to the following formula:

[0069] AOP(t+1)=a×bias(t)+b×i_bias(t)+c×d_bias(t)+AIP (1);

[0070] Wherein, AOP(t+1) is the frequency of the clock signal CLK2 at the next time (real time t+1), AIP is the frequency of the clock signal CLK1, and coefficients a, b and c are weight coefficients corresponding to each bias value, which can be configured through prior circuit simulation and / or real-time parameter adaptive adjustment mechanism. After determining the frequency of the clock signal CLK2 at the next time, the audio output circuit 140 can send a corresponding control signal to its internal phase-locked loop circuit to adjust the frequency of the clock signal CLK2.

[0071] Through the above mechanism, the operating frequency of the audio output circuit 140 (e.g., the frequency of the clock signal CLK2) can be dynamically adjusted to ensure that the storage space 102A can store enough audio data to be output (i.e., to be played), thereby avoiding interruption of the played audio. In this way, the user's auditory experience can be improved.

[0072] Figure 3A According to some embodiments of the present application, Figure 1 Flowchart of the operations related to audio and video synchronization performed by the processor 130. In operation S310, a difference is determined based on the image timestamp ITS of the current image frame data IF and the audio timestamp ATS of the current sub-audio data SA. For example, operation S310 can be expressed as follows: EUS=ITS-ATS, where EUS is the difference in operation S310. In operation S320, confirm whether the difference is in the first numerical range, the second numerical range, or the third numerical range. In operation S330, if the difference is in the first numerical range, control the image output circuit 150 to discard the current image frame data IF so as not to output the current image frame data IF. In operation S340, if the difference is in the second numerical range, control the image output circuit 150 to continue to output the current image frame data IF. In operation S350, if the difference is within the third numerical range, the image output circuit 150 is controlled to continuously output and display the current frame data IF, and wait for a preset time period and after the preset time period expires, decide again based on the difference whether to control the image output circuit 150 to stop outputting the current frame data IF.

[0073] For explanation of operation S330, operation S340 and operation S350, please refer to Figure 3B , Figure 3B According to some embodiments of the present application, Figure 3A A schematic diagram of the first numerical range, the second numerical range and the third numerical range mentioned.

[0074] Since the difference EUS represents the difference between the timing of the current image frame data IF and the timing of the current sub-audio data SA, if the difference EUS is a positive number, it means that the current image frame data IF is ahead of the current sub-audio data SA. On the contrary, if the difference EUS is a negative number, it means that the current image frame data IF lags behind the current sub-audio data SA. Figure 3B As shown, the first numerical range NS1 can be defined by a critical value TH1, wherein the critical value TH1 can be a negative number, which can be set to about -30 milliseconds (ms), for example. Therefore, if the difference value EUS is a negative number and is less than the critical value TH1, it means that the difference value EUS is in the first numerical range NS1. Under this condition, it means that the current image frame data IF lags behind the current sub-audio data SA too much, so the processor 130 can control the image output circuit 150 to discard the current image frame data IF (i.e., operation S330) to abandon the display of the current image frame data IF, thereby speeding up the display of the next image frame data IF. In other words, if the current image frame data IF lags behind the current sub-audio data SA too much, the processor 130 can abandon the display of part of the current image frame data IF accordingly to reduce the delay of image display. In some other embodiments, the first numerical range NS1 can be defined by a critical value TH1 and a critical value TH1', wherein the critical value TH1' is a negative number less than the critical value TH1, for example, the critical value TH1' can be configured to be about -500 milliseconds. Under this condition, if the difference value EUS is greater than or equal to the threshold value TH1 ′ and less than the threshold value TH1 , it means that the difference value EUS is located in the first value range NS1 .

[0075] The second numerical range NS2 can be defined by a threshold value TH1 and a threshold value TH2, wherein the threshold value TH2 can be a positive number, which can be set to about 50 milliseconds, for example. Therefore, if the difference value EUS is greater than or equal to the threshold value TH1 and less than the threshold value TH2, it means that the difference value EUS is in the second numerical range NS2. Under this condition, it means that the current image frame data IF is close to (i.e., roughly synchronized with) the current sub-audio data SA, so the processor 130 can control the image output circuit 150 to continuously output the current image frame data IF (i.e., operation S340).

[0076] The third numerical range NS3 can be defined by the threshold value TH2. Therefore, if the difference value EUS is greater than or equal to the threshold value TH2, it means that the difference value EUS is in the third numerical range NS3. Under this condition, it means that the current image frame data IF is too much ahead of the current sub-audio data SA. Therefore, the processor 130 can control the image output circuit 150 to continuously output and display the current image frame data IF and wait for a preset time period (for example, about, but not limited to, 10 milliseconds) (i.e., operation S360). In this way, the display time of the current image frame data IF can be delayed. After the preset time period expires, the processor 130 can again determine whether to control the image output circuit 150 to stop outputting the current image frame data IF according to the difference value EUS (i.e., perform operation S330 again after the preset time period expires). In other words, since the sensitivity of the human ear is usually much greater than the sensitivity of the human eye, if the timing of the current image frame data IF is too far ahead of the timing of the current sub-audio data SA, the processor 130 can continue to display the current image frame data IF being displayed and wait for the aforementioned preset time period. After the preset time period expires, the processor 130 may perform the same operation again to confirm whether to adjust the image output circuit 150 to stop displaying the current frame data IF, so as to confirm whether to adjust the audio-video synchronization at the next timing.

[0077] Through the above synchronization mechanism, the processor 130 can dynamically adjust the timing of the image output circuit 150 outputting the corresponding image frame data IF according to the image timestamp ITS corresponding to the current image frame data IF and the audio timestamp ATS corresponding to the current sub-audio data SA, so that the timing of the image frame data display can be synchronized with the timing of the sub-audio data playback. In this way, the processor 130 can synchronize the image output data ID2 that has undergone different image processing with the audio output data AD2 that has undergone different audio processing in different scenarios, thereby providing a better user experience.

[0078] In some related technologies, the audio and video processing device adjusts one of the image data or audio data to be played by setting a fixed delay time so that it can be synchronized with the other of the image data or the audio data. However, if the usage scenarios of the audio and video processing device are different, the corresponding image processing or audio processing performed by it may be different, resulting in the fixed delay time may not be able to synchronize the above two data with each other correctly. Under this condition, it is also necessary to retest the audio and video processing device set in the scenario to find a suitable delay time again. Compared with the above technology, in some embodiments of the present application, the processor 130 dynamically adjusts the display timing of the image frame data according to the respective timestamps of the image data and the audio data. In this way, the synchronization of audio and video data can be achieved in real time in different scenarios.

[0079] Figure 4A flowchart of a method 400 for synchronizing audio and video data is drawn according to some embodiments of the present application. In some embodiments, the operation of the method 400 for synchronizing audio and video data may be performed by, but not limited to, Figure 1 The audio and video data synchronization device 100 is executed.

[0080] In operation S410, an image input data is received from an input interface, and an audio input data is received from the input interface according to a first clock signal. In operation S420, the audio input data is stored in a storage space in a memory according to a write indicator. In operation S430, an image processing is performed according to the image input data to generate an image output data, and the image output data is stored in the memory. In operation S440, an audio processing is performed according to the audio input data to generate an audio output data, and the audio output data is stored in the storage space of the memory. In operation S450, a plurality of sub-audio data in the audio output data is read out from the storage space according to a read indicator and a second clock signal, and the second clock signal is adjusted according to the write indicator, the read indicator and the first clock signal. In operation S460, a plurality of frame data in the image output data is read out from the memory in sequence. In operation S470 , it is determined whether to stop outputting the current frame data according to a first difference between an image timestamp corresponding to a current frame data among the plurality of frame data and an audio timestamp corresponding to a current sub audio data among the plurality of sub audio data.

[0081] The description of the multiple operations of the above-mentioned audio and video data synchronization method 400 can refer to the above-mentioned multiple embodiments, so it will not be repeated here. The above-mentioned multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, the various operations under the audio and video data synchronization method 400 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the audio and video data synchronization method 400 can be performed simultaneously or partially simultaneously.

[0082] In summary, the audio and video data synchronization device and the audio and video data synchronization method provided in some embodiments of the present application can adjust the operating frequency of the audio output circuit according to the actual data access amount during the process of outputting audio data to avoid interruption of the audio output, and can dynamically adjust the display timing of the frame data according to the timestamp of the current frame and the timestamp of the current audio, so that the playback process of the audio and video data in various scenarios can be nearly synchronized, thereby improving the overall user experience.

[0083] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. An audio and video data synchronization device, characterized in that: include: an audio input circuit, receiving an audio input data from an input interface according to a first clock signal, and; An image input circuit receives image input data from the input interface; A processor for controlling the following operations: storing the audio input data to a storage space in a memory according to a write indicator; Performing an image processing according to the image input data to generate an image output data, and storing the image output data in the memory; as well as Performing an audio process according to the audio input data to generate an audio output data, and storing the audio output data in the storage space of the memory; an audio output circuit, reading out a plurality of sub-audio data in the audio output data from the storage space according to a read indicator and a second clock signal, and adjusting the second clock signal according to the write indicator, the read indicator and the first clock signal; and an image output circuit, which reads out a plurality of image frame data in the image output data from the memory in sequence; The processor further determines whether to control the image output circuit to stop outputting the current image frame data according to a first difference between an image timestamp corresponding to a current image frame data among the multiple image frame data and an audio timestamp corresponding to a current sub-audio data among the multiple sub-audio data.

2. The audio-visual data synchronization device according to claim 1, wherein: The audio output circuit determines a first bias value corresponding to a current time according to a difference between a second difference and a target value, and adjusts the frequency of the second clock signal according to the first bias value and the frequency of the first clock signal, and the second difference is the difference between the write indicator and the read indicator corresponding to the current time.

3. The audio-visual data synchronization device as claimed in claim 2, characterized in that: The audio output circuit determines a second bias value and a third bias value corresponding to the current time according to the first bias value, and determines the frequency of the second clock signal at a time according to the sum of the first bias value, the second bias value, the third bias value and the frequency of the first clock signal corresponding to the current time.

4. The audio-visual data synchronization device as claimed in claim 3, characterized in that: The second bias value corresponding to the current time is the sum of the first bias value corresponding to the current time and the second bias value corresponding to a previous time, and the third bias value corresponding to the current time is the difference between the first bias value corresponding to the current time and the first bias value corresponding to the previous time.

5. The audio-visual data synchronization device as claimed in claim 1, characterized in that: When the first difference is a negative number and is smaller than a critical value, the processor controls the image output circuit to discard the current image frame data so as not to output the current image frame data.

6. The audio-visual data synchronization device as claimed in claim 1, characterized in that: When the first difference is greater than or equal to a first threshold and less than a second threshold, the processor controls the image output circuit to continuously output the current image frame data.

7. The video and audio data synchronization device as claimed in claim 6, characterized in that: The first threshold is a negative number, and the second threshold is a positive number.

8. The audio-visual data synchronization device as claimed in claim 1, characterized in that: When the first difference is a positive number and is greater than or equal to a critical value, the processor controls the image output circuit to continuously output and display the current frame data, waits for a preset time period, and after the preset time period expires, decides again based on the first difference whether to control the image output circuit to stop outputting the current frame data.

9. A method for synchronizing audio and video data, characterized in that: Executed by an audio and video data synchronization device, the audio and video data synchronization method includes: receiving an image input data from an input interface, and receiving an audio input data from the input interface according to a first clock signal; storing the audio input data to a storage space in a memory according to a write indicator; Performing an image processing according to the image input data to generate an image output data, and storing the image output data in the memory; Performing an audio process according to the audio input data to generate an audio output data, and storing the audio output data in the storage space of the memory; Reading a plurality of sub-audio data in the audio output data from the storage space according to a read indicator and a second clock signal, and adjusting the second clock signal according to the write indicator, the read indicator and the first clock signal; Reading out a plurality of image frame data in the image output data from the memory in sequence; and Whether to stop outputting the current frame data is determined according to a first difference between an image timestamp corresponding to a current frame data among the plurality of frame data and an audio timestamp corresponding to a current sub-audio data among the plurality of sub-audio data.

10. The method for synchronizing audio and video data as claimed in claim 9, wherein: Adjusting the second clock signal according to the write indicator, the read indicator, and the first clock signal includes: Determining a first offset value corresponding to a current time according to a difference between a second difference value and a target value; and adjusting the frequency of the second clock signal according to the first offset value and the frequency of the first clock signal, The second difference is the difference between the write index and the read index corresponding to the current time.

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