Hall integrated chip for horizontal direction detection

Abstract

The present application relates to the field of semiconductor technology, and in particular to a Hall integrated chip for horizontal direction detection, wherein the Hall integrated chip comprises a first Hall chip and a second Hall chip, the first Hall chip and the second Hall chip are arranged adjacent to each other, the output end of the first Hall chip and the output end of the second Hall chip are connected in parallel, the positive and negative potentials generated by the first Hall chip and the second Hall chip under the interference of the vertical magnetic field cancel each other out, a first magnetic focusing structure is arranged on the first Hall chip, and a second magnetic focusing structure is arranged on the second Hall chip, the target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction are serrated, and the target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction have an angle of deviation from the vertical direction of 0 degrees to 10 degrees. The Hall integrated chip for horizontal direction detection provided in the present application has a simple production process, strong anti-interference ability, a large measuring range, and high detection accuracy.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit design and manufacturing, and in particular to a Hall integrated chip for horizontal direction detection. Background Art

[0002] The horizontal direction detection current sensor refers to a sensor used to detect the current in the horizontal direction. In the related technology, the horizontal direction detection current sensor is mainly prepared by complementary metal oxide semiconductor (CMOS) standard process, vertical process, tunneling magnetoresistance technology (TMR) type magnetic field sensitive element, etc.

[0003] However, the CMOS standard process requires the preparation of the magnetic field concentrator to be carried out together with the Hall process during wafer tape-out, which results in high production costs and difficulty in the production process. In addition, the zero-position bias (zero bias) and signal-to-noise ratio of the Hall signal itself are low, resulting in insufficient sensitivity and weak anti-interference ability. In addition, due to the necessity to use the wafer-end process, the thickness of the magnetic field concentrator added above the wafer is generally limited to within 50um, which greatly limits the concentrated magnetic field and bias capabilities of the magnetic field concentrator, resulting in relatively low magnetic field conversion efficiency and even more insufficient sensitivity, making it unsuitable for measurements of smaller currents. The Hall sensitivity produced by the vertical production process is low, and the signal-to-noise ratio is poor, which greatly reduces the measurement accuracy. TMR-type magnetic field sensitive elements cannot work for a long time in a strong magnetic field environment, and are not suitable for the manufacture of current sensors with large currents. When a strong magnetic field approaches, the TMR will be severely interfered with and the output will be unbalanced, causing the current sensor to work abnormally and ultimately degrade its performance.

[0004] Therefore, it is particularly important to provide a Hall integrated chip for horizontal direction detection with simple production process, strong anti-interference ability, large measuring range and high detection accuracy. Summary of the invention

[0005] The present application provides a Hall integrated chip for horizontal direction detection to at least solve the above-mentioned problems existing in the related art.

[0006] In order to solve the above technical problems, the technical solution of this application is as follows:

[0007] According to a first aspect of an embodiment of the present application, a Hall integrated chip for horizontal direction detection is provided, wherein the Hall integrated chip comprises a first Hall chip and a second Hall chip, wherein the first Hall chip and the second Hall chip are arranged adjacent to each other, an output end of the first Hall chip and an output end of the second Hall chip are connected in parallel, and positive and negative potentials generated by the first Hall chip and the second Hall chip under vertical magnetic field interference cancel each other out;

[0008] A first magnetic focusing structure is arranged on the first Hall chip, and a second magnetic focusing structure is arranged on the second Hall chip. The target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction are both serrated. The target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction have an angle of deviation from the vertical direction of 0 degrees to 10 degrees.

[0009] The jagged target edge includes grooves, concave points and convex points, the angle at the concave points is 20 degrees to 120 degrees, the size of the convex points in the vertical direction is 0 μm to 20 μm, and the size of the grooves in the vertical direction is 5 μm to 30 μm.

[0010] In an optional embodiment, the thickness of the first magnetic field focusing structure and the thickness of the second magnetic field focusing structure are both greater than or equal to 60 μm.

[0011] In an optional embodiment, the first magnetic field focusing structure and the second magnetic field focusing structure are both in the shape of square columns, or the first magnetic field focusing structure and the second magnetic field focusing structure are both in the shape of columns with a trapezoidal side view.

[0012] In an optional embodiment, a partial area of ​​the first magnetic focusing structure is arranged on the first Hall chip and covers the Hall sensing area of ​​the first Hall chip, and a ratio of an area of ​​the partial area on the first Hall chip covered by the first magnetic focusing structure to an area of ​​the first magnetic focusing structure is greater than or equal to 1 / 4;

[0013] A partial area of ​​the second magnetic concentrating structure is arranged on the second Hall chip and covers the Hall sensing area of ​​the second Hall chip. The ratio of the area of ​​the partial area covered by the second magnetic concentrating structure on the second Hall chip to the area of ​​the second magnetic concentrating structure is greater than or equal to 1 / 4.

[0014] In an optional embodiment, the bottoms of the first magnetic focusing structure and the second magnetic focusing structure are both rectangular, a vertex corner of the bottom of the first magnetic focusing structure is located on the first Hall chip, and a vertex corner of the bottom of the second magnetic focusing structure is located on the second Hall chip;

[0015] A top angle of the bottom of the first magnetic focusing structure is arranged opposite to a top angle of the bottom of the second magnetic focusing structure; or, an edge of the bottom of the first magnetic focusing structure is in the same straight line with the center line of the first Hall chip in the horizontal direction, and an edge of the bottom of the second magnetic focusing structure is in the same straight line with the center line of the second Hall chip in the horizontal direction.

[0016] In an optional embodiment, the first magnetic focusing structure is mounted on the first Hall chip by glue, and the second magnetic focusing structure is mounted on the second Hall chip by glue.

[0017] In an optional embodiment, the first magnetic field focusing structure and the second magnetic field focusing structure are respectively mounted on the first Hall chip and the second Hall chip through films with uniform thickness.

[0018] In an optional embodiment, a third magnetic field focusing structure is further provided at the bottom of the first Hall chip and the second Hall chip;

[0019] There is a first overlapping part between the first projection of the third magnetic focusing structure on the first Hall chip and the second projection of the first magnetic focusing structure on the first Hall chip; there is a second overlapping part between the third projection of the third magnetic focusing structure on the second Hall chip and the fourth projection of the second magnetic focusing structure on the second Hall chip.

[0020] In an optional embodiment, the first projection and the second projection both cover the Hall sensing area of ​​the first Hall chip, and the third projection and the fourth projection both cover the Hall sensing area of ​​the second Hall chip.

[0021] The ratio of the area of ​​the first overlapping portion to the area of ​​the first Hall chip is in the range of 1 / 5 to 1, and the ratio of the area of ​​the second overlapping portion to the area of ​​the second Hall chip is in the range of 1 / 5 to 1.

[0022] The Hall integrated chip provided in the embodiment of the present application includes a first Hall chip and a second Hall chip, wherein the first Hall chip and the second Hall chip are arranged adjacent to each other, and the output end of the first Hall chip and the output end of the second Hall chip are connected in parallel, and this connection mode makes the dual Hall output a differential signal. The zero bias of the two Halls is offset due to the orthogonal working current and this differential design, and the output signals thereof are connected in parallel to improve the signal-to-noise ratio. In addition, the characteristic of canceling the same-direction signals enables it to have a strong anti-interference ability: when there is magnetic field interference in the vertical direction, the outputs of the two Hall interference items can cancel each other because of their close distance and one positive and one negative, thereby enhancing the anti-interference ability of the terminal current sensor product. In addition, a magnetic concentrator structure is also provided on the Hall chip, and the target edge of the magnetic concentrator structure in the vertical direction is serrated, and the target edge of the magnetic concentrator structure in the vertical direction has an angle of deviation from the vertical direction of 0 degrees to 10 degrees. The serrated structure makes the ability of the final prepared current sensor to bias the magnetic field in the horizontal direction more concentrated. On the basis of the design of the original magnetic field concentrator, the effect of the magnetic field bias is enhanced. This allows the sensing unit to obtain more biased magnetic fields, further reducing the interference of magnetic fields in other directions on the product and improving the signal-to-noise ratio of the entire module. In addition, the strengthening of the magnetic field bias makes the linear output range of the final current sensor wider, which can increase the effective range and reduce signal errors, thereby improving the stability and accuracy of the final signal.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute an improper limitation on the present application.

[0025] Figure 1 This is a schematic diagram of the input and output circuits of a Hall integrated chip provided in an embodiment of the present application.

[0026] Figure 2 This is a side view of a magnetic focusing structure provided in an embodiment of the present application installed on a Hall chip.

[0027] Figure 3 It is a side view of a magnetic focusing structure provided in an embodiment of the present application.

[0028] Figure 4 It is a schematic diagram of a target edge provided in an embodiment of the present application.

[0029] Figure 5 It is a schematic diagram of a combination of a Hall integrated chip and a back-end circuit provided in an embodiment of the present application.

[0030] Figure 6 This is a side view of another magnetic focusing structure provided in an embodiment of the present application installed on a Hall chip.

[0031] Figure 7 It is a schematic diagram of magnetic field distribution in a simulation model provided in an embodiment of the present application.

[0032] The following is a supplementary explanation of the reference numerals:

[0033] 1-first Hall chip, 2-second Hall chip, 3-first soldering pad, 4-second soldering pad, 5-third soldering pad, 6-fourth soldering pad, 7-first magnetic focusing structure, 8-second magnetic focusing structure, 9-grooves, 10-concave points, 11-bumps, 12-third magnetic focusing structure. DETAILED DESCRIPTION

[0034] The following content provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of the components and configurations described below are disclosed in a simplified manner. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of the first feature above or on the second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the application may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0035] Additionally, spatially relative terms, such as "below," "beneath," "lower," "on," "upper," "front," "back," "above," and the like, may be used in this application for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0036] An embodiment of the present application provides a Hall integrated chip for horizontal direction detection, wherein the Hall integrated chip includes a first Hall chip and a second Hall chip, wherein the first Hall chip and the second Hall chip are adjacently arranged, and an output end of the first Hall chip and an output end of the second Hall chip are connected in parallel, and positive and negative potentials generated by the first Hall chip and the second Hall chip under vertical magnetic field interference cancel each other out.

[0037] A first magnetic focusing structure is arranged on the first Hall chip, and a second magnetic focusing structure is arranged on the second Hall chip. The target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction are both serrated. The target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction have an angle of deviation from the vertical direction of 0 degrees to 10 degrees.

[0038] The embodiment of the present application adopts an out-of-phase parallel dual Hall structure as the sensitive core. A Hall pair is composed of two cross-structure Hall chips. The two Hall chips are two Hall chips that are closely adjacent to each other on the manufacturing wafer. After wafer cutting, multiple independent dual Hall integrated chips can be directly obtained, which is essentially different from the traditional method of packaging two independent Hall chips together. In this way, the performance of the two Hall chips can be guaranteed to be similar and the zero bias is similar. In addition, the area occupied is small and the cost is low.

[0039] Figure 1 is a schematic diagram of the input and output circuits of a Hall integrated chip provided in an embodiment of the present application, such as Figure 1As shown, the Hall integrated chip includes a first Hall chip 1 and a second Hall chip 2, and the input ends of the first Hall chip 1 and the second Hall chip 2 are connected in series to facilitate simultaneous power supply. The output ends of the first Hall chip 1 and the second Hall chip 2 use a parallel wiring structure to achieve signal extraction. The first Hall chip 1 includes electrodes A1, A2, A3, and A4. The power supply ends of the first Hall chip 1 are A1 and A3, A1 is the positive power supply electrode, A3 is the negative power supply electrode, and the output ends are A2 and A4. A2 and A4 output Hall potential vertically, A2 is the positive Hall potential electrode, and A4 is the negative Hall potential electrode. The second Hall chip 2 includes electrodes B1, B2, B3, and B4. The power supply ends are B1 and B3, and the output ends are B2 and B4. B2 and B4 output Hall potential horizontally, B4 is the positive Hall electrode, and B2 is the negative Hall electrode.

[0040] Continue as Figure 1 As shown, A1 and B1 are connected, and a first pad 3 is set on the connecting line, A3 and B3 are connected, and a third pad 5 is set on the connecting line. A2 and B2 are connected, and a second pad 4 is set on the connecting line, and A4 and B4 are connected, and a fourth pad 6 is set on the connecting line. Thus, a voltage can be applied between the first pad 3 and the third pad 5 to generate a Hall potential between the second pad 4 and the fourth pad 6, or a voltage can be applied between the second pad 4 and the fourth pad 6 to generate a Hall potential between the first pad 3 and the third pad 5.

[0041] Therefore, through the above connection, the dual Hall outputs are one positive and one negative, so that the longitudinal potential generated by the first Hall chip 1 and the transverse potential generated by the second Hall chip 2 are offset, which will directly shield the vertical magnetic field without generating any output. The final output calculation equation is Vh= (VHall1+VHall2) / 2, where VHall1 refers to the output of the first Hall chip 1, and VHall2 refers to the output of the second Hall chip 2. Based on this structure, when the vertical magnetic field interferes with the chip body, the output of the chip will be zero due to the anisotropic design, effectively avoiding the interference of the vertical magnetic field. And its output signal is connected in parallel to improve the signal-to-noise ratio. In addition, the characteristic of canceling the same-direction signal makes it have a strong anti-interference ability: when there is vertical magnetic field interference, the output of the two Hall interference items is the same because they are very close and can cancel each other out, which will enhance the anti-interference ability of the terminal current sensor product.

[0042] The embodiment of the present application further installs a magnetic field focusing structure above the Hall chip, and the entire magnetic field focusing structure adopts a sawtooth structure design. Figure 2 This is a side view of a magnetic field collecting structure provided in an embodiment of the present application installed on a Hall chip. Figure 3 is a side view of a magnetic field focusing structure provided in an embodiment of the present application, such as Figure 2 and Figure 3As shown, a first magnetic focusing structure 7 is arranged on the first Hall chip 1, and a second magnetic focusing structure 8 is arranged on the second Hall chip 2. The target edges of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 in the vertical direction are both serrated. The target edges of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 in the vertical direction have an angle of deviation from the vertical direction of 0 degrees to 10 degrees.

[0043] It should be noted that the vertical direction is the stacking direction of the Hall chip and the magnetic concentrator structure. The target edge of the vertical direction is an edge parallel to the vertical direction, in which case the angle of deviation from the vertical direction is 0 degrees; or the target edge of the vertical direction is an edge that deviates from the vertical direction by a preset angle, in which case the preset angle of deviation from the vertical direction is greater than 0 degrees and less than 10 degrees.

[0044] The embodiment of the present application uses a sawtooth magnetic concentrator structure to make the ability (gain) of the final current sensor to bias the horizontal magnetic field more than double that of the traditional magnetic concentrator (IMC), reduce the hysteresis effect, and increase the magnetic field saturation point by more than 2 times. The increased gain allows the Hall sensing area to obtain more effective magnetic fields, reduce the interference of magnetic fields in other directions on the product, and improve the signal-to-noise ratio. In addition, the reduction in hysteresis will enhance signal linearity, and the improvement in magnetic saturation performance will make the linear output range of the final current sensor wider, increase the effective range, reduce signal errors, and improve the stability and accuracy of the final signal.

[0045] It should be noted that the embodiment of the present application does not limit the shape and size of the first magnetic focusing structure 7 and the second magnetic focusing structure 8. In order to ensure that the output of the chip will be zero due to the anisotropic design and effectively avoid the interference of the vertical magnetic field, the shape, size and installation direction of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 can be the same.

[0046] In one embodiment, the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are structures that are consistent from top to bottom. For example, the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are both square columns. At this time, the four vertical edges of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are target edges, and the four target edges are serrated, and the angles of the four target edges that deviate from the vertical direction are all 0 degrees.

[0047] In another embodiment, the side view of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are structures that are small at the top and large at the bottom. For example, the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are both columnar with a trapezoidal side view. At this time, the four vertical edges of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are target edges, and the four target edges are serrated, and the angle of the four target edges deviating from the vertical direction is greater than 0 degrees and less than 10 degrees.

[0048] In another embodiment, the side view of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are structures that are larger at the top and smaller at the bottom. For example, the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are both columns that are inverted trapezoidal in side view. At this time, the four vertical edges of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are target edges, and the four target edges are serrated, and the angle of the four target edges deviating from the vertical direction is greater than 0 degrees and less than 10 degrees.

[0049] In the embodiment of the present application, the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are both set to a square column, or the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are both set to a column with a trapezoidal side view, so that when a horizontal magnetic field passes through, the square column or the columnar magnetic focusing structure with a trapezoidal side view can deflect part of the horizontal magnetic field into a vertical magnetic field, so that the chip senses a horizontal current. At the same time, due to the sawtooth structure design, the efficiency of the deflection part of the magnetic focusing structure is improved, and the signal-to-noise ratio of the final prepared current sensor and the detection accuracy of the current sensor are simultaneously improved.

[0050] In an optional embodiment, the thickness of the first magnetic focusing structure 7 and the thickness of the second magnetic focusing structure 8 are both greater than or equal to 60 μm. This design can improve the magnetic field bias capability, thereby improving the magnetic field conversion efficiency and detection sensitivity, and can be applied to measurements of smaller currents. Furthermore, this design can avoid reaching magnetic saturation too early and reduce the residual magnetic effect, so that the linear output range of the final prepared current sensor is wider, the effective range can be increased, and the signal error can be reduced, thereby improving the stability and accuracy of the final signal.

[0051] In an optional embodiment, the jagged target edge includes grooves, concave points and convex points, the angle at the concave points is 20 degrees to 120 degrees, the height of the convex points in the vertical direction ranges from 0 μm to 20 μm, and the size of the grooves in the vertical direction ranges from 5 μm to 30 μm.

[0052] Figure 4 is a schematic diagram of a target edge provided in an embodiment of the present application, such as Figure 4 As shown, the jagged target edge includes gullies 9, concave points 10 and convex points 11, wherein the gullies 9 refer to the triangular gaps formed by the cutting tool being sunken inward along the target edge, the concave points 10 refer to the vertices of the triangular gaps, and the convex points 11 refer to the portions of the target edge that are not cut by the cutting tool.

[0053] Exemplarily, the size range h1 of the convex point 11 in the vertical direction may be 0 μm-20 μm. When the size is 0, the convex point 11 may be a point. When the size is greater than 0, the convex point 11 is a line segment.

[0054] Exemplarily, the vertical dimension of the gully 9 may be the length of the base of the triangular notch, and the dimension range h2 may be 5 μm-30 μm.

[0055] For example, the angle at the concave point 10 may refer to the angle θ between the two sides of the triangular notch, which may be 20 degrees to 120 degrees.

[0056] The embodiment of the present application can further improve the ability to bias the horizontal magnetic field by designing the gullies 9, convex points 11 and concave points 10 of the jagged target edge as described above, so that the ability (gain) of the current sensor finally prepared to bias the horizontal magnetic field is more than doubled compared to the traditional magnetic collector (IMC), the hysteresis effect is reduced, and the magnetic field saturation point is increased by more than 2 times. The increased gain allows the Hall sensing area to obtain more effective magnetic fields, reduces the interference of magnetic fields in other directions on the product, and improves the signal-to-noise ratio. In addition, the reduction of hysteresis will enhance the signal linearity, and the improved performance of magnetic saturation will make the linear output range of the final current sensor wider, increase the effective range, reduce signal errors, and improve the stability and accuracy of the final signal.

[0057] In other embodiments, the groove may also be a notch of other shapes, such as an arc-shaped notch, a rectangular notch, an S-shaped notch, etc.

[0058] In an optional embodiment, a partial area of ​​the first magnetic focusing structure 7 is arranged on the first Hall chip 1 and covers the Hall sensing area of ​​the first Hall chip 1, and the ratio of the area of ​​the partial area covered by the first magnetic focusing structure 7 on the first Hall chip 1 to the area of ​​the first magnetic focusing structure 7 is greater than or equal to 1 / 4;

[0059] A partial area of ​​the second magnetic concentrating structure 8 is arranged on the second Hall chip 2 and covers the Hall sensing area of ​​the second Hall chip 2. The ratio of the area of ​​the partial area covered by the second magnetic concentrating structure 8 on the second Hall chip 2 to the area of ​​the second magnetic concentrating structure 8 is greater than or equal to 1 / 4.

[0060] In this embodiment, when the magnetic focusing structure is installed on the Hall chip, the magnetic focusing chip needs to ensure that at least 1 / 4 of the area is pressed on the corresponding Hall chip, and this area needs to completely cover the Hall sensing area of ​​the corresponding Hall chip. Furthermore, the cross center of the corresponding Hall chip can be completely covered. Thus, through this setting, the directions of the magnetic fields felt by the dual Hall chips connected in parallel in opposite directions are also different, and the final outputs are added. It is easier to eliminate the interference of stray magnetic fields and improve the signal-to-noise ratio.

[0061] In an optional embodiment, the bottoms of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are both rectangular, a vertex of the bottom of the first magnetic focusing structure 7 is located on the first Hall chip 1, and a vertex of the bottom of the second magnetic focusing structure 8 is located on the second Hall chip 2;

[0062] A top corner of the bottom of the first magnetic focusing structure 7 is arranged opposite to a top corner of the bottom of the second magnetic focusing structure 8; or, an edge of the bottom of the first magnetic focusing structure 7 is in the same straight line with the center line of the first Hall chip 1 in the horizontal direction, and an edge of the bottom of the second magnetic focusing structure 8 is in the same straight line with the center line of the second Hall chip 2 in the horizontal direction.

[0063] In this embodiment, since part of the first magnetic focusing structure 7 is arranged on the first Hall chip 1, a vertex of the bottom of the first magnetic focusing structure 7 can be arranged on the first Hall chip 1, and similarly, a vertex of the bottom of the second magnetic focusing structure 8 can be arranged on the second Hall chip 2. On this basis, the first magnetic focusing structure 7 and the second magnetic focusing structure 8 can be arranged in a relative manner of vertex to vertex, or in a side to side arrangement.

[0064] Optionally, for relative settings, after a top angle of the bottom of the first magnetic focusing structure 7 is set relative to a top angle of the bottom of the second magnetic focusing structure 8, the acute angle between the center line of the first Hall chip 1 in the horizontal direction and the edge of the bottom of the first magnetic focusing structure 7 is 30 to 60 degrees, and the acute angle between the center line of the second Hall chip 2 in the horizontal direction and the edge of the bottom of the second magnetic focusing structure 8 is 30 to 60 degrees. The magnetic focusing structure is rotated 30 to 60 degrees and then installed on the Hall chip. This installation method can improve the horizontal magnetic field bias capability, so that the ability (gain) of the prepared current sensor to bias the horizontal magnetic field is more than doubled than that of the traditional IMC, thereby further improving the ability to resist interference from the vertical magnetic field.

[0065] Figure 5 is a schematic diagram of a combination of a Hall integrated chip and a back-end circuit provided in an embodiment of the present application, such as Figure 5As shown, the bottoms of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 are both rectangular. When the first magnetic focusing structure 7 is installed on the first Hall chip 1, the first magnetic focusing structure 7 can be pre-aligned so that one edge of the bottom of the first magnetic focusing structure 7 is parallel to the center line of the first Hall chip 1 in the horizontal direction. Then, the first magnetic focusing structure 7 is rotated by a preset angle in a clockwise or counterclockwise direction so that the acute angle between the center line of the first Hall chip 1 in the horizontal direction and the edge of the bottom of the first magnetic focusing structure 7 is the preset angle. Similarly, when the second magnetic focusing structure 8 is installed on the second Hall chip 2, the second magnetic focusing structure 8 can be pre-aligned so that one edge of the bottom of the second magnetic focusing structure 8 is parallel to the center line of the second Hall chip 2 in the horizontal direction. Then, the second magnetic focusing structure 8 is rotated by a preset angle in a clockwise or counterclockwise direction so that the acute angle between the center line of the second Hall chip 2 in the horizontal direction and the edge of the bottom of the second magnetic focusing structure 8 is the preset angle.

[0066] It should be noted that the preset angle can be 30 to 60 degrees, preferably 45 degrees. When the preset angle is 45, the top angle of the first magnetic focusing structure 7 is rotated to the center of the first Hall chip 1, and the top angle of the second magnetic focusing structure 8 is rotated to the center of the second Hall chip 2.

[0067] Optionally, for the edge-to-edge setting, one edge of the bottom of the first magnetic focusing structure is in the same straight line with the center line of the first Hall chip in the horizontal direction, and one edge of the bottom of the second magnetic focusing structure is in the same straight line with the center line of the second Hall chip in the horizontal direction.

[0068] The embodiment of the present application can improve the detection sensitivity by arranging the first magnetic focusing structure 7 and the second magnetic focusing structure 8 relative to each other, and can increase the installation tolerance by arranging the first magnetic focusing structure 7 and the second magnetic focusing structure 8 side by side, thereby reducing the installation difficulty and cost.

[0069] It should be noted that the magnetic focusing structure can be connected to the corresponding Hall chip in any manner, and no specific limitation is made thereto.

[0070] In an optional embodiment, the first magnetic focusing structure 7 is mounted on the first Hall chip 1 by glue, and the second magnetic focusing structure 8 is mounted on the second Hall chip 2 by glue. By mounting the magnetic focusing structure on the corresponding Hall chip by glue, the mounting difficulty and cost can be reduced, and the consistency of the Hall integrated chip can be ensured.

[0071] In a specific embodiment, the first magnetic field focusing structure 7 and the second magnetic field focusing structure 8 are respectively mounted on the first Hall chip 1 and the second Hall chip 2 through films with uniform thickness.

[0072] In this embodiment, the film with consistent thickness can be realized by a wafer bonding film (DAF film). The thickness of the DAF film between the first magnetic focusing structure 7 and the first Hall chip 1 is equal to the thickness of the DAF film between the second magnetic focusing structure 8 and the second Hall chip 2, thereby ensuring the high consistency of the magnetic focusing structure and the stability of the product. The DAF film can also help reduce the stress introduced into the chip during the curing and baking of the product after mounting, and reduce the influence of stress during the product plastic sealing.

[0073] It should be noted that the embodiment of the present application does not limit the preparation materials of the first magnetic concentrating structure 7 and the second magnetic concentrating structure 8, which may include but are not limited to: nanocrystalline, iron-nickel alloy and other magnetic concentrating materials.

[0074] The following is a description of the preparation process of the Hall integrated chip:

[0075] 1) First, use the mainstream Hall manufacturing process to produce closely adjacent Hall pairs and their anisotropically parallel dual Hall structures on a magnetic sensitive material wafer, and then bond the anisotropically parallel dual Hall structures to an insulating substrate.

[0076] 2) The magnetic concentrating structure is made into a square column with serrated edges and / or a trapezoidal column in side view by high-speed cutting. The angle of the cutting tool is selected according to the angle (0-10 degrees) of the vertical edge deviating from the vertical direction, and the cutting parameters are adjusted according to the 5μm-30μm serrated shape of the vertical edge after cutting. When the horizontal magnetic field passes through, it will be deflected into a vertical magnetic field through the magnetic concentrating structure, causing the chip to sense horizontal current. At the same time, due to the sawtooth structure design, the efficiency of the deflection part of the magnetic concentrating structure is improved, and the signal-to-noise ratio and product accuracy of the final current sensor are simultaneously improved.

[0077] 3) The cut magnetic concentrating structures are placed in designated areas on the first Hall chip 1 and the second Hall chip 2 .

[0078] In an optional embodiment, a third magnetic field focusing structure 12 is further provided at the bottom of the first Hall chip 1 and the second Hall chip 2;

[0079] There is a first overlapping part between the first projection of the third magnetic focusing structure 12 on the first Hall chip 1 and the second projection of the first magnetic focusing structure 7 on the first Hall chip 1; there is a second overlapping part between the third projection of the third magnetic focusing structure 12 on the second Hall chip 2 and the fourth projection of the second magnetic focusing structure 8 on the second Hall chip 2.

[0080] Figure 6 FIG. 1 is a side view of another magnetic focusing structure provided in an embodiment of the present application installed on a Hall chip, such as Figure 6As shown, the third magnetic concentrating structure 12 is a whole structure, which is arranged at the bottom of the first Hall chip 1 and the second Hall chip 2, and the thickness of the third magnetic concentrating structure 12 is relatively small. Exemplarily, the thickness of the third magnetic concentrating structure 12 is less than 60 μm, preferably, it can be about 50 μm.

[0081] Continue as Figure 6 As shown, the projection of the third magnetic focusing structure 12 on the Hall chip overlaps with the projections of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 on the Hall chip. Specifically, there is a first overlapping portion between the first projection of the third magnetic focusing structure 12 on the first Hall chip 1 and the second projection of the first magnetic focusing structure 7 on the first Hall chip 1; there is a second overlapping portion between the third projection of the third magnetic focusing structure 12 on the second Hall chip 2 and the fourth projection of the second magnetic focusing structure 8 on the second Hall chip 2 (the second overlapping portion is Figure 6 The part indicated by the arrow in the figure), through the design of this structure, the ability of the magnetic field deflection sheet can be enhanced, and its magnetic field focusing ability can be increased by more than 3 times.

[0082] It should be noted that the embodiment of the present application does not limit the length and width of the third magnetic focusing structure 12. In order to ensure that the projection of the third magnetic focusing structure 12 on the Hall chip overlaps with the projections of the first magnetic focusing structure 7 and the second magnetic focusing structure 8 on the Hall chip, and further enhance the ability of the magnetic focusing sheet to deflect the magnetic field, the length of the third magnetic focusing structure 12 in the horizontal direction can be set to be less than or equal to the distance between the extension of the first magnetic focusing structure 7 and the extension of the second magnetic focusing structure 8, so that the projection of the first magnetic focusing structure 7 and the projection of the second magnetic focusing structure 8 cover the edge of the third magnetic focusing structure 12.

[0083] In an optional embodiment, in order to further enhance the ability of the magnetic field deflection sheet to deflect the magnetic field, each projection can cover the Hall sensing area of ​​the corresponding Hall chip, more specifically, can cover the cross center area of ​​the corresponding Hall chip. Exemplarily, the first projection and the second projection both cover the Hall sensing area of ​​the first Hall chip 1, and the third projection and the fourth projection both cover the Hall sensing area of ​​the second Hall chip 2.

[0084] It should be noted that the embodiment of the present application does not limit the area of ​​the first overlapping part and the second overlapping part. In order to further enhance the ability of the magnetic field deflection sheet to ensure that the magnetic field focusing ability is increased by more than 3 times, the ratio of the area of ​​the first overlapping part to the area of ​​the first Hall chip can be set to a range of 1 / 5 to 1, and the ratio of the area of ​​the second overlapping part to the area of ​​the second Hall chip can be set to a range of 1 / 5 to 1.

[0085] In an optional embodiment, similar to the first magnetic focusing structure 7 and the second magnetic focusing structure 8, the third magnetic focusing structure 12 can also be mounted on the first Hall chip 1 and the bottom of the first Hall chip 1 through a wafer adhesive film, thereby ensuring the high consistency of the magnetic focusing structure and the stability of the product. The wafer adhesive film can also help reduce the stress introduced into the chip during curing and baking after the product is mounted, and reduce the impact of stress during product plastic sealing.

[0086] It should be noted that the embodiment of the present application does not limit the preparation material of the third magnetic concentrating structure 12, which may include but is not limited to: nanocrystals, or magnetic concentrating materials such as iron-nickel alloys.

[0087] The following is an explanation of the preparation process of the Hall integrated chip including the third magnetic focusing structure 12:

[0088] 1) First, use the mainstream Hall manufacturing process to produce closely adjacent Hall pairs and their anisotropically parallel dual Hall structures on a magnetic sensitive material wafer. Set the third magnetic concentrating structure 12 at the bottom of the cut dual Hall structure and bond it to the insulating substrate.

[0089] 2) The magnetic concentrator structure is made into a square column with serrated edges and / or a trapezoidal column in side view by high-speed cutting. The angle of the cutting tool is selected according to the angle (0-10 degrees) of the vertical edge deviating from the vertical direction, and the cutting parameters are adjusted according to the 5μm-30μm serrated vertical edge after cutting. When the horizontal magnetic field passes through, it will be deflected into a vertical magnetic field through the magnetic concentrator structure, causing the chip to sense horizontal current. At the same time, due to the sawtooth structure design, the efficiency of the deflection part of the magnetic concentrator structure is improved, and the signal-to-noise ratio and product accuracy of the final product are simultaneously improved.

[0090] 3) The cut magnetic concentrating structures are placed in designated areas on the first Hall chip 1 and the second Hall chip 2 .

[0091] The embodiment of the present application also provides a current sensor for horizontal direction detection, the current sensor comprising an insulating substrate, a lead frame and the above-mentioned Hall integrated chip;

[0092] The Hall integrated chip is bonded to the wire substrate of the insulating substrate;

[0093] The insulating substrate is arranged on the lead frame; the lead substrate of the insulating substrate mounts the Hall integrated chip and the lead frame through a patch process.

[0094] In this embodiment, the Hall integrated chip can be bonded to the wire substrate of the insulating substrate instead of being integrated into the processing circuit, and the Hall integrated chip and the wire frame containing the current row can be mounted on the wire substrate through the patch process. Specifically, two Hall chips can be interconnected on the wire substrate by using metal leads, or two Hall chips can be interconnected by using flip chip packaging (Flipchip) and other forms. The interface required for the original Hall output is reserved on the back-end signal processing circuit so that the output of the inverse parallel dual Hall structure can be introduced into the processing circuit.

[0095] Optionally, the conductor substrate of the insulating substrate is used to mount the Hall integrated chip and the conductor frame through a wafer adhesive film. The mounting directions of the two Hall chips are kept consistent. The wafer adhesive film needs to confirm the consistency of the film thickness so that the height of the two Hall chips remains consistent. The use of wafer adhesive film can also help reduce the stress introduced into the chip during curing and baking after the product is mounted.

[0096] Optionally, the packaging process of the current sensor can be as follows: the Hall integrated chip and the conductive frame containing the current row are mounted and placed together in a plastic encapsulation mold. The mold is filled with plastic encapsulation material, and the mold is closed to melt the plastic encapsulation material and then filled. In this high temperature environment, the wafer bonding film can more effectively reduce the impact of stress on the chip and ensure the consistency of the Hall chip. After the plastic encapsulation is completed, the product is placed in a rib cutting mold for molding and separation of the corresponding shape.

[0097] The current sensor for horizontal detection prepared in the embodiment of the present application has a horizontal magnetic field bias capability (gain) that is more than doubled compared to the traditional magnetic collector (IMC), reduces the hysteresis effect, and increases the magnetic field saturation point by more than 2 times. The increased gain allows the Hall sensing area to obtain more effective magnetic fields, reduces the interference of magnetic fields in other directions on the product, and improves the signal-to-noise ratio. In addition, the reduced hysteresis will enhance the signal linearity, and the improved performance of magnetic saturation will make the final sensor linear output range wider, increase the effective range, reduce signal errors, and improve the stability and accuracy of the final signal.

[0098] The following is an example of the beneficial effects of the current sensor prepared in the embodiment of the present application:

[0099] The current sensor comprises a first Hall chip 1, a second Hall chip 2, a first magnetic focusing structure 7 arranged on the first Hall chip 1, a second magnetic focusing structure 8 arranged on the second Hall chip 2, an insulating substrate and a lead frame containing a current row. Figure 7 It is a schematic diagram of magnetic field distribution in a simulation model provided in an embodiment of the present application. Figure 7 a in the figure refers to the magnetic field distribution diagram obtained by using the 30-micron thick magnetic concentrating layer of the existing IMC. Figure 7b in the figure refers to the magnetic field distribution diagram obtained by using a 100-micron-thick, non-serrated magnetic focusing sheet. Figure 7 c in the figure refers to the magnetic field distribution diagram obtained by using the sawtooth magnetic focusing structure in the embodiment of the present application, with the target side deviating from the vertical direction at an angle of 0 degrees. Figure 7 The direction of the dotted arrow in the figure refers to the direction of the current magnetic field.

[0100] like Figure 7 As shown in a, when a current of 20A is passed through the wire frame, the thickness of the conventional IMC is relatively small, and the signal obtained using the 30-micron-thick magnetic concentrating layer of the existing IMC is 2.65mv.

[0101] like Figure 7 As shown in b, the signal obtained using a 100-micron-thick, non-serrated magnetic focusing sheet is 3.67 mV, which is greater than the signal of the IMC thin layer.

[0102] like Figure 7 As shown in c in the figure, the signal obtained using the sawtooth magnetic focusing structure in the embodiment of the present application and the angle of the target edge deviating from the vertical direction is 0 degrees is 5.42mv.

[0103] It can be seen that the signal obtained using the sawtooth magnetic focusing structure in the embodiment of the present application is increased by 47% compared with the non-sawtooth magnetic focusing layer, and the signal gain is increased by more than 100% compared with the IMC thin layer.

[0104] The preparation and installation process of the above-mentioned Hall integrated chip are described below through different embodiments:

[0105] Embodiment 1:

[0106] The dual Hall chip (the first Hall chip 1 and the second Hall chip 2) is made of gallium arsenide material. The dual Hall chip is designed and manufactured separately, and the anisotropic parallel structure is made by metal sputtering to obtain the differential output result. The output polarity of the dual Hall chip is designed to be opposite, the power supply end is in series state to facilitate simultaneous power supply, and the output end is in parallel state, directly outputting the magnetic field sensing results of the dual Hall at the same time. In this design, if the vertical magnetic field interferes, since the dual Hall outputs are one positive and one negative, the vertical magnetic field will be directly shielded and no output will be generated. The final output calculation equation is Vh= (VHall1+VHall2) / 2. Based on this structure, when the vertical magnetic field interferes with the chip body, the output of the chip will be zero due to the anisotropic design, effectively avoiding the interference of the vertical magnetic field.

[0107] The dual Hall chip is bonded to the wire substrate of the insulating substrate instead of being integrated into the processing circuit. The DAF film is used on the wire substrate to mount the anisotropic parallel dual Hall and the back-end processing circuit. The mounting direction of the two Hall chips is kept consistent. The DAF film needs to confirm the consistency of the film thickness so that the height of the two Hall chips is consistent. The use of DAF film can also help reduce the stress introduced into the chip during curing and baking after the product is mounted. The two Hall chips are interconnected by using metal leads on the wire substrate (Flipchip and other forms can also be used here).

[0108] The interface originally required for the Hall output is reserved on the back-end signal processing circuit so that the output of the inverse parallel dual Hall structure can be introduced into the processing circuit.

[0109] The magnetic concentrating structure (i.e., the first magnetic concentrating structure 7 and the second magnetic concentrating structure 8) is prepared using magnetic concentrating materials such as nanocrystals or iron-nickel alloys. The magnetic concentrating structure is made into a square column with serrated edges and / or a trapezoidal column in side view by high-speed cutting. When the horizontal magnetic field passes through, it will be deflected into a vertical magnetic field through the magnetic concentrating structure, causing the chip to sense horizontal current. At the same time, due to the serrated structure design, the efficiency of the deflection part of the magnetic concentrating structure is improved, and the signal-to-noise ratio and product accuracy of the final product are simultaneously improved.

[0110] At the back end, the magnetic focusing structure is transposed 45° and mounted above the center of the Hall chip using a patch process (the first magnetic focusing structure 7 is mounted above the first Hall chip 1, and the second magnetic focusing structure 8 is mounted above the second Hall chip 2). The magnetic focusing structure needs to ensure that at least 1 / 4 of the area is pressed on a single Hall chip, and this 1 / 4 area needs to completely cover the Hall sensing area of ​​the single Hall chip. A layer of equal-height film is used as an adhesive part between the magnetic focusing structure and the corresponding Hall chip to ensure the high consistency of the first magnetic focusing structure 7 and the second magnetic focusing structure 8, as well as the stability of the product. This solution can simultaneously reduce the impact of stress during product plastic sealing. Benefiting from this magnetic focusing structure, the directions of the magnetic fields felt by the dual Hall chips connected in parallel in opposite directions are also different, and the final outputs are added. It is easier to eliminate the interference of stray magnetic fields and improve the signal-to-noise ratio. Afterwards, the electrodes and pads of the Hall chip are connected to the back-end circuit by metal bonding. This completes the production of the Hall integrated chip in this embodiment.

[0111] The process of packaging the current sensor using this Hall integrated chip is as follows: Place the Hall integrated chip and the lead frame containing the current row into the plastic encapsulation mold. Fill the mold with plastic encapsulation material, close the mold to melt the plastic encapsulation material and then fill it. In this high temperature environment, the DAF film can more effectively reduce the impact of stress on the upper Hall chip and ensure the consistency of the Hall chip. After the plastic encapsulation is completed, the product is put into the rib cutting mold for molding and separation of the corresponding shape.

[0112] Embodiment 2:

[0113] Different from Example 1, here, a thin (for example, about 50 microns thick) third magnetic focusing structure 12 is also mounted below the anisotropic parallel dual Hall structure, and connected in the form of a DAF film, so that the structure enhances the ability of the magnetic focusing sheet to deflect the magnetic field, and its magnetic focusing ability is increased by more than 3 times. The length of the third magnetic focusing structure 12 in the horizontal direction is less than or equal to the distance between the extension of the first magnetic focusing structure 7 and the extension of the second magnetic focusing structure 8, so that the projection of the first magnetic focusing structure 7 and the projection of the second magnetic focusing structure 8 cover the edge of the third magnetic focusing structure.

[0114] There is a first overlapping portion between a first projection of the third magnetic focusing structure on the first Hall chip and a second projection of the first magnetic focusing structure on the first Hall chip, and both the first projection and the second projection cover the center of the first Hall chip.

[0115] There is a second overlapping portion between a third projection of the third magnetic focusing structure on the second Hall chip and a fourth projection of the second magnetic focusing structure on the second Hall chip, and both the third projection and the fourth projection cover the center of the second Hall chip.

[0116] Then, the same manufacturing process as in Example 1 is implemented, specifically:

[0117] The dual Hall chip (the first Hall chip 1 and the second Hall chip 2) is made of gallium arsenide material. The dual Hall chip is designed and manufactured separately, and the anisotropic parallel structure is made by metal sputtering to obtain the differential output result. The output polarity of the dual Hall chip is designed to be opposite, the power supply end is in series state to facilitate simultaneous power supply, and the output end is in parallel state, directly outputting the magnetic field sensing results of the dual Hall at the same time. In this design, if the vertical magnetic field interferes, since the dual Hall outputs are one positive and one negative, the vertical magnetic field will be directly shielded and no output will be generated. The final output calculation equation is Vh= (VHall1+VHall2) / 2. Based on this structure, when the vertical magnetic field interferes with the chip body, the output of the chip will be zero due to the anisotropic design, effectively avoiding the interference of the vertical magnetic field.

[0118] The dual Hall chip is bonded to the wire substrate of the insulating substrate instead of being integrated into the processing circuit. The DAF film is used on the wire substrate to mount the anisotropic parallel dual Hall and the back-end processing circuit. The mounting direction of the two Hall chips is kept consistent. The DAF film needs to confirm the consistency of the film thickness so that the height of the two Hall chips is consistent. The use of DAF film can also help reduce the stress introduced into the chip during curing and baking after the product is mounted. The two Hall chips are interconnected by using metal leads on the wire substrate (Flipchip and other forms can also be used here).

[0119] The interface originally required for the Hall output is reserved on the back-end signal processing circuit so that the output of the inverse parallel dual Hall structure can be introduced into the processing circuit.

[0120] The magnetic concentrating structure (i.e., the first magnetic concentrating structure 7 and the second magnetic concentrating structure 8) is prepared using magnetic concentrating materials such as nanocrystals or iron-nickel alloys. The magnetic concentrating structure is made into a square column with serrated edges and / or a trapezoidal column in side view by high-speed cutting. When the horizontal magnetic field passes through, it will be deflected into a vertical magnetic field through the magnetic concentrating structure, causing the chip to sense horizontal current. At the same time, due to the serrated structure design, the efficiency of the deflection part of the magnetic concentrating structure is improved, and the signal-to-noise ratio and product accuracy of the final product are simultaneously improved.

[0121] At the back end, the magnetic focusing structure is transposed 45° and mounted above the center of the Hall chip using a patch process (the first magnetic focusing structure 7 is mounted above the first Hall chip 1, and the second magnetic focusing structure 8 is mounted above the second Hall chip 2). The magnetic focusing structure needs to ensure that at least 1 / 4 of the area is pressed on a single Hall chip, and this 1 / 4 area needs to completely cover the Hall sensing area of ​​the single Hall chip. A layer of equal-height film is used as an adhesive part between the magnetic focusing structure and the corresponding Hall chip to ensure the high consistency of the first magnetic focusing structure 7 and the second magnetic focusing structure 8, as well as the stability of the product. This solution can simultaneously reduce the impact of stress during product plastic sealing. Benefiting from this magnetic focusing structure, the directions of the magnetic fields felt by the dual Hall chips connected in parallel in opposite directions are also different, and the final outputs are added. It is easier to eliminate the interference of stray magnetic fields and improve the signal-to-noise ratio. Afterwards, the electrodes and pads of the Hall chip are connected to the back-end circuit by metal bonding. This completes the production of the Hall integrated chip in this embodiment.

[0122] The process of packaging the current sensor using this Hall integrated chip is as follows: Place the Hall integrated chip and the lead frame containing the current row into the plastic packaging mold. Fill the mold with plastic packaging material, close the mold to melt the plastic packaging material and then fill it. In this high temperature environment, the DAF film can more effectively reduce the impact of stress on the upper Hall chip and ensure the consistency of the Hall chip. After the plastic packaging is completed, the product is put into the rib cutting mold for molding and separation of the corresponding shape.

[0123] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0124] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A Hall integrated chip for horizontal direction detection, comprising a first Hall chip and a second Hall chip, wherein the first Hall chip and the second Hall chip are arranged adjacent to each other, an output end of the first Hall chip and an output end of the second Hall chip are connected in parallel, and the positive and negative potentials generated by the first Hall chip and the second Hall chip under the interference of a vertical magnetic field cancel each other out, characterized in that: A first magnetic focusing structure is arranged on the first Hall chip, and a second magnetic focusing structure is arranged on the second Hall chip. The target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction are both serrated. The target edges of the first magnetic focusing structure and the second magnetic focusing structure in the vertical direction have an angle of deviation from the vertical direction of 0 degrees to 10 degrees.

2. The Hall integrated chip according to claim 1, characterized in that: The jagged target edge includes grooves, concave points and convex points, the angle at the concave points is 20 degrees to 120 degrees, the size of the convex points in the vertical direction is 0 μm to 20 μm, and the size of the grooves in the vertical direction is 5 μm to 30 μm.

3. The Hall integrated chip according to claim 1, characterized in that: The thickness of the first magnetic field focusing structure and the thickness of the second magnetic field focusing structure are both greater than or equal to 60 μm.

4. The Hall integrated chip according to claim 1, characterized in that: The first magnetic field focusing structure and the second magnetic field focusing structure are both in the shape of square columns, or the first magnetic field focusing structure and the second magnetic field focusing structure are both in the shape of columns with a trapezoidal side view.

5. The Hall integrated chip according to claim 1, characterized in that: A partial area of ​​the first magnetic focusing structure is arranged on the first Hall chip and covers the Hall sensing area of ​​the first Hall chip, and a ratio of an area of ​​the partial area on the first Hall chip covered by the first magnetic focusing structure to an area of ​​the first magnetic focusing structure is greater than or equal to 1 / 4; A partial area of ​​the second magnetic concentrating structure is arranged on the second Hall chip and covers the Hall sensing area of ​​the second Hall chip. The ratio of the area of ​​the partial area covered by the second magnetic concentrating structure on the second Hall chip to the area of ​​the second magnetic concentrating structure is greater than or equal to 1 / 4.

6. The Hall integrated chip according to claim 5, characterized in that: The bottoms of the first magnetic focusing structure and the second magnetic focusing structure are both rectangular, a vertex of the bottom of the first magnetic focusing structure is located on the first Hall chip, and a vertex of the bottom of the second magnetic focusing structure is located on the second Hall chip; A top angle of the bottom of the first magnetic focusing structure is arranged opposite to a top angle of the bottom of the second magnetic focusing structure; or, an edge of the bottom of the first magnetic focusing structure is in the same straight line with the center line of the first Hall chip in the horizontal direction, and an edge of the bottom of the second magnetic focusing structure is in the same straight line with the center line of the second Hall chip in the horizontal direction.

7. The Hall integrated chip according to claim 1, characterized in that: The first magnetic field focusing structure is mounted on the first Hall chip by glue, and the second magnetic field focusing structure is mounted on the second Hall chip by glue.

8. The Hall integrated chip according to claim 1, characterized in that: The first magnetic field focusing structure and the second magnetic field focusing structure are respectively mounted on the first Hall chip and the second Hall chip through films with the same thickness.

9. The Hall integrated chip according to any one of claims 1 to 8, characterized in that: A third magnetic field focusing structure is also provided at the bottom of the first Hall chip and the second Hall chip; There is a first overlapping part between the first projection of the third magnetic focusing structure on the first Hall chip and the second projection of the first magnetic focusing structure on the first Hall chip; there is a second overlapping part between the third projection of the third magnetic focusing structure on the second Hall chip and the fourth projection of the second magnetic focusing structure on the second Hall chip.

10. The Hall integrated chip according to claim 9, characterized in that: The first projection and the second projection both cover the Hall sensing area of ​​the first Hall chip, and the third projection and the fourth projection both cover the Hall sensing area of ​​the second Hall chip; The ratio of the area of ​​the first overlapping portion to the area of ​​the first Hall chip is in the range of 1 / 5 to 1, and the ratio of the area of ​​the second overlapping portion to the area of ​​the second Hall chip is in the range of 1 / 5 to 1.

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