Memory with dual column redundancy

Abstract

The memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns among the plurality of column groups, the plurality of column groups may be divided into a non-shift region, a single shift region, and a double shift region. The memory includes a plurality of input / output circuits corresponding to the plurality of column groups. Each input / output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input / output circuit also includes a switch matrix. In the non-shift region, the switch matrix couples the input / output circuit to a core in a corresponding column group. In the single shift region, the switch matrix couples the input / output circuit to a core in a subsequent column group. In the dual shift region, the switch matrix couples the input / output circuit to a core in a next column group.

Description

Technical Field

[0001] The present application relates to memory, and more particularly to a memory bank in which a pair of defective ranks can be replaced with two redundant ranks. Background Art

[0002] Static random access memory (SRAM) includes an array of bit cells arranged in rows and columns. To enhance performance, for example by reducing bit line capacitance, the bit cell array is typically subdivided into banks. Without redundancy, a single error to a bank can render the entire bank inoperable. Therefore, each bank typically has redundant columns so that the bank can replace defective columns with redundant columns.

[0003] There are two main ways to implement column redundancy: input / output (I / O) shifting and sense amplifier shifting. I / O shifting is simpler to implement than sense amplifier shifting, but requires more semiconductor die space. In both types of column redundancy, each memory bank can replace defective columns by using redundant columns. Thus, a memory bank can replace a single defective column with a redundant column. However, defects in two columns in a single memory bank can render the memory bank non-functional. Summary of the invention

[0004] According to one aspect of the present disclosure, a memory is provided, comprising: a plurality of column groups, each of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group, a second column group adjacent to the first column group, and a third column group adjacent to the second column group; and a first switch matrix, the first switch matrix being configured to couple a latch to one of the first column group, the second column group, and the third column group in response to a plurality of column redundancy signals.

[0005] According to another aspect of the present disclosure, a memory is provided, comprising: a plurality of column groups, each of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group and a second column group adjacent to the first column group; a first latch; a second latch; a first switch matrix, the first switch matrix comprising: a first switch coupled between the first column group and a first center node, a second switch coupled between the first center node and the second column group, a third switch coupled between the first latch and the first center node, and a fourth switch coupled between the first center node and the second latch.

[0006] According to another aspect of the present disclosure, a memory is provided, comprising: a plurality of column groups, each of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group and a second column group; a first latch; a second latch; a first switch matrix, the first switch matrix coupled to the first column group, the second column group, the first latch and the second latch; a first redundant column group, the first redundant column group comprising a first plurality of multiplexed redundant columns; and a second redundant column group, the second redundant column group comprising a second plurality of multiplexed redundant columns.

[0007] According to another aspect of the present invention, a method for memory redundancy is provided, comprising: coupling a first latch to a first column group among the plurality of column groups in response to a subset of the plurality of column groups extending from an initial column group to a first column group without a defective column group; coupling the first latch to a second column group among the plurality of column groups in response to the first column group being a first defective column group among the plurality of column groups, wherein the second column group is adjacent to the first column group; and coupling the first latch to a third column group among the plurality of column groups in response to the second column group being a second defective column group among the plurality of column groups, wherein the third column group is adjacent to the second column group.

[0008] These and additional advantages may be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A memory bank with dual redundant shifting according to an aspect of the present disclosure is illustrated.

[0010] Figure 2 An example of a system including a local data path and an I / O circuit according to an aspect of the present disclosure is shown. Figure 1 part of a memory bank.

[0011] Figure 3 A portion of a dual-redundant shift bank including a switch matrix and a corresponding decoder according to an aspect of the present disclosure is illustrated.

[0012] Figure 4A is a truth table implemented by a decoder according to an aspect of the present disclosure.

[0013] Figure 4B is a circuit diagram of a decoder for a dual redundant shift bank according to an aspect of the present disclosure.

[0014] Figure 5 A write path portion of a dual redundant shift bank according to an aspect of the present disclosure is illustrated.

[0015] Figure 6 A read path portion of a dual redundant shift bank according to an aspect of the present disclosure is illustrated.

[0016] Figure 7 is a flow chart of a dual-redundancy shift method for a memory bank according to one aspect of the present disclosure.

[0017] Figure 8 Some example electronic systems incorporating dual redundant shift memories according to an aspect of the present disclosure are illustrated.

[0018] Specific implementations of the present disclosure and its advantages may be best understood by referring to the following detailed description.It should be understood that like reference numerals are used to identify like elements illustrated in one or more of the figures in the drawings. DETAILED DESCRIPTION

[0019] An I / O shift redundancy scheme is provided that can replace two defective column groups in a single memory. In order to provide such advantageous dual redundancy, a memory including a plurality of column groups and a pair of redundant column groups is disclosed. In order to better understand these innovative features, some terms will first be reviewed. In an SRAM memory body, each bit cell stores a bit signal and the complement of the bit signal. In order to access these complementary signals, the bit cell is coupled to a pair of bit lines. The SRAM memory body includes a plurality of such bit line pairs, each bit line pair being coupled to a single column of bit cells arranged in a single column in several rows according to corresponding word lines. During a write operation, an input latch in an input / output circuit (also referred to herein as an I / O circuit) is coupled to a selected bit cell through a corresponding bit line pair. Similarly, during a read operation, an output latch in an input / output circuit is coupled to a selected bit cell through a corresponding bit line pair.

[0020] This coupling between the bit line pairs (and corresponding bit cells) and the input / output circuits can be multiplexed so that the input / output circuits can be coupled to one of the multiple columns that are multiplexed. For example, in a "MUX2" implementation, the bit line pairs can be organized into odd and even pairs. Depending on the multiplexing, the input / output circuits can then be coupled to selected bit line pairs from the corresponding odd and even pairs. In a write operation, the input / output circuits can then be coupled to the selected bit line pairs through a write driver and a write multiplexer. Similarly, during a read operation, the input / output circuits can be coupled to the selected bit line pairs through a read multiplexer and a sense amplifier. Other types of multiplexing of bit line pairs can be used, such as in a "MUX4" implementation, where each input / output circuit can be coupled to one of four multiplexed columns.

[0021] With respect to column multiplexing, the combination of a write driver, a write multiplexer, a read multiplexer, and a sense amplifier may be denoted herein as a "local data path". The combination of a local data path and a corresponding multiplexed column is denoted herein as a "column group" to emphasize the bit line multiplexing aspect. Each multiplexed column contains a bit line pair and a plurality of bit cells.

[0022] The following discussion will be directed to a specific implementation in which the I / O circuit is a global I / O circuit, but it will be appreciated that the I / O shifting disclosed herein is applicable to specific implementations in which the I / O circuit is a local I / O circuit. The term "global" I / O circuit is used because a global I / O circuit can be shared between two memory banks, while a local I / O circuit belongs to only one memory bank. In the following discussion, for simplicity, each global I / O circuit will be referred to simply as an "I / O circuit."

[0023] In order to address the possibility of two defective column groups in a single memory bank, a memory bank including two redundant column groups is disclosed. If there is no defective column group in the memory bank, the switch matrix in each I / O circuit is configured to couple the latch in the I / O circuit to the corresponding default column group. During a read operation, the output latch in the I / O circuit then receives the retrieved data bit from the default column group. Similarly, the input latch in the I / O circuit provides the data bit to be written to the default column group during a write operation. If the memory bank includes a single defective column group, one or more of the I / O circuits can be alternatively coupled to adjacent column groups. For example, assume that there are N column groups arranged from the (N-1)th column group to the zeroth column group in the memory bank, where N is a positive integer. Then there will be N I / O circuits: the (N-1)th I / O circuit corresponding to the (N-1)th column group, the (N-2)th I / O circuit corresponding to the (N-2)th column group, and so on, to the zeroth I / O circuit corresponding to the zeroth column group. In the absence of any errors, each I / O circuit is coupled to a corresponding column group. However, it is assumed that the i-th column group is the first defective column group in the memory body, where i is an integer less than N. From the N-th column group to the (i+1)-th column group, each I / O circuit continues to be coupled to its default column group, as previously discussed. From the i-th column group to the zeroth column group, each global I / O circuit is alternatively coupled to a column group adjacent or neighboring the default column group. For example, the i-th global I / O circuit is coupled to the (i-1)-th column group, the (i-1)-th I / O circuit is coupled to the (i-2)-th column group, and so on, so that the zeroth I / O circuit is coupled to the first redundant column group. In the case of such a single defective column group, the array of column groups can thereby be divided into a non-shifted region in which each I / O circuit is coupled to a default column group and a single shifted region in which each I / O circuit is coupled to a column group continuous or adjacent to the default column group.

[0024] If there are two defective column groups in a single memory body, the plurality of column groups may be alternatively divided into a non-shift region, a single-shift region, and a double-shift region. The non-shift region and the single-shift region are as described above, and are divided by the initial defective column group. The previous column group of the second defective column group is the initial column group in the double-shift region. Each I / O circuit in the double-shift region is coupled to the next adjacent column group of the default column group of the I / O circuit. For example, assume that the initial defective column group is the i-th column group as described above. The second defective column group may then be designated as the j-th column group, where j is an integer less than i and greater than or equal to zero. The (j+1)-th column group will then separate the single-shift region from the double-shift region. In this case, the (j+1)th I / O circuit would be coupled to the (j-1)th column group, the jth I / O circuit would be coupled to the (j-2)th column group, and so on, such that the first I / O circuit would be coupled to the first redundant column group and the zeroth I / O circuit would be coupled to the second redundant column group.

[0025] In a given memory bank, if there is no defective column group, the entire plurality of column groups form a no-shift region. In this case, there is neither a single-shift region nor a double-shift region. If there is only one defective column group, the plurality of column groups are divided into no-shift regions and single-shift regions, and there is no double-shift region. If there are two (non-contiguous) defective column groups, the plurality of column groups are divided into no-shift regions, single-shift regions, and double-shift regions. A memory with two consecutive defective column groups can be divided into no-shift regions and double-shift regions (no single-shift region).

[0026] To identify defective column groups, the memory can be tested, for example, at the time of manufacturing. The memory can be an embedded memory in a system such as a system on a chip (SoC). The address of the defective column group can then be stored in a read-only memory (e.g., a fuse array) in the SoC. During normal operation of the SoC, a column group among a plurality of column groups in the memory is addressed for a read or write operation. There are then three possibilities: 1) the addressed column group is in a non-shift region, 2) the addressed column group is in a single shift region, and 3) the addressed column group is a double shift region. In order to determine which of the three possibilities exists for the addressed column group, each I / O circuit includes a redundant decoder. For simplicity, each redundant decoder will be simply referred to as a decoder in the following discussion.

[0027] exist Figure 1An example memory bank 100 having such advantageous dual redundancy is shown in FIG. The memory bank 100 includes sixteen column groups arranged from the fifteenth column group to the zeroth column group. Each column group includes a core, which includes a bit line pair and a bit cell (not shown). Since there are sixteen column groups, there are also sixteen I / O circuits arranged from the fifteenth I / O circuit 125 to the zeroth I / O circuit 126. In a non-shifted state, the sixteen I / O circuits are coupled to a default column group of the sixteen column groups on a one-to-one basis. For example, the fifteenth I / O circuit 125 is coupled to the fifteenth column group, and the zeroth I / O circuit 126 is coupled to the zeroth column group. Each I / O circuit is coupled to the core of the column group through a local data path (LDP). For example, the fifteenth I / O circuit 125 can be coupled to the core 120 through the LDP 130 of the fifteenth column group. The local data path of each column group may include a write multiplexer and a read multiplexer (not shown), as will be further explained herein.

[0028] In memory bank 100, the 11th column group has a first defect 135. Therefore, the 11th column group is the first defective column group in memory bank 100. As will be further explained herein, each I / O circuit from the 11th column group to the zeroth column group will therefore be in a single shift region 110 or a double shift region 115. The 15th column group to the 12th column group are in the no shift region 105. If the 11th column group is the only defective column group in memory bank 100, the single shift region 110 will extend from the 11th column group to the zeroth column group. However, memory bank 100 has a second defect 140 in the 7th column. Therefore, the 7th column group is the second defective column group in memory bank 100. The single shift region 110 therefore ends at the 9th column group. The double shift region 115 extends from the 8th column group to the zeroth column group.

[0029] In the no-shift region 105, each I / O circuit is coupled to a local data path and a core in the default rank group of the I / O circuit. For example, the fifteenth I / O circuit 125 is thus coupled to the core 120 of the 15th rank group through the local data path 130 in the 15th rank group. The coupling of each I / O circuit is represented by arrow 140. As the name "single-shift" implies, each I / O circuit in the single-shift region 110 is not coupled to its default rank group, but is coupled to its default rank group through a local data path in an adjacent rank group. For example, the 11th I / O circuit 150 is coupled to the core 160 of the 10th rank group through a local data path 155 in the 10th rank group. Similarly, each I / O circuit in the double-shift region 115 is coupled to the default rank group of the I / O circuit through a local data path in the next adjacent rank group. For example, the seventh I / O circuit 165 in the double-shift region 115 is coupled to the local data path 170 in the 5th rank group to the core 175 of the 5th rank group.

[0030] Due to the double shift in the double shift region 115, the I / O circuit 180 in the 1st rank group is coupled to the core 190 in the first redundant rank group through the local data path 185 in the first redundant rank group (the 1st redundant rank). Similarly, the zeroth I / O circuit 126 is coupled to the core 193 in the second redundant rank group through the local data path 192 in the second redundant rank group (the 2nd redundant rank).

[0031] To achieve no-shift, single-shift, and double-shift behavior, each I / O circuit includes a switch matrix ( Figure 1 Specifically, each switch matrix is ​​controlled by a corresponding redundant shift signal and a dual redundant shift signal. For the sake of clarity, Figure 1 1 shows a single redundant shift (red_shift) signal 151, but in reality there will be sixteen different redundant shift signals, one for each I / O circuit. Similarly, for clarity of illustration, Figure 1 1 shows a single dual redundant shift (dual red_shift) signal 152, but in reality there will be sixteen different dual redundant shift signals, one for each I / O circuit. Each I / O circuit thus receives a corresponding redundant shift signal 151 and a dual redundant shift signal 152. For additional clarity of illustration, Figure 1 105. In the example, only the I / O circuits for which the redundant shift signal 151 is true are shown to receive the redundant shift signal 151. Thus, only the I / O circuits in the single shift region 110 and the double shift region 115 are shown to receive the redundant shift signal 151. The redundant shift signal 151 is false for each I / O circuit without a shift region 105. For additional clarity of illustration, Figure 1 1 shows the I / O circuits receiving the dual redundant shift signal 152 only for the I / O circuits for which the dual redundant shift signal 152 is true. The dual redundant shift signal 152 is true for each I / O circuit in the dual shift region 115 except for the initial rank group in the dual shift region 115 (which is the 8th rank group in the memory bank 100) and is false for each I / O circuit in the no shift region 105 and in the single shift region 110.

[0032] The I / O circuit arrangement of the I / O circuits from the 15th I / O circuit 125 to the zeroth I / O circuit 126 provides the basis for what are herein referred to as the “previous” I / O circuit and the “subsequent” I / O circuit. Except for the 15th I / O circuit 125, each I / O circuit has a previous I / O circuit in the I / O circuit arrangement. For example, the 12th I / O circuit 149 is the previous I / O circuit of the 11th I / O circuit 150. More generally, the i-th I / O circuit is the previous I / O circuit of the (i-1)th I / O circuit, where i is a positive integer. Except for the zeroth I / O circuit 126, each I / O circuit has a subsequent I / O circuit in the I / O circuit arrangement. For example, the 11th I / O circuit 150 is the subsequent I / O circuit of the 12th I / O circuit 149. More generally, the (i-1)th I / O circuit is the subsequent I / O circuit of the i-th I / O circuit, where i is also a positive integer. Note that this arrangement is arbitrary and may be reversed in an alternative implementation where the two redundant column groups would be adjacent to the 15th column group instead of adjacent to the zeroth column group. In this alternative implementation, the zeroth column would be the initial column and the 15th column would be the final column.

[0033] This definition of previous and subsequent I / O circuits, in turn, provides the basis for the definitions denoted herein as "feedback" and "feedforward" signals. A feedback signal propagates from a given I / O circuit to a previous I / O circuit. Conversely, a feedforward signal propagates from a given I / O circuit to a subsequent I / O circuit.

[0034] As previously described, the term "column group" includes the local data paths and the associated core of multiplexed bit line pairs and bit cells. For example, in a "MUX 2" implementation of the memory array 100, each of the column groups includes both even bit line pairs and odd bit line pairs. Depending on the column addressing, in such an implementation, each I / O circuit is then coupled to either an even bit line pair or an odd bit line pair. More generally, each column group may include a plurality of multiplexed bit line pairs depending on the size or magnitude of the column multiplexing. Figure 22 shows a portion 200 of a specific implementation of MUX 2 of the memory body 100. For clarity of illustration, portion 200 only includes the first column group (column 1), the zeroth column group (column 0), the first redundant column group (first redundant column), and the second redundant column group (second redundant column). I / O circuit 180 is the default I / O circuit for the first column group. Similarly, the zeroth I / O circuit 126 is the default I / O circuit for the zeroth column group. Each of the first column group, the zeroth column group, the first redundant column group, and the second redundant column group includes both an even bit line pair and an odd bit line pair. Each even bit line pair and odd bit line pair is formed by a bit line bl and a complementary bit line blb. Each bit line pair is coupled to a plurality of bit cells arranged in a row. For clarity of illustration, only one bit cell is shown for each bit line pair. For example, the even bit line pair in the first column group is coupled to bit cell 215. The bit line pairs and bit cells of each column group form the core 120 of the column group ( Figure 1 ). For clarity of illustration, the local data paths in each column group are represented only by a write multiplexer and a write driver (WD), but it will be appreciated that the corresponding read multiplexers and sense amplifiers will also be included in this MUX 2 implementation. Thus, the first column group includes a write driver 210-1 and a write multiplexer 205-1, the zeroth column group includes a write driver 210-2 and a write multiplexer 205-2, the first redundant column group includes a write driver 210-3 and a write multiplexer 205-3, and the second redundant column group includes a write driver 210-4 and a write multiplexer 205-4. Depending on the data input signal during a write operation, each write driver controls the binary state (true or false) of the write driver (wd) signal and the complementary write driver (wdb) signal to the corresponding write multiplexer. Depending on whether an even bit line pair or an odd bit line pair is selected, each write multiplexer then drives the appropriate bit line pair accordingly.

[0035] If there are no errors in such a specific implementation, the first column group and the second column group will be in the no-shift region. In this case, the I / O circuit 180 responds to its data input signal during a write operation to couple to the write driver 210-1 in the first column group accordingly. Similarly, in this no-shift condition, the zeroth I / O circuit 126 will respond to its data input signal during a write operation to couple to the write driver 210-2 in the zeroth column group. Neither the first redundant column group nor the second redundant column group is used in this case.

[0036] If the first and zeroth column groups are included in the single shift region, the first I / O circuit 180 is coupled to the write driver 210-2 in the zeroth column group during a write operation addressing the first column group. Similarly, the zeroth I / O circuit 126 is coupled to the write driver 210-3 in the first redundant column group under this single shift condition during a write operation to the zeroth column group. Each I / O circuit includes a decoder that controls whether the I / O circuit is shifted. For illustration purposes, in Figure 2 2. Each decoder is shown separately from its I / O circuit in FIG. 2. For example, decoder 220 controls the shift of the first I / O circuit 180. Similarly, decoder 225 controls the shift of the zeroth I / O circuit 126.

[0037] If the first and zeroth column groups are included in the double shift region, during a write operation to the first column group, the data input signal from the first I / O circuit 180 is coupled to the write driver 210-3 in the first redundant column group. Similarly, during a write operation to the zeroth column group, the data input signal from the zeroth I / O circuit 126 is coupled to the write driver 210-4 in the second redundant column group. An example switch matrix for each I / O circuit will now be discussed.

[0038] Example Switch Matrix

[0039] In order to perform selection between no shifting, single redundant shifting and dual redundant shifting within each I / O circuit, each I / O circuit includes a switch matrix. As used herein, a "switch matrix" is considered to include a plurality of switches. Figure 3 , an example portion 300 of a memory bank is shown, which includes an i-th column group 301, an (i-1)th column group 303, and an (i-2)th column group 304, where i is a positive integer. In the default state (no column group error and therefore no shift), the i-th switch matrix 305 couples the i-th I / O (io) signal to the core (not shown) in the i-th column group 301. Similarly, in the absence of any error, the (i-1)th switch matrix 310 couples the (i-1)th io signal to the (i-1)th column group 303. Each switch matrix is ​​controlled by a corresponding decoder. For example, the i-th decoder 315 controls the i-th switch matrix 305. Similarly, the (i-1)th decoder 320 controls the (i-1)th switch matrix 310. Each decoder and switch matrix combination is part of a corresponding I / O circuit (not shown). The i-th I / O circuit therefore includes the i-th switch matrix 305 and the i-th decoder 315. Similarly, the (i-1)th I / O circuit includes an (i-1)th switch matrix 310 and an (i-1)th decoder 320 .

[0040] Referring again to the memory bank 100, it will be appreciated that the redundant shift signal 151 and the dual redundant shift signal 152 are shown in a simplified form, where each I / O circuit is controlled by a separate redundant shift signal and a separate dual redundant shift signal. If there are N column groups (N is a complex positive integer), then there are N redundant shift signals and N dual redundant shift signals. In the portion 300, the i-th redundant shift signal controls the switching of the switch 1B in the i-th switch matrix 305, and the i-th dual redundant shift signal controls the switch 2A in the i-th switch matrix 305. The (i-1)th redundant shift signal controls the switching of the analog switch 1B in the (i-1)th switch matrix 310, and the (i-1)th dual redundant shift signal controls the switch 2A in the (i-1)th switch matrix 310.

[0041] The switch 1B in the i-th switch matrix 305 is coupled to the switch 1A in the (i-1)th switch matrix 310. Similarly, the switch 1B in the (i-1)th switch matrix 310 is coupled to the switch 1A in the (i-2)th switch matrix (not shown). The coupling between the switch 1B and the switch 1A in the consecutive switch matrix can be regarded as a 1-level coupling. In addition, the switch 2B in the i-th switch matrix 305 is coupled to the switch 2A in the (i-1)th switch matrix 310. Similarly, the switch 2B in the (i-1)th switch matrix 310 is coupled to the switch 2A (not shown) in the (i-2)th switch matrix. The coupling between the switch 2B and the switch 2A in the consecutive switch matrix can be regarded as a 2-level coupling. Each switch 2B is controlled by a dual redundant shift cutoff signal, as will be further described herein. For example, the i-th dual redundant shift cutoff signal controls the switch 2B in the i-th switch matrix 305. Similarly, the (i-1)th dual redundant shift cutoff signal controls the switch 2B in the (i-1)th switch matrix 310 .

[0042] In each switch matrix, switch 1B is configured to be closed when the corresponding redundant shift signal is true. For example, switch 1B in the i-th switch matrix 305 is configured to be closed when the i-th redundant shift signal is true. In contrast, each switch 1A is configured to be closed when the complement of the corresponding redundant shift signal is true. For example, inverter 325 inverts the i-th redundant shift signal to control the switching of switch 1A in the i-th switch matrix 305. In the same manner, inverter 330 inverts the (i-1)th redundant shift signal to control the switching of switch 1A in the (i-1)th switch matrix 310. In each switch matrix, switches 1A, 1B, 2A and 2B are coupled to each other through a central node. For example, the central node 306 in the i-th switch matrix 305 couples its switches 1A, 1B, 2A and 2B together. Similarly, the central node 307 in the (i-1)th switch matrix 310 couples its switches 1A, 1B, 2A and 2B together.

[0043] In each switch matrix, switch 2A is configured to be closed when the corresponding dual redundant shift signal is true. For example, when the (i-1)th dual redundant shift signal is true, switch 2A in the (i-1)th switch matrix 310 is closed. Similarly, when the i-th dual redundant shift signal is true, switch 2A in the i-th switch matrix 305 is closed. Each switch 2B is configured to be closed when the complement of the corresponding dual redundant shift cut-off signal is true. For example, when the i-th dual redundant shift cut-off signal is false, switch 2B in the i-th switch matrix 305 is closed. Conversely, when the i-th dual redundant shift cut-off signal is true, switch 2B in the i-th switch matrix 305 is open.

[0044] Each decoder is configured to generate a corresponding binary cut-off signal, as will be further explained herein. In order to control the corresponding shift matrix, each decoder feeds forward its redundant shift signal and its dual redundant shift signal to the decoder in the subsequent I / O circuit. For example, the i-th decoder 315 feeds forward the i-th redundant shift signal and the i-th dual redundant shift signal to the (i-1)th decoder 320. Similarly, each decoder feeds back its cut-off signal to the decoder in the previous I / O circuit. For example, the (i-1)th decoder 315 feeds back its (i-1)th cut-off signal to the i-th decoder 315.

[0045] Therefore, each decoder can receive a cut-off signal from a decoder of a subsequent I / O circuit, and receive a redundant shift signal and a dual redundant shift signal from a decoder of a previous I / O circuit. Based on these signals and its own cut-off signal, the decoder then generates its redundant shift signal, its dual redundant shift signal, and its dual redundant shift cut-off signal to control the corresponding switch matrix. For example, the i-th decoder 315 receives the (i+1)th redundant shift signal and the (i+1)th dual redundant shift signal from a decoder (not shown) of the (i+1)th I / O circuit. In addition, the i-th decoder 315 receives the (i-1)th cut-off signal from the (i-1)th decoder 320. Based on these signals and the i-th cut-off signal, the i-th decoder 315 can generate the i-th redundant shift signal, the i-th dual redundant shift signal, and the i-th dual redundant shift cut-off signal.

[0046] As will be further explained herein, each decoder may be configured with decoder logic to control the generation of its redundant shift signal, its dual redundant shift signal, and its dual redundant shift cut signal. Figure 4A4 shows an example truth table 400 of the decoder logic in the i-th decoder 315. It should be understood that similar logic applies to the remaining decoders, such as the (i-1)-th decoder 320. If the i-th column group 301 is in the non-shift region 105 of the memory bank 100, the non-shift mode in the truth table 400 is valid. In this non-shift mode, the i-th cut signal, the (i+1)-th redundant shift signal, the (i+1)-th dual redundant shift signal, and the (i-1)-th cut signal are all false (having a binary zero state). The decoder logic then responds in this non-shift mode so that the i-th redundant shift signal, the i-th dual redundant shift signal, and the i-th dual redundant shift cut signal are all false. In the non-shift mode, switch 1a is turned on, switch 1b is turned off, switch 2a is turned off, and switch 2b is turned on. Therefore, the i-th IO signal will be propagated to the i-th column group 301 through the switch matrix 305.

[0047] Conversely, if the i-th column group 301 is in the single shift region 110, the single shift mode in the truth table 400 is valid. In the single shift mode, there are two possibilities, depending on whether the i-th column group 301 is the initial defective column group in the single shift region 110 or whether the i-th column group 301 is after the initial defective column group. An example of an initial defective column group is the 11th column group in the memory bank 100. An example of a column group after this initial defective column group in the single shift region 110 in the memory bank 100 would be the 10th column group or the 9th column group. In both possibilities, the decoder logic responds to set the i-th redundant shift signal to true and to set both the i-th dual redundant shift signal and the i-th dual redundant shift cut signal to false. The i-th decoder 315 is then controlled so that its switch 1b is on, its switch 2a is off, and its switch 2b is on.

[0048] If the i-th column group 301 is the initial defective column group in the single shift region 110, the single shift mode of the decoder logic in the i-th decoder 315 is specified as the "single shift (i-th column is the first defective column)" mode in the truth table 400. In this mode, the i-th cut signal is true, and the (i+1)-th redundant shift signal, the (i+1)-th dual redundant shift signal, and the (i-1)-th cut signal are all false. If the i-th column group 301 is after the initial defective column group in the single shift region 110, the single shift mode of the decoder logic in the i-th decoder 315 is specified as the "single shift (i-th column is after the first defective column)" mode in the truth table 400. In this mode, the (i+1)-th redundant shift signal is true, and the i-th cut signal, the (i+1)-th dual redundant shift signal, and the (i-1)-th cut signal are all false. In both single shift modes, the iioth signal propagates through the i-th switch matrix 305 to be coupled to the (i−1)th column group 303 .

[0049] Conversely, if the i-th column group 301 is in the double shift region 115, the double shift mode in the truth table 400 is valid. In the double shift mode, there are three possibilities depending on the position of the i-th column group 301 in the double shift region 115. In the first possibility, the i-th column group 301 is the second defective column group. An example of the second defective column group is the 7th column group in the memory bank 100. The corresponding mode in the truth table 400 is designated as the "double shift (i-th column is the second defective column)" mode. In this mode, both the i-th cut-off signal and the (i+1)-th redundant shift signal are true, while the (i+1)-th dual redundant shift signal and the (i-1)-th cut-off signal are false. The decoder logic responds to these signal states by setting the i-th redundant shift signal, the i-th dual redundant shift signal, and the i-th dual redundant shift cut-off signal to true. Then, the switch 1a is turned off, the switch 1b is turned on, the switch 2a is turned on, and the switch 2b is turned off.

[0050] In the second possibility of the double shift mode, the i-th column group 301 is the column group following the second defective column group. An example of such a column group in the memory bank 100 would be any one of the 6th column group to the 0th column group. The corresponding mode in the truth table 400 is designated as the "double shift (i-th column after the 2nd defective column)" mode. In this mode, the (i+1)th redundant shift signal and the (i+1)th dual redundant shift signal are both true, while the i-th cut signal and the (i-1)th cut signal are both false. The decoder logic responds to these signal states by setting the i-th redundant shift signal, the i-th dual redundant shift signal, and the i-th dual redundant shift cut signal to true. Then, switch 1a is turned off, switch 1b is turned on, switch 2a is turned on, and switch 2b is turned off.

[0051] In a third possibility of a double shift mode, the i-th column group 301 is the previous column group of the second defective column group. An example of such a column group in the memory bank 100 would be the 8th column group. The corresponding mode in the truth table 400 is designated as the "double shift (i-th column before the 2nd defective column)" mode. In this mode, the (i+1)th redundant shift signal and the (i-1)th cut signal are both true, while the i-th cut signal and the (i+1)th redundant shift signal are both false. The decoder logic responds to these signal states by setting the i-th redundant shift signal and the i-th dual redundant shift cut signal to true and by setting the i-th dual redundant shift signal to false. Then switch 1a is turned off, switch 1b is turned on, switch 2a is turned off, and switch 2b is turned off.

[0052] Truth table 400 can be implemented using a variety of logic gates. Figure 4BAn example logic gate implementation of the i-th decoder 315 is shown in FIG. One function of the i-th decoder 315 is to determine whether the i-th column group 301 is the initial defective column group or the second defective column group in the corresponding memory bank. As previously described, a test of the memory bank can be performed at the time of manufacturing to identify the addresses of the initial defective column group (if any) and the second defective column group (if any). Therefore, there is a set of pre-decoding address signals fa-1, fb-1, and fc-1 that identify the first defective column group. These pre-decoding address signals are true only for the redundant decoder corresponding to the first defective column group. However, for all remaining redundant decoders, at least one of them is false. Similarly, there is a set of pre-decoding address signals fa-2, fb-2, and fc-2 that identify the second defective column group. These pre-decoding address signals are true only for the redundant decoder corresponding to the second defective column group. However, for all remaining redundant decoders, at least one of them is false. Each decoder is configured to assert its cutoff signal only when the set of pre-decoding address signals fa-1, fb-1 and fc-1 or the set of pre-decoding address signals fa-1, fb-2 and fc-2 of the default column group of the decoder is true. For example, if the i-th column group 301 is faulty, the i-th decoder 315 asserts the i-th cutoff signal.

[0053] In the i-th decoder 315, the first NAND gate 405 is used to decode the pre-decoded address signals fa-1, fb-1, and fc-1. The output signal of the first NAND gate 405 is false only when the i-th column group is the first defective column group, otherwise it is true. Similarly, the second NAND gate 410 is used to decode the pre-decoded address signals fa-2, fb-2, and fc-2. The output signal of the second NAND gate 410 is false only when the i-th column group is the second defective column group, otherwise it is true.

[0054] A logic gate such as NAND gate 415 NANDs the output signals from NAND gates 405 and 410 to produce the i-th severance signal. The combination of NOR gate 425 that NORs the i-th severance signal with the (i+1)-th redundant shift signal to produce the output signal red_shft_n will control the binary state of the i-th redundant shift, as discussed with respect to truth table 400, and the output signal red_shft_n is inverted by inverter 430 to produce the i-th redundant shift signal.

[0055] The combination of NAND gate 435, inverter 440, NOR gate 445, and inverter 450 can be further shown to control the binary state of the i-th dual-redundant shift signal, as discussed with respect to truth table 400. NAND gate 435 NANDs the i-th cut-off signal with the (i+1) redundant shift signal to produce an output signal that is inverted by inverter 440. NOR gate 445 NORs the output signal from inverter 440 with the (i+1) dual-redundant shift signal to produce an output signal dred_shft_n, which is inverted by inverter 450 to produce the i-th dual-redundant shift signal.

[0056] Additionally, the combination of NAND gate 455, inverter 460, NOR gate 465, and inverter 470 may be shown controlling the binary state of the i-th dual-redundant shift cut signal, as discussed with respect to truth table 400. NAND gate 455 NANDs the i-th redundant shift signal with the (i-1)-th cut signal to produce an output signal inverted by inverter 460. NOR gate 465 NORs the output signal of inverter 460 with the i-th dual-redundant shift signal to produce an output signal dred_shft_cut_n, which is inverted by inverter 470 to produce the i-th dual-redundant shift cut signal.

[0057] Note that the single and double column group shifting through the switch matrix disclosed herein does not affect the column multiplexing in the local data path. In other words, the column redundancy disclosed herein is independent of the column multiplexing, i.e., whether the column multiplexing is MUX2, MUX4, etc. Therefore, the column redundancy disclosed herein can be easily implemented in any suitable memory bank, regardless of the column multiplexing amplitude.

[0058] Some example implementations of the switch matrix will now be discussed.

[0059] Write Path Switch Matrix

[0060] Referring again to memory bank portion 300, it will be appreciated that the switch matrix is ​​shown in simplified form as there may be a write switch matrix for the write path and a separate read switch matrix for the read path. Figure 5, showing a portion 500 of a memory bank, which illustrates some example write-path switch matrices. Portion 500 includes seven switch matrices for seven column groups, starting from the Nth column group to the (N-6)th column group (N is a positive integer greater than six). In this example implementation, each switch 1A and switch 1B are formed by a transmission gate, although other types of switches may also be used. Each switch matrix therefore includes a transmission gate 1A and a transmission gate 1B. Each switch 2A and 2B are formed by a tri-state inverter, although other types of switches may also be used. Therefore, each switch matrix includes a tri-state inverter 2A and a tri-state inverter 2B. For clarity of illustration, the tri-state control signals for the 2A and 2B tri-state inverters are not shown. The (N-1)th column group is the first initially defective column. Therefore, the Nth column is still in the default non-shifted state. The data input signal of each column group is stored in the corresponding data in the (din) latch. The term "latch" is used herein to generally refer to a storage element that can store a binary signal.

[0061] Since the Nth column group is in the non-shift state, its tri-state inverter 2B and transmission gate 1A are turned on. The data in the signal for the Nth column group will therefore be turned on from its din latch to the data in the (din) buffer for the Nth column group. In the case where the (N-1)th column group is the first defective column group, each transmission gate 1A will not be turned on starting from the (N-1)th column group and continuing to the (N-6)th column group. Similarly, each transmission gate 1B will be turned on starting from the (N-1)th column group and continuing to the (N-6)th column group.

[0062] The second defective column group is the (N-4)th column group. The cut-off signal of each defective column group will be true, and the cut-off signal of each remaining column group will be false. Since the defective column groups are the (N-1)th column group and the (N-4)th column group, these column groups are the only column groups whose cut-off signals are true. In the case where the (N-4)th column group is the second defective column group, only the (N-1)th column group and the (N-2)th column group are in the single shift region. The three-state inverter 2B and the transmission gate 1B are therefore turned on in the switch matrix for these column groups, as discussed similarly to section 300. The (N-3)th column group to the (N-6)th column group are in the double shift region. Since the (N-3)th column group is the initial column group in the double shift region, the transmission gate 1A and the three-state inverters 2A and 2B in the corresponding switch matrix are not turned on. Starting from the second defective column group (in this example, the (N-4)th column group), each transmission gate 1B and tri-state inverter 2A are turned on to provide the desired dual redundant shift. Due to the inversion of the data input signal in the tri-state inverter 2A or 2B, each din buffer can be configured to invert its buffered data input signal. Some example read path switch matrices will now be discussed.

[0063] Read Path Switch Matrix

[0064] Figure 6 6 shows a portion 600 of a memory bank, which illustrates some example read path switch matrices. Portion 600 is similar to portion 500 and thus includes seven switch matrices for seven column groups, starting from the Nth column group to the (N-6)th column group (N is a positive integer greater than six). In this example implementation, each switch 1A and switch 1B are formed by a three-state inverter, although other types of switches may also be used. Therefore, each switch matrix includes a three-state inverter 1A and a three-state inverter 1B. Each switch 2A and 2B are also formed by a three-state inverter, although other types of switches may also be used. Therefore, each switch matrix includes a three-state inverter 2A and a three-state inverter 2B. For clarity of illustration, the three-state control signals for the 1A, 1B, 2A and 2B tri-state inverters are not shown. The (N-1)th column group is the first initially defective column group. Therefore, the Nth column group is still in the default non-shifted state. In some implementations, the read paths for these rank groups can be selected between rank groups of a first memory bank or rank groups of a second memory bank (memory banks are not shown for clarity of illustration).

[0065] Since the Nth column group is in the non-shifted state, the tri-state inverter 2B and the tri-state inverter 1A in the corresponding switch matrix are turned on. The data output signal for the Nth column group will therefore be turned on from the selected memory bank to the data output (dout) latch for the Nth column group. In the case where the (N-1)th column group is the first defective column group, each tri-state inverter 1A will not be turned on starting from the switch matrix for the (N-1)th column group and continuing to the switch matrix for the (N-6)th column group. Similarly, each tri-state inverter 1B will be turned on starting from the switch matrix for the (N-1)th column group and continuing to the switch matrix for the (N-6)th column group.

[0066] The second defective column group is the (N-4)th column group. The cut-off signal of each defective column group will be true, and the cut-off signal of each remaining column group will be false. Since the defective column groups are the (N-1)th column group and the (N-4)th column group, these column groups are the only column groups whose cut-off signals are true. In the case where the (N-4)th column group is the second defective column group, only the (N-1)th column group and the (N-2)th column group are single-shift columns. Therefore, the tri-state inverter 2B and the tri-state inverter 1B in the corresponding switch matrix are conductive for this single-shift state, as discussed similarly to section 300. The (N-3)th column group to the (N-6)th column group are double-shift column groups. Since the (N-3)th column group is the initial double-shift column group, the tri-state inverter 1A and the tri-state inverters 2A and 2B in the corresponding switch matrix are not conductive. Starting from the second defective column group (in this example, the (N-4)th column group), each tri-state inverter 1B and tri-state inverter 2A is turned on in the corresponding switch matrix to provide the desired dual redundant shift.

[0067] Now refer to Figure 7 The method includes an action 700 of coupling a first latch to a first column group of the plurality of column groups arranged consecutively from the initial column group in response to a subset of the plurality of column groups extending from the initial column group to the first column group without a defective column group. Figure 5 , coupling the Nth data input latch to the Nth column group is an example of action 700. Similarly, Figure 6 As shown in , coupling the Nth data output latch to the Nth column group is another example of act 700. The method also includes act 705 of coupling the first latch to a second column group of the plurality of column groups in response to the first column group being a first defective column group of the plurality of column groups, wherein the second column group is continuous with the first column group. Figure 5 The coupling of the (N-1)th data input latch to the (N-2)th column group as shown in is an example of action 705. Similarly, Figure 6 As shown in FIG. 7 , coupling the (N-1)th data output latch to the (N-2)th column group is an example of act 705. Finally, the method includes act 710 of coupling the first latch to a third column group among the plurality of column groups in response to the second column group being a second defective column group among the plurality of column groups, wherein the third column group is continuous with the second column group. Figure 5 The coupling of the (N-4)th data input latch to the (N-6)th column group shown in is an example of action 710. Similarly, Figure 6 The coupling of the (N−4)th data output latch to the (N−6)th column group shown in FIG. 7 is an example of action 710 .

[0068] The memory disclosed herein can be incorporated into a variety of electronic systems. For example, Figure 8As shown in , a cellular phone 800, a laptop computer 805, and a tablet PC 810 can all include a memory with dual redundant shifting according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with a memory constructed according to the present disclosure.

[0069] The present disclosure will now be summarized by the following example clauses:

[0070] Clause 1. A memory, the memory comprising:

[0071] a plurality of column groups, each of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group, a second column group adjacent to the first column group, and a third column group adjacent to the second column group; and a first switch matrix configured to couple a latch to one of the first column group, the second column group, and the third column group in response to a plurality of column redundancy signals.

[0072] Clause 2. The memory of clause 1, wherein the first switch matrix comprises:

[0073] The first central node;

[0074] a first switch coupled between the first column group and the first central node; and

[0075] a second switch coupled between the first central node and the latch, the memory further comprising:

[0076] a first decoder configured to close the first switch and close the second switch to couple the latch to the first column group in response to the plurality of column groups having no defective column groups from an initial column group in the plurality of column groups to the first column group. Clause 3. The memory of Clause 2, wherein the first switch matrix further comprises:

[0077] a third switch coupled between the first center node and the second column group, wherein the first decoder is further configured to open the first switch, close the second switch, and close the third switch to couple the latch to the second column group in response to the first column group being an initial defective column group among the plurality of column groups.

[0078] Clause 4. The memory of Clause 2, wherein the first decoder is further configured to open the second switch in response to the second column group being a second defective column group among the plurality of column groups, the memory further comprising:

[0079] a second switch matrix including a third switch coupled between the latch and a second center node and including a fourth switch coupled between the second center node and the third column group; and

[0080] a second decoder configured to close the third switch and close the fourth switch to couple the latch to the third column group in response to the second column group being the second defective column group. Clause 5. The memory of any of Clauses 1 to 4, wherein the memory further comprises:

[0081] a first redundant rank; and

[0082] A second redundant rank.

[0083] Clause 6. The memory of any of Clauses 2 to 4, wherein the first switch comprises a transmission gate and the second switch comprises a tri-state inverter.

[0084] Clause 7. A memory comprising:

[0085] a plurality of column groups, each column group of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group and a second column group adjacent to the first column group;

[0086] a first latch;

[0087] a second latch; and

[0088] A first switch matrix, the first switch matrix comprising: a first switch coupled between the first column group and a first center node, a second switch coupled between the first center node and the second column group, a third switch coupled between the first latch and the first center node, and a fourth switch coupled between the first center node and the second latch. Clause 8. The memory of Clause 7, wherein the first switch matrix comprises:

[0089] A third latch;

[0090] a first redundant column group, the first redundant column group being adjacent to the second column group;

[0091] a second redundant rank group, the second redundant rank group being adjacent to the first redundant rank group; and

[0092] a second switch matrix, the second switch matrix comprising: a first switch coupled between the second column group and a second central node, a second switch coupled between the second central node and the first redundant column group, a third switch coupled between the second latch and the second central node, and a fourth switch coupled between the second central node and the third latch. Clause 9. A memory according to any one of clauses 7 to 8, wherein the first decoder is configured to control the first switch matrix in response to whether the first column group is a non-shift region among the plurality of column groups, a single shift region among the plurality of column groups, or a double shift region among the plurality of column groups.

[0093] Clause 10. The memory of clause 9, wherein the first decoder is further configured to decode an address of the first column group to determine whether the first column group is in the no-shift region, the single-shift region, or the double-shift region. Clause 11. The memory of any one of clauses 1 to 10, wherein the memory is integrated into a cellular phone.

[0094] Clause 12. The memory of any one of clauses 1 to 10, wherein the memory is a static random access memory (SRAM).

[0095] Clause 13. The memory of any of Clauses 7 to 12, wherein the first column group comprises a first plurality of bit line pairs and the second column group comprises a second plurality of bit line pairs.

[0096] Clause 14. A memory, the memory comprising:

[0097] a plurality of column groups, each of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group and a second column group; a first latch; a second latch;

[0098] a first switch matrix coupled to the first column group, the second column group, the first latch, and the second latch;

[0099] A first redundant column group, the first redundant column group including a first plurality of multiplexed redundant columns; and a second redundant column group, the second redundant column group including a second plurality of multiplexed redundant columns.

[0100] Clause 15. The memory according to clause 14, further comprising:

[0101] A first decoder is configured to decode an address signal in response to a column redundancy state of the plurality of column groups to control a switch state of the first switch matrix.

[0102] Clause 16. The memory of clause 15, wherein the first switch matrix comprises:

[0103] A first switch coupled between the first column group and a first center node, a second switch coupled between the first center node and the second column group, a third switch coupled between the first latch and the first center node, and a fourth switch coupled between the first center node and the second latch.

[0104] Clause 17. The memory of any of Clauses 14 to 16, wherein each plurality of multiplexed columns comprises a plurality of multiplexed bit line pairs.

[0105] Clause 18. The memory of any of clauses 15 to 16, wherein the first decoder comprises a first logic gate configured to decode a first address signal. Clause 19. The memory of clause 18, wherein the first decoder further comprises a second logic gate configured to decode a second address signal.

[0106] Clause 20. The memory of Clause 19, wherein the first logic gate and the second logic gate each comprise a NAND gate.

[0107] Clause 21. A memory according to any one of clauses 14 to 20, wherein the first latch and the second latch each comprise an input latch for writing a bit. Clause 22. A method for column redundancy, the method comprising:

[0108] responsive to a subset of a plurality of column groups extending from an initial column group to a first column group without a defective column group, coupling a first latch to a first column group of the plurality of column groups arranged consecutively from the initial column group;

[0109] coupling the first latch to a second column group among the plurality of column groups in response to the first column group being a first defective column group among the plurality of column groups, wherein the second column group is continuous with the first column group; and coupling the first latch to a third column group among the plurality of column groups in response to the second column group being a second defective column group among the plurality of column groups, wherein the third column group is continuous with the second column group.

[0110] Clause 23. The method according to clause 22, further comprising:

[0111] A first address is decoded to determine whether the first column group is the first defective column group of the plurality of column groups.

[0112] Clause 24. The method according to clause 23, further comprising:

[0113] A second address is decoded to determine whether the first column group is the second defective column group of the plurality of column groups.

[0114] Clause 25. The method of clause 24, wherein decoding the first address comprises decoding the first address in a first logic gate, and decoding the second address comprises decoding the second address in a second logic gate. Clause 26. The method of any one of clauses 22 to 27, further comprising:

[0115] In response to the plurality of column groups having no defective column groups, a final latch is coupled to a final column group of the plurality of column groups.

[0116] Clause 27. The method according to clause 28, further comprising:

[0117] In response to the plurality of rank groups including the first defective rank group and not including the second defective rank group, the final latch is coupled to a first redundant rank group.

[0118] Clause 28. The method according to clause 26, further comprising:

[0119] In response to the plurality of rank groups including the first defective rank group and the second defective rank group, coupling the final latch to a second redundant rank group. Clause 29. The method of Clause 28, wherein coupling the final latch to the second redundant rank group comprises coupling a final input latch to the second redundant rank group.

[0120] Clause 30. The method of Clause 28, wherein coupling the final latch to the second redundant rank group comprises coupling a final output latch to the second redundant rank group.

[0121] As those skilled in the art will understand by now and depending on the specific application at hand, many modifications, substitutions and changes may be made to the materials, devices, configurations and methods of using the apparatus of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the specific implementations illustrated and described herein (as they are only some examples of the present disclosure), but should be fully equivalent to the attached claims and their functional equivalents.

Claims

1. A memory, comprising: a plurality of column groups, each of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group, a second column group adjacent to the first column group, and a third column group adjacent to the second column group; as well as A first switch matrix is ​​configured to couple a latch to one of the first column group, the second column group, and the third column group in response to a plurality of column redundancy signals.

2. The memory according to claim 1, wherein the first switch matrix comprises: The first central node; a first switch coupled between the first column group and the first central node; and a second switch coupled between the first central node and the latch, the memory further comprising: A first decoder is configured to close the first switch and close the second switch to couple the latch to the first column group in response to the plurality of column groups having no defective column groups from an initial column group of the plurality of column groups to the first column group.

3. The memory according to claim 2, wherein the first switch matrix further comprises: a third switch coupled between the first center node and the second column group, wherein the first decoder is further configured to open the first switch, close the second switch, and close the third switch to couple the latch to the second column group in response to the first column group being an initial defective column group among the plurality of column groups.

4. The memory of claim 2, wherein the first decoder is further configured to open the second switch in response to the second column group being a second defective column group among the plurality of column groups, the memory further comprising: a second switch matrix including a third switch coupled between the latch and a second center node and including a fourth switch coupled between the second center node and the third column group; as well as A second decoder is configured to close the third switch and close the fourth switch to couple the latch to the third column group in response to the second column group being the second defective column group.

5. The memory according to claim 1, wherein the memory further comprises: a first redundant column group; and A second redundant rank.

6. The memory of claim 2, wherein the first switch comprises a transmission gate and the second switch comprises a tri-state inverter.

7. A memory, comprising: a plurality of column groups, each column group of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group and a second column group adjacent to the first column group; a first latch; A second latch; and A first switch matrix, the first switch matrix comprising: a first switch coupled between the first column group and a first center node, a second switch coupled between the first center node and the second column group, a third switch coupled between the first latch and the first center node, and a fourth switch coupled between the first center node and the second latch.

8. The memory according to claim 7, wherein the second rank group is a final rank group among the plurality of rank groups, the memory further comprising: A third latch; a first redundant column group, the first redundant column group being adjacent to the second column group; a second redundant column group, the second redundant column group being adjacent to the first redundant column group; and a second switch matrix, the second switch matrix comprising: a first switch coupled between the second column group and a second central node, a second switch coupled between the second central node and the first redundant column group, a third switch coupled between the second latch and the second central node, and a fourth switch coupled between the second central node and the third latch.

9. The memory according to claim 7, further comprising: A first decoder is configured to control the first switch matrix in response to whether the first column group is a no-shift region among the plurality of column groups, a single-shift region among the plurality of column groups, or a double-shift region among the plurality of column groups. 10 . The memory of claim 9 , wherein the first decoder is further configured to decode an address of the first column group to determine whether the first column group is in the no-shift region, the single-shift region, or the double-shift region.

11. The memory of claim 7, wherein the memory is included in a cellular telephone.

12. The memory of claim 7, wherein the memory is a static random access memory (SRAM).

13. The memory of claim 7, wherein the first column group includes a first plurality of bit line pairs and the second column group includes a second plurality of bit line pairs.

14. A memory, comprising: a plurality of column groups, each column group of the plurality of column groups comprising a plurality of multiplexed columns, the plurality of column groups comprising a first column group and a second column group; a first latch; A second latch; a first switch matrix coupled to the first column group, the second column group, the first latch, and the second latch; a first redundant column group, the first redundant column group comprising a first plurality of multiplexed redundant columns; and A second redundant column group includes a second plurality of multiplexed redundant columns.

15. The memory according to claim 14, further comprising: A first decoder is configured to decode an address signal in response to a column redundancy state of the plurality of column groups to control a switch state of the first switch matrix.

16. The memory of claim 15, wherein the first switch matrix comprises: A first switch coupled between the first column group and a first center node, a second switch coupled between the first center node and the second column group, a third switch coupled between the first latch and the first center node, and a fourth switch coupled between the first center node and the second latch.

17. The memory of claim 15, wherein each plurality of multiplexed columns comprises a plurality of multiplexed bit line pairs.

18. The memory of claim 15, wherein the first decoder comprises a first logic gate configured to decode a first address signal.

19. The memory of claim 18, wherein the first decoder further comprises a second logic gate configured to decode a second address signal.

20. The memory of claim 19, wherein the first logic gate and the second logic gate each comprise a NAND gate.

21. The memory of claim 16, wherein the first latch and the second latch each comprise an input latch for writing a bit.

22. A column redundancy method, the method comprising: coupling a first latch to a first column group of the plurality of column groups in response to a subset of the plurality of column groups extending from an initial column group to a first column group without a defective column group; coupling the first latch to a second column group among the plurality of column groups in response to the first column group being a first defective column group among the plurality of column groups, wherein the second column group is adjacent to the first column group; as well as The first latch is coupled to a third column group among the plurality of column groups in response to the second column group being a second defective column group among the plurality of column groups, wherein the third column group is adjacent to the second column group.

23. The method according to claim 22, further comprising: A first address is decoded to determine whether the first column group is the first defective column group of the plurality of column groups.

24. The method according to claim 23, further comprising: A second address is decoded to determine whether the first column group is the second defective column group of the plurality of column groups.

25. The method of claim 24, wherein decoding the first address comprises decoding the first address in a first logic gate, and decoding the second address comprises decoding the second address in a second logic gate.

26. The method according to claim 24, further comprising: In response to the plurality of column groups having no defective column groups, a final latch is coupled to a final column group of the plurality of column groups.

27. The method according to claim 26, further comprising: In response to the plurality of rank groups including the first defective rank group and not including the second defective rank group, the final latch is coupled to a first redundant rank group.

28. The method according to claim 26, further comprising: In response to the plurality of rank groups including the first defective rank group and the second defective rank group, the final latch is coupled to a second redundant rank group.

29. The method of claim 28, wherein coupling the final latch to the second redundant rank group comprises coupling a final input latch to the second redundant rank group.

30. The method of claim 28, wherein coupling the final latch to the second redundant rank group comprises coupling a final output latch to the second redundant rank group.

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