Flat panel detector, exposure control system and X-ray detection system

Abstract

The invention provides a flat panel detector, an exposure control system and an X-ray detection system, and belongs to the technical field of detectors. The flat panel detector of the present disclosure includes: a sensing panel including a pixel unit, a read line, and a scan line; the reading circuit board comprises two reading circuits which are arranged on the two sides, oppositely arranged in the first direction, of the sensing panel respectively. The reading circuit comprises a plurality of reading sub-circuits, and the reading sub-circuits in the reading circuits at different sides are arranged in a one-to-one correspondence manner; reading lines connected with the reading sub-circuits are different; the gate driving circuit board comprises a shift register; the gate drive circuit board comprises a first side and a second side which are oppositely arranged along a first direction, a part of shift registers in a direction from a target center of the gate drive circuit board to the first side are cascaded in sequence, and the other part of shift registers in a direction from the target center to the second side are cascaded in sequence. And the first shift registers cascaded at different sides are electrically connected with the initial signal end on the main control board.

Description

Technical Field

[0001] The present invention belongs to the technical field of detectors, and in particular relates to a flat panel detector, an exposure control system and an X-ray detection system. Background Art

[0002] X-ray detection technology is an X-ray digital radiography (DR) detection technology that appeared in the 1990s. Due to the advantages of DR technology such as fast imaging speed, high resolution, and high signal-to-noise ratio, it is widely used in medical imaging, industrial detection, security detection, and scientific research. The core of the DR system is the X-ray receiving device, such as the flat panel detector (FPD), which has the advantages of high-quality imaging and high resolution.

[0003] There are two main types of flat panel detectors currently used in the market, one is a static detector and the other is a dynamic detector. Among them, static detectors usually only have a single-sided integrated read-out integrated circuit (ROIC) board due to their low frame rate. Dynamic detectors use double-sided and double-number ROICs for data acquisition due to their high frame rate. Under this structural layout, using the scanning method of the traditional gate drive circuit will result in serious screen splitting. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a flat panel detector, an exposure control system and an X-ray detection system.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a flat panel detector, which includes a sensing panel, a reading circuit board, a gate driving circuit board and a main control board; the main control board includes a start signal terminal;

[0006] The sensing panel includes a plurality of pixel units, a plurality of readout lines extending along a first direction, and a plurality of scan lines extending along a second direction; the pixel units are electrically connected to one of the scan lines and one of the readout lines; the plurality of readout lines are divided into a plurality of readout line groups arranged side by side in the second direction, each of the readout line groups includes two readout lines arranged side by side and spaced apart in the first direction;

[0007] The readout circuit board comprises two readout circuits, which are respectively arranged on two sides of the sensing panel that are arranged opposite to each other along the first direction; the readout circuit comprises a plurality of readout sub-circuits arranged side by side along the second direction, and the readout sub-circuits in the readout circuits on different sides are arranged one by one correspondingly; the two readout sub-circuits arranged correspondingly are respectively electrically connected to different readout lines in a group of the readout line groups;

[0008] The gate driving circuit board comprises a plurality of shift registers arranged side by side along a first direction, and the shift registers are connected to the scan lines in a one-to-one correspondence;

[0009] The two sides of the gate driving circuit board that are relatively arranged along the first direction are recorded as the first side and the second side. A part of the shift registers in the direction from the target center of the gate driving circuit board to the first side are cascaded in sequence, and another part of the shift registers in the direction from the target center to the second side are cascaded in sequence. The first shift register cascaded on different sides is electrically connected to the start signal terminal.

[0010] In some embodiments, the gate driving circuit includes N shift registers;

[0011] When N is an even number greater than or equal to 2, the N / 2th shift register and the N / 2+1th shift register are both electrically connected to the start signal terminal; the N / 2th shift register is sequentially cascaded to the first gate drive chip; the N / 2+1th shift register is sequentially cascaded to the Nth shift register;

[0012] When N is an odd number greater than 1, the (N+1) / 2th shift register is electrically connected to the start signal terminal, the output terminal of the (N+1) / 2th shift register is electrically connected to the input terminal of the (N+1) / 2-1th shift register and the input terminal of the (N+1) / 2+1th shift register; the (N+1) / 2th shift register is cascaded sequentially to the 1st gate drive chip; and the (N+1) / 2th shift register is cascaded sequentially to the Nth shift register.

[0013] In some embodiments, the shift register is configured to provide a gate driving signal to the pixel unit in response to receiving a frame start signal sent by the start signal terminal;

[0014] The pixel unit is configured to collect image data of the object under test in response to the gate drive signal transmitted by the scanning line;

[0015] The reading subcircuit is configured to receive the image data transmitted by the reading line and send it to the main control board;

[0016] The main control board is configured to convert the image data into a bright field image and output it.

[0017] In some embodiments, the main control board includes a controller and a data transmission line; the data transmission line electrically connects the controller and the reading subcircuit; the data transmission line is used to transmit the image data;

[0018] The data transmission line is a differential signal line; the differential signal line includes a group of differential sub-line pairs with equal lengths.

[0019] In some embodiments, the flat panel detector further comprises an outer frame and a middle frame; the reading circuit board is arranged on a side of the middle frame close to the outer frame, the sensing panel is arranged on a side of the middle frame away from the reading circuit board, and the main control board is arranged on a side of the outer frame close to the reading circuit board;

[0020] The data transmission line comprises a first sub-segment and a second sub-segment which are electrically connected and are in different layers. The first sub-segment and the second sub-segment are bridged by a first connecting via. The first sub-segment is closer to the reading sub-circuit than the second sub-segment. One end of the first sub-segment is electrically connected to the reading sub-circuit, and one end of the second sub-segment is electrically connected to the controller.

[0021] A second connection via is disposed around the first connection via, and the second connection via is grounded.

[0022] In some embodiments, the readout circuit board further comprises a grounding layer disposed on a side of the readout subcircuit close to the sensing panel and a first grounding terminal disposed on a side of the readout subcircuit away from the grounding layer, wherein the first grounding terminal is electrically connected to the grounding layer; the flat panel detector further comprises a first connector disposed on a side of the readout circuit board close to the main control board, wherein the first connector electrically connects the readout subcircuit and the main control board;

[0023] The housing of the first connector is in direct contact with the first ground terminal.

[0024] In some embodiments, the flat panel detector further includes an adapter; the first connector is electrically connected to the main control board through the adapter; and the output pad spacing of the adapter is greater than the pad spacing of the first connector.

[0025] In some embodiments, the reading circuit board also includes a plurality of first connecting pads and a plurality of second connecting pads arranged on the side of the reading sub-circuit away from the ground layer, and the second connecting pads are arranged between adjacent first connecting pads; the first connecting pads are bound and connected to the first connector, and the second connecting pads are electrically connected to the ground layer.

[0026] In some embodiments, the flat panel detector further includes a middle frame disposed on a side of the reading subcircuit close to the sensing panel;

[0027] The reading circuit board also includes a solder resist layer arranged on a side of the ground layer close to the sensing panel; the solder resist layer has an opening, the opening exposes the ground layer, the ground layer is in direct contact with the middle frame, and the middle frame is grounded.

[0028] In some embodiments, the flat panel detector further comprises an outer frame and a middle frame; the reading circuit board is arranged on a side of the middle frame close to the outer frame, the sensing panel is arranged on a side of the middle frame away from the reading circuit board, and the main control board is arranged on a side of the outer frame close to the reading circuit board;

[0029] The reading subcircuit, the shift register and the main control board are all fixed on the middle frame through different grounding holes, and the middle frame is grounded.

[0030] In some embodiments, the main control board includes a power supply; the flat panel detector further includes a second connector and a third connector disposed on a side of the reading circuit board close to the main control board, the second connector and the third connector being electrically connected to different reading circuits;

[0031] The power supply is electrically connected to the second connector via a first power line, and is used to supply power to each of the read sub-circuits in one of the read circuits electrically connected to the second connector; the power supply is electrically connected to the third connector via a second power line, and is used to supply power to each of the read sub-circuits in another of the read circuits electrically connected to the third connector;

[0032] The first power line and the second power line have the same resistance.

[0033] In some embodiments, the main control board further includes a second ground terminal, a first power signal terminal and a second power signal terminal, and the second ground terminal is arranged between the adjacent first power signal terminal and the second power signal terminal;

[0034] The first power signal terminal and the second power signal terminal are both electrically connected to the shift register and are used to provide power signals with different voltages to the shift register.

[0035] In some embodiments, the flat panel detector further includes an outer frame, a middle frame, a first heat conducting structure, and a second heat conducting structure;

[0036] The reading circuit board is arranged on a side of the middle frame close to the outer frame, the sensing panel is arranged on a side of the middle frame away from the reading circuit board, and the main control board is arranged on a side of the outer frame close to the reading circuit board;

[0037] The first heat-conducting structure is arranged between the reading subcircuit and the middle frame; and the second heat-conducting structure is arranged between the main control board and the outer frame.

[0038] In a second aspect, an embodiment of the present disclosure further provides an exposure control system, which includes a flat panel detector, a high voltage generator, a host and a light source as described in any one of the first aspects;

[0039] The host is configured to send an image acquisition instruction to the main control board of the flat panel detector; and send exposure configuration information to the high voltage generator;

[0040] The main control board is configured to send a preparation signal to the high voltage generator in response to the image acquisition instruction; and send an exposure control signal to the high voltage generator in response to receiving a feedback signal sent by the high voltage generator;

[0041] The high-voltage generator is configured to respond to the preparation signal, configure pre-exposure parameters according to the exposure configuration information, and generate a feedback signal to send to the main control board when the configuration is completed; and, in response to receiving the exposure control signal, control the lighting of the light source.

[0042] In some embodiments, the exposure control system further includes a photoelectric coupler, and the main control board is electrically connected to the high voltage generator via the photoelectric coupler.

[0043] In a third aspect, an embodiment of the present disclosure further provides an X-ray detection system, which includes any image exposure control system as described in the second aspect, and a display panel;

[0044] The host is configured to receive the bright field image sent by the main control board and send it to the display panel;

[0045] The display panel is configured to display the bright field image. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of a bilateral driving circuit of an existing flat panel detector;

[0047] Figure 2 A schematic diagram of another existing double-sided driving circuit of a flat panel detector;

[0048] Figure 3 A schematic diagram of a driving circuit of a flat panel detector provided in an embodiment of the present disclosure;

[0049] Figure 4 A schematic diagram of the arrangement of the reading lines provided in the embodiment of the present disclosure;

[0050] Figure 5 A schematic diagram of a driving circuit for an even number of shift registers provided by an embodiment of the present disclosure;

[0051] Figure 6A schematic diagram of a driving circuit for an odd number of shift registers provided by an embodiment of the present disclosure;

[0052] Figure 7 A schematic diagram of signal transmission of a flat panel detector provided in an embodiment of the present disclosure;

[0053] Figure 8 A schematic diagram of a driving circuit of a pixel unit provided in an embodiment of the present disclosure;

[0054] Fig. 9 A schematic diagram of the electrical connection relationship of the driving circuit of the flat panel detector provided in an embodiment of the present disclosure;

[0055] Fig.10 for Fig. 9 A partial longitudinal schematic diagram of the central main control board and the reading circuit board;

[0056] Fig.11 Another signal transmission schematic diagram of the flat panel detector provided in the embodiment of the present disclosure;

[0057] Fig.12a A schematic plan view of a reading circuit board provided in an embodiment of the present disclosure;

[0058] Figure 12b A schematic diagram of reading a pad on a circuit board provided by an embodiment of the present disclosure;

[0059] Fig.13 A schematic plan view of a flat panel detector provided in an embodiment of the present disclosure;

[0060] Fig.14 A schematic diagram of power supply routing provided in an embodiment of the present disclosure;

[0061] Fig.15 A partial schematic diagram of the power supply area of ​​the shift register of the main control board provided in the embodiment of the present disclosure;

[0062] Fig.16 A schematic plan view of a flat panel detector provided in an embodiment of the present disclosure;

[0063] Fig.17 A schematic diagram of the longitudinal distribution of each circuit board of the flat panel detector provided by an embodiment of the present disclosure;

[0064] Fig.18 A schematic diagram of an exposure control system of a low-speed static detector in the related art;

[0065] Fig.19 A schematic diagram of an exposure control system provided by an embodiment of the present disclosure;

[0066] Figure 20a to Figure 20c A circuit diagram between a high voltage generator and a flat panel detector provided in an embodiment of the present disclosure;

[0067] Fig.21 A schematic diagram of another exposure control system provided by an embodiment of the present disclosure;

[0068] Fig. 22 A schematic diagram of an X-ray detection system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0070] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0071] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0072] It should be noted that in the present disclosure, the first direction X, the second direction Y and the third direction Z intersect each other. The first direction X and the second direction Y are perpendicular to each other in the plane where the sensing panel is located, wherein the first direction X can be the row direction in the pixel units arranged in an array, or can also be the column direction. Among them, the row direction is the horizontal direction, and the column direction is the vertical direction. When the first direction X is the row direction, the second direction Y is the column direction; when the first direction X is the column direction, the second direction Y is the row direction. The third direction Z is the vertical direction. The present disclosure takes the first direction X as the row direction and the second direction Y as the column direction as an example for explanation, which does not constitute a limitation to the present disclosure.

[0073] It should be noted that the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. Among them, N-type thin film transistor refers to N-type ion doping in the active layer of the thin film transistor; P-type thin film transistor refers to P-type ion doping in the active layer of the thin film transistor. The working level signal of the N-type thin film transistor is a high level signal; the working level signal of the P-type thin film transistor is a low level signal.

[0074] In the related art, low-speed static detectors usually have only one-sided integrated ROIC board due to their low frame rate (e.g., about 5Fps). Even if there is a double-sided ROIC board, the ROIC01 on both sides is staggered, and the read line 011 connects the pixel units of the entire row (or column) in its extension direction, such as Figure 1 As shown. Therefore, when designing the gate drive circuit 02, the gate drive signal (Gate) can be scanned column by column (or row by row). The start signal (STV_In) enters from the first shift register 021 (counting from left to right), and the end signal (STV_Out) is output from the last shift register 021. The time difference of all column data is the transmission time of a scan line 022, so there will be no split screen problem.

[0075] High-speed dynamic detectors use double-sided and double-number ROICs for data acquisition due to their high frame rate (e.g. 30Fps), and a single read line only runs through approximately half of the sensing panel. At this time, if the traditional gate scanning method is still used for scanning in the same direction, such as Figure 2As shown, the data collection of the last column of the left half screen is delayed by half a frame time compared to the data collection of the first column of the right half screen, and the last column of data of the left half screen and the first column of data of the left half screen are adjacent columns, which will cause serious split-screen phenomenon on the sensing panel, and ultimately manifest as a bright field image presented on the user side (display panel) with a more obvious brightness difference in the middle of the screen.

[0076] In view of this, embodiments of the present disclosure provide a flat panel detector that substantially eliminates one or more of the problems caused by limitations and defects of the related art.

[0077] Figure 3 A schematic diagram of a driving circuit of a flat panel detector provided in an embodiment of the present disclosure, Figure 4 The schematic diagram of the arrangement of the reading line 12 provided in the embodiment of the present disclosure is as follows: Figure 3 and Figure 4 As shown, the flat panel detector includes a sensing panel 1, a reading circuit board 2, a gate driving circuit board 3 and a main control board 4; the main control board 4 includes a start signal terminal STV0.

[0078] Wherein, the sensing panel 1 includes a plurality of pixel units 11, a plurality of read lines 12 extending along a first direction X, and a plurality of scan lines 13 extending along a second direction Y. The pixel unit 11 is mainly used to collect external visible light and convert it into an electrical signal to obtain image data of the object under test, so as to provide it to the user and present a bright field image. Exemplarily, the pixel unit 11 mainly includes a sub-pixel (not shown in the figure) and a driving circuit (not shown in the figure) for driving the sub-pixel. The sub-pixel includes but is not limited to a photodiode 111, which is used to convert the optical signal into an electrical signal. The scan line 13 is mainly used to transmit the gate drive signal to the pixel unit 11. The read line 12 is mainly used to transmit the image data output by the pixel unit 11. Therefore, each pixel unit 11 is electrically connected to a scan line 13 and a read line 12 independently.

[0079] Optionally, the plurality of pixel units 11 are arranged in an array, including a plurality of rows and a plurality of columns of pixel units 11 .

[0080] The plurality of read lines 12 are divided into a plurality of read line groups 5 arranged side by side in the second direction Y, and each read line group 5 includes two read lines 12 arranged side by side and spaced apart in the first direction X. The read lines 12 in one read line group 5 are electrically connected to a row of pixel units 11. Different read lines 12 are electrically connected to different pixel units 11. Exemplarily, the two read lines 12 in the read line group 5 are respectively recorded as a first read line 121 and a second read line 122, the first read line 121 is electrically connected to the pixel units 11 in the left half of the sensing panel 1, and the second read line 122 is electrically connected to the pixel units 11 in the right half of the sensing panel 1. The first read line 121 and the second read line 122 in the same read line group 5 are spaced apart.

[0081] The reading circuit board 2 includes two reading circuits 20, which are respectively arranged on two sides of the sensing panel 1 that are relatively arranged along the first direction X; the reading circuit 20 includes a plurality of reading sub-circuits 21 arranged side by side along the second direction Y, and the reading sub-circuits 21 in the reading circuits 20 on different sides are arranged one by one; the two correspondingly arranged reading sub-circuits 21 are respectively electrically connected to different reading lines 12 in a group of reading line groups 5.

[0082] Exemplarily, the read lines 12 are arranged in a one-to-one correspondence with the read sub-circuits 21. The two read circuits 20 are respectively recorded as a first read circuit 201 and a second read circuit 202. The read sub-circuit 21 in the first read circuit 201 is electrically connected to the first read line 121, and the read sub-circuit 21 in the second read circuit 202 is electrically connected to the second read line 122.

[0083] Exemplarily, the reading sub-circuit 21 is a ROIC.

[0084] The gate driving circuit board 3 includes a plurality of shift registers 31 arranged side by side along the first direction X. The shift registers 31 are connected to the scan lines 13 in a one-to-one correspondence.

[0085] Optionally, the number of the reading sub-circuits 21 in the reading circuit 20 is the same as the number of rows of the pixel units 11 . The number of the shift registers 31 is the same as the number of columns of the pixel units 11 .

[0086] The two sides of the gate driving circuit board 3 that are relatively arranged along the first direction X are recorded as the first side 3a and the second side 3b. A part of the shift registers 31 in the direction from the target center O of the gate driving circuit board 3 to the first side 3a are cascaded in sequence, and another part of the shift registers 31 in the direction from the target center O to the second side 3b are cascaded in sequence. The first shift registers 31 cascaded on different sides are electrically connected to the start signal terminal STV0.

[0087] Here, when the number of the multiple shift registers 31 is an even number, the target center O may be the center of the middle two shift registers of the even number of shift registers 31; when the number of the multiple shift registers 31 is an odd number, the target center O may be the location of the central shift register 31. The start signal terminal STV0 is located on the reference line in the second direction Y where the target center O is located.

[0088] The first shift register 31 is electrically connected to the start signal terminal STV0, and is used to receive a frame start signal at the power-on start stage to enter the scanning stage, and output a start signal of the next stage to the next stage step by step to achieve column-by-column scanning.

[0089] The gate driving circuit includes N shift registers 31 (represented as the first shift register 31 , the second shift register 31 , . . . , the Nth shift register 31 from left to right); N is a positive integer greater than or equal to 1.

[0090] Alternatively, if Figure 5 As shown, if N is an even number, the N / 2th shift register 31 and the N / 2+1th shift register 31 are both electrically connected to the start signal terminal STV0; the N / 2th shift register 31 is sequentially cascaded to the 1st gate drive chip, that is, the output signal of the N / 2th shift register 31 is used as the input signal (start signal) of the N / 2-1th shift register 31; the N / 2+1th shift register 31 is sequentially cascaded to the Nth shift register 31, that is, the output signal of the N / 2+1th shift register 31 is used as the input signal (start signal) of the N / 2+2th shift register 31.

[0091] like Figure 5 As shown, the first reading line 121 and the second reading line 122 each pass through half of the sensing panel 1. The first reading line 121 and the second reading line 122 are symmetrically arranged, with the same length, the same material, and the same impedance.

[0092] Alternatively, if Figure 6As shown, if N is an odd number, the (N+1) / 2th shift register 31 is electrically connected to the start signal terminal STV0, and the output terminal of the (N+1) / 2th shift register 31 is electrically connected to the input terminal of the (N+1) / 2-1th shift register 31 and the input terminal of the (N+1) / 2+1th shift register 31, that is, the output signal of the (N+1) / 2th shift register 31 is also used as the input signal of the (N+1) / 2-1th shift register 31 and the input signal of the (N+1) / 2+1th shift register 31. The (N+1) / 2th shift register 31 is cascaded to the first gate drive chip in sequence; the (N+1) / 2th shift register 31 is cascaded to the Nth shift register 31 in sequence. That is to say, if N is an odd number, the first shift registers 31 cascaded on different sides are shared, and the output signal is simultaneously output to the input end of the (N+1) / 2-1th shift register 31 and the input end of the (N+1) / 2+1th shift register 31.

[0093] The flat-panel detector provided by the disclosed embodiment utilizes bilateral and double-number ROICs for data acquisition, and a single read line 12 only runs through approximately half of the sensing panel 1; at the same time, multiple shift registers 31 are grouped and reversely cascaded and scanned, so that the data acquisition of adjacent columns of pixel units 11 at the boundary position of the first read line 121 and the second read line 122 can be performed synchronously (when N is an even number), or the data acquisition of all columns of pixel units 11 differs in time by only the transmission duration of one scan line 13 (when N is an odd number), so that the split screen phenomenon will not occur, thereby solving the split screen problem in the related art.

[0094] In some embodiments, Figure 7 A signal transmission schematic diagram of a flat panel detector provided in an embodiment of the present disclosure, such as Figure 7 As shown, the frame start signal (STV) is a signal sent by the main control board 4 to the shift register 31 for controlling the shift register 31 to start the scanning function. The gate drive signal (Gata) is a gate signal output by the shift register 31 for turning on the switch transistor 112 of the pixel unit 11.

[0095] Specifically, the shift register 31 is configured to provide a gate drive signal to the pixel unit 11 in response to a frame start signal (STV) sent by the start signal receiving terminal STV0. The pixel unit 11 is configured to collect image data of the object under test in response to the gate drive signal transmitted by the scan line 13. The reading subcircuit 21 is configured to receive image data transmitted by the reading line 12 and send it to the main control board 4. The main control board 4 is configured to convert the image data into a bright field image and output it.

[0096] Optionally, Figure 8A schematic diagram of a driving circuit of a pixel unit 11 provided in an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the pixel unit 11 includes a photodiode 111, a switch transistor 112 and a storage capacitor 113. Among them, the first electrode of the photodiode 111 is electrically connected to the reference voltage terminal 14 of the sensing panel 1, and the main control board 4 fixedly outputs a reference voltage Vbias of -6V to the reference voltage terminal 14; the second electrode of the photodiode 111 is electrically connected to the first electrode of the switch transistor 112; the second electrode of the switch transistor 112 is electrically connected to one end of the reading line 12; the control electrode of the switch transistor 112 is electrically connected to one end of the scanning line 13; the first electrode plate of the storage capacitor 113 is electrically connected to the first electrode of the photodiode 111, and the first electrode plate of the storage capacitor 113 is electrically connected to the second electrode of the photodiode 111.

[0097] The photodiode 111 is used to convert the optical signal into an electrical signal, recorded as image data, and stored in the storage capacitor 113. When the control electrode of the switch transistor 112 receives a gate drive signal, the first electrode and the second electrode are turned on, and the storage capacitor 113 is discharged at this time, and the image data is transmitted to the reading sub-circuit 21 through the reading line 12. The reading sub-circuit 21 further sends the received image data to the main control board 4.

[0098] The sensing panel 1 in the embodiment of the present disclosure is similar to a large panel formed by splicing two sub-panels. In order to ensure that there is no split screen phenomenon at the boundary between the first reading line 121 and the second reading line 122, in addition to controlling the gate scanning synchronization, its hardware design must also ensure that the electrical characteristics of the left and right sides are consistent, as shown in the following embodiment.

[0099] In some embodiments, Fig. 9 A schematic diagram of the electrical connection relationship of the driving circuit of the flat panel detector provided in the embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the main control board 4 includes a controller 41 and a data transmission line 42. The data transmission line 42 electrically connects the controller 41 and the reading subcircuit 21; the data transmission line 42 is mainly used to transmit image data, that is, the reading subcircuit 21 transmits the received image data to the controller 41.

[0100] Optionally, the data transmission lines 42 include a plurality of lines, each of which is connected to the read sub-circuit 21 in a one-to-one correspondence.

[0101] Optionally, the data transmission line 42 is a differential signal line; the differential signal line includes a group of differential sub-line pairs of equal length. Here, "equal length" includes synchronous routing of the differential sub-line pairs and synchronous layer switching.

[0102] The flat panel detector provided by the embodiment of the present disclosure is applied to high frame rate detection. In this embodiment, the transmitted image data is a high-speed signal, and adopts a differential signal (LVDS) transmission mode and synchronous routing to ensure that the crosstalk signals are offset.

[0103] Optionally, each data transmission line 42 may adopt a serpentine routing layout to ensure that each data transmission line 42 is of equal length, thereby ensuring that each data transmission line 42 has consistent impedance, thereby reducing signal reflection during image data transmission and reducing signal attenuation.

[0104] Optionally, each data transmission line 42 is set to a differential impedance of 100 ohms, thereby reducing signal reflection and signal attenuation during image data transmission.

[0105] Exemplarily, the controller 41 is a Field Programmable Gate Array (FPGA).

[0106] In some embodiments, Fig.10 for Fig. 9 A partial longitudinal diagram of the main control board and the reading circuit board, such as Fig.10 As shown, the flat panel detector also includes an outer frame 10 and a middle frame 9; the reading circuit board 2 is arranged on a side of the middle frame 9 close to the outer frame 10, the sensing panel 1 is arranged on a side of the middle frame 9 away from the reading circuit board 2, and the main control board 4 is arranged on a side of the outer frame 10 close to the reading circuit board 2. Here, the main control board 4 and the reading circuit board 2 are arranged in layers, and the main control board 4 is closer to the outer frame 10 than the reading circuit board 2. When the two are electrically connected, the data transmission line 42 needs to be designed across layers. Specifically, the data transmission line 42 includes an electrically connected first sub-segment 421 and a second sub-segment 422, and the two are in different layers. The first sub-segment 421 and the second sub-segment 422 are bridged by a first connecting via V1, and the first sub-segment 421 is closer to the reading sub-circuit 21 than the second sub-segment 422; one end of the first sub-segment 421 is electrically connected to the reading sub-circuit 21, and one end of the second sub-segment 422 is electrically connected to the controller 41.

[0107] Alternatively, if Fig. 9 As shown, a second connection via V2 is disposed around the first connection via V1, and the second connection via V2 is grounded. Exemplarily, second connection vias V2 are disposed on opposite sides of the differential sub-line pair, and the second connection vias V2 are grounded, thereby absorbing electromagnetic interference when the surrounding signal is transmitted across the first sub-segment 421 and the second sub-segment 422.

[0108] In some embodiments, Fig. 9 and Fig.10As shown, the flat panel detector also includes a first cable 61, one end of which is electrically connected to the data transmission line 42, and also uses a differential signal line, which includes a group of differential sub-line pairs of equal length. The other end of the first cable 61 is electrically connected to the reading sub-circuit 21. The number of first cables 61 is the same as the number of reading sub-circuits 21, and the two are connected one by one. The differential sub-line pairs are made of equal length and change layers at the same time to ensure that the parasitic parameters of the differential cable (first cable 61) are consistent.

[0109] Optionally, the first cable 6 is a flexible FPC cable.

[0110] In some embodiments, Fig.11 Another signal transmission schematic diagram of the flat panel detector provided in the embodiment of the present disclosure is as follows: Fig.11 As shown, the main control board 4 further includes a first clock signal line 43, a second clock signal line 44, a frame start signal line 45 and a configuration signal line 46. One end of the frame start signal line 45 is a start signal terminal STV0, and the other end is electrically connected to the shift register 31.

[0111] The controller 41 is configured to provide a first clock signal to the reading sub-circuit 21 through a first clock signal line 43, and to provide a second clock signal to the shift register 31 through a second clock signal line 44; to provide a frame start signal to the shift register 31 through a frame start signal line 45; and to provide a configuration signal to the reading sub-circuit 21 through a configuration signal line 46.

[0112] The reading subcircuit 21 is configured to respond to the configuration signal, configure parameters to prepare to read the image data; and respond to the first clock signal, output the image data according to the corresponding timing.

[0113] The shift register 31 is configured to provide a gate driving signal to the pixel unit 11 in response to a frame start signal.

[0114] Optionally, the first clock signal line 43 and the second clock signal line 44 are both differential signal lines, routed on the same layer, and exchange holes at the same time to ensure impedance consistency, reduce signal reflection during signal transmission, and reduce signal attenuation.

[0115] Optionally, the flat panel detector further includes a second cable 62 ; two ends of the second cable 62 are electrically connected to the first clock signal line 43 and the reading sub-circuit 21 .

[0116] Optionally, the flat panel detector further includes a third cable 63 ; two ends of the second cable 63 are electrically connected to the second clock signal line 44 and the shift register 31 .

[0117] Optionally, the flat panel detector further includes a fourth cable 64 ; two ends of the fourth cable 64 are electrically connected to the frame start signal line 45 and the shift register 31 .

[0118] Optionally, the flat panel detector further includes a fifth cable 65 ; two ends of the fifth cable 65 are electrically connected to the configuration signal line 46 and the reading sub-circuit 21 .

[0119] Optionally, the second cable 62 and the third cable 63 both use differential signal lines, and the differential signal lines include a group of differential sub-line pairs of equal length.

[0120] The number of first clock signal lines 43 is the same as the number of read subcircuits 21, and the two are connected in one-to-one correspondence. The number of second clock signal lines 44 is the same as the number of shift registers 31, and the two are connected in one-to-one correspondence. The differential sub-line pairs are made equal in length and the layers are changed at the same time to ensure that the parasitic parameters of the differential cables are consistent.

[0121] In some embodiments, the data transmission line 42, the first clock signal line 43 and the second clock signal line 44 are all high-speed buses, using differential signal (LVDS) synchronous transmission to eliminate crosstalk signals. The start signal line 45 and the configuration signal line 46 are all low-speed buses, such as a serial peripheral interface (SPI) bus.

[0122] Optionally, the data transmission line 42 and the first clock signal line 43 have the same length and the same impedance, thereby ensuring that the signals are aligned when the image data is transmitted.

[0123] In the present disclosure, the voltage difference of the LVDS signal differential pair is 350 mV, while the SPI signal level is 2.5 V. In order to prevent the SPI signal from interfering with the LVDS signal, the present disclosure sets the high-speed bus and the low-speed bus separately during layout and wiring.

[0124] In some embodiments, Fig.12a A schematic plan view of a reading circuit board 2 provided in an embodiment of the present disclosure, as shown in FIG. Fig.10 and Fig.12a As shown, the reading circuit board 2 also includes a grounding layer 22 arranged on the side of the reading sub-circuit 21 close to the sensing panel 1 and a first grounding terminal 23 arranged on the side of the reading sub-circuit 21 away from the grounding layer 22, and the first grounding terminal 23 is electrically connected to the grounding layer 22; the flat panel detector also includes a first connector 71 arranged on the side of the reading circuit board 2 close to the main control board 4, and the first connector 71 electrically connects the reading sub-circuit 21 and the main control board 4; the shell of the first connector 71 is in direct contact with the first grounding terminal 23.

[0125] The grounding layer 22 is grounded, that is, it transmits a ground signal. The ground signal is a reference signal for the driving circuit of the entire flat panel detector. If there is a difference or waveguide in the ground signal levels of the two sub-panels, it will directly lead to a grayscale difference between the sub-panels. Therefore, the driving circuit of the entire flat panel detector must be fully grounded. In this embodiment, the housing of the first connector 71 is in direct contact with the first ground terminal 23 to ensure that the first connector 71 is fully grounded and the impedance is reduced.

[0126] In some embodiments, Fig.10 and Fig.12a As shown, the flat panel detector further includes an adapter 8; the first connector 71 is electrically connected to the main control board 4 through the adapter 8. Specifically, the reading subcircuit 21 is electrically connected to the first connector 71, the first connector 71 is plugged into the adapter 8, and the adapter 8 is electrically connected to the data transmission line 42 of the main control board 4 through the first cable 6.

[0127] Optionally, the output pad pitch of the adapter 8 is greater than the pad pitch of the first connector 71. For example, the output pad pitch of the adapter 8 is 0.5 mm; the pad pitch of the first connector 71 is 0.3.

[0128] Optionally, the number of output pads of the adapter 8 is less than the number of pads of the first connector 71. The number of output pads of the adapter 8 is 50; the number of pads of the first connector 71 is 53.

[0129] Exemplarily, the number of pads of the reading subcircuit 21 is 53 pins, with a pitch of 0.3 mm, and the corresponding first connector 71 model is FH26J-55S-0.3SHW60. According to previous design experience, the first connector 71 is easily damaged during use, so an adapter 8 is added. The adapter 8 is a conversion FPC, which actually converts the 53 pin / 0.3 mm first connector 71 into a 50 pin / 0.5 mm connector to avoid damage to the first connector 71 during image data transmission at high frame rates, thereby ensuring the stability of image data transmission.

[0130] In some embodiments, Figure 12b A schematic diagram of reading a pad on a circuit board 2 provided in an embodiment of the present disclosure, such as Fig.10 and Figure 12b As shown, the reading circuit board 2 also includes a plurality of first connecting pads 24 and a plurality of second connecting pads 25 arranged on the side of the reading subcircuit 21 away from the ground layer 22, and the second connecting pads 25 are arranged between adjacent first connecting pads 24; the first connecting pads 24 are bound and connected to the first connector 71, and the second connecting pads 25 are electrically connected to the ground layer 22.

[0131] Optionally, a second connection pad 25 is disposed between any adjacent first connection pads 24. Optionally, a second connection pad 25 is sandwiched between every two first connection pads 24.

[0132] In this embodiment, a second connecting pad 25 is added and grounded to absorb electromagnetic interference between adjacent first connecting pads 24 .

[0133] In some embodiments, Fig.10 As shown, the flat panel detector further includes a middle frame 9 disposed on the side of the reading subcircuit 2 close to the sensing panel 1. The reading circuit board 2 further includes a solder resist layer 26 disposed on the side of the grounding layer 22 close to the sensing panel 1; the solder resist layer 26 has an opening 261, the opening 261 exposes the grounding layer 22, and the grounding layer 22 is in direct contact with the middle frame 9.

[0134] Here, the solder resist layer 26 mainly plays the role of insulation and preventing oxidation of metal lines. The solder resist layer 26 is coated on the surface of the ground layer 22 close to the sensing panel 1, and has an opening 261 thereon to expose part of the ground layer 22, and the exposed part of the ground layer 22 is directly in contact with the middle frame 9, thereby reducing the contact impedance of the ground signal.

[0135] In some embodiments, Fig.13 A schematic plan view of a flat panel detector provided in an embodiment of the present disclosure, such as Fig.13 As shown, the reading subcircuit 21, the shift register 31 and the main control board 4 are all fixed on the middle frame 9 through different grounding holes, and the middle frame 9 is grounded.

[0136] Specifically, the reading circuit board 2 further includes a first grounding hole H1, which is used to fix the reading circuit board 2 to the middle frame 9. The gate driving circuit board 3 further includes a second grounding hole H2, which is used to fix the gate driving circuit board 3 to the middle frame 9. The main control board 4 further includes a third grounding hole H3, which is used to fix the main control board 4 to the middle frame 9.

[0137] Optionally, the first grounding hole H1, the second grounding hole H2 and the third grounding hole H3 are all conductive vias and are electrically connected to the grounding layer 22 of the reading circuit board 2, the gate drive circuit board 3 and the main control board 4, thereby connecting the ground of the reading circuit board 2, the gate drive circuit board 3 and the main control board 4 to the middle frame 9, realizing a common ground path between the reading circuit board 2, the gate drive circuit board 3 and the main control board 4, and ensuring the consistency of the ground signal level between each circuit board.

[0138] Here, the number and position of the first grounding hole H1, the second grounding hole H2 and the third grounding hole H3 are not limited. For example, 3 to 8 grounding holes can be set on each circuit board (reading circuit board 2, gate drive circuit board 3 and main control board 4), and are set at the four corners or edges of the circuit board.

[0139] Optionally, the material of the middle frame 9 may be aluminum alloy, ensuring that the impedance between the middle frame 9 and each circuit board is less than or equal to 10 mΩ.

[0140] In some embodiments, Fig.14 A schematic diagram of power supply routing provided in an embodiment of the present disclosure, such as Fig.14 As shown, the main control board 4 also includes a power supply 47; the flat panel detector also includes a second connector 72 and a third connector 73 arranged on the side of the reading circuit board 2 close to the main control board 4. The second connector 72 and the third connector 73 are electrically connected to different reading circuits 20, namely the first reading circuit 201 and the second reading circuit 202. The controller 41 of the main control board 4 controls the power supply 47 to output power signals to the first reading circuit 201 and the second reading circuit 202 at the same time to supply power to the reading circuit 20. Specifically, the power supply 47 is electrically connected to the second connector 72 through the first power line 481, and is used to supply power to each reading sub-circuit 21 in one reading circuit 20 (the first reading circuit 201) electrically connected to the second connector 72; the power supply 47 is electrically connected to the third connector 73 through the second power line 482, and is used to supply power to each reading sub-circuit 21 in another reading circuit 20 (the second reading circuit 202) electrically connected to the third connector 73. The resistance of the first power line 481 and the second power line 482 are the same.

[0141] Here, the first power line 481 and the second power line 482 are connected through the power supply on the main control board 4. While the two are connected to the reading sub-circuit 21 at the shortest possible distance, a serpentine routing method can be used to ensure that the two have the same length and consistent impedance.

[0142] In this embodiment, the first reading circuit 201 and the second reading circuit 202 adopt a homologous design to ensure that the characteristics of the power supply signal are consistent, thereby ensuring that the grayscale is consistent. At the same time, the resistance of the first power line 481 and the second power line 482 are the same, that is, the impedance is consistent, thereby ensuring that the power supply signal reaching the first reading circuit 201 and the second reading circuit 202 is consistent, thereby ensuring that the electrical characteristics of the first reading circuit 201 and the second reading circuit 202 are consistent.

[0143] It should be noted that in the embodiment of the present disclosure, the first reading circuit 201 and the second reading circuit 202 are integrated on the same reading circuit board 2, which is beneficial to ensure the consistency of electrical characteristics.

[0144] In some embodiments, Fig.15 The main control board provided in the embodiment of the present disclosure is a partial schematic diagram of the shift register power supply area, such as Fig.15As shown, the main control board 4 also includes a second ground terminal 49, a first power signal terminal 410 and a second power signal terminal 411. The second ground terminal 49 is arranged between adjacent first power signal terminals 410 and second power signal terminals 411; the first power signal terminal 410 and the second power signal terminal 411 are both electrically connected to the shift register 31, and are used to provide power signals of different voltages to the shift register 31.

[0145] Optionally, the first power signal terminal 410 provides a first power signal, such as a high level signal VGH, which is 15V, to the shift register 31 through the third power line 103; the second power signal terminal 411 provides a second power signal, such as a low level signal VGL, which is -8V, to the shift register 31 through the fourth power line 104. The shift register 31 is controlled by the second clock signal and the frame start signal, and the gate drive signal output by the shift register 31 is a high level signal VGH or a low level signal VGL to control the on and off of the switch transistor 112 in the pixel unit 11.

[0146] In this embodiment, electromagnetic interference is absorbed by adding a second ground terminal 49 between the first power signal terminal 410 and the second power signal terminal 411 .

[0147] In some embodiments, Fig.16 A schematic plan view of a flat panel detector provided in an embodiment of the present disclosure, Fig.17 A schematic diagram of the longitudinal distribution of each circuit board of the flat panel detector provided by the embodiment of the present disclosure, such as Fig.16 and Fig.17 As shown, the flat panel detector also includes an outer frame 10, a middle frame 9, a first heat-conducting structure 1011 and a second heat-conducting structure 1012; the reading circuit board 2 is arranged on a side of the middle frame 9 close to the outer frame 10, the sensing panel 1 is arranged on a side of the middle frame 9 away from the reading circuit board 2, and the main control board 4 is arranged on a side of the outer frame 10 close to the reading circuit board 2.

[0148] The first heat-conducting structure 1011 is arranged between the reading sub-circuit 21 and the middle frame 9; the two surfaces of the first heat-conducting structure 1011 that are arranged opposite to each other in the third direction Z are in direct contact with the reading sub-circuit 21 and the middle frame 9 respectively, and are used to introduce the heat on the reading sub-circuit 21 into the middle frame 9 to achieve rapid heat dissipation of the reading sub-circuit 21.

[0149] The second heat-conducting structure 1012 is arranged between the main control board 4 and the outer frame 10; the two surfaces of the second heat-conducting structure 1012 that are relatively arranged in the third direction Z are in direct contact with the main control board 4 and the outer frame 10 respectively, and are used to introduce the heat on the main control board 4 into the outer frame 10 to achieve rapid heat dissipation of the main control board 4.

[0150] Optionally, the first heat-conducting structure 1011 is a heat-conducting silicone. Optionally, the first heat-conducting structure 1011 is a conductive silicone, which can realize the electrical connection between the ground layer 22 and the middle frame 96 through the first heat-conducting structure 1011 located in the opening 261. The solder resist layer 26 is relatively thin, and FIG17 is only a schematic diagram for easy viewing, and is not used as a size limitation of the structure shown in the present disclosure.

[0151] Optionally, the second heat-conducting structure 1012 is a metal heat-conducting strip, and its material can be alloy copper or the like.

[0152] It should be noted that when the driving circuit of the flat panel detector is working, the FPGA on the main control board 4 and the ROIC on the reading circuit board 2 are the main heat sources. The sensing panel 1 is a semiconductor device and is easily affected by temperature when collecting image data. Therefore, in this embodiment, the heat of the reading circuit board 2 is quickly introduced into the middle frame 9 through the first heat conducting structure 1011, and the heat on the main control board 4 is quickly introduced into the outer frame 10 through the second heat conducting structure 1012, so as to avoid the influence of excessive temperature on the collected image data.

[0153] like Fig.17 As shown, the circuit board of the flat panel detector is a double-layer layout in the third direction Z, the main control board 4 and the gate drive circuit board 3 are located in the upper layer, and the reading circuit board 2 is located in the lower layer, so that the gate drive circuit board 3 and the reading circuit board 2 are staggered in space to avoid interference, and the main control board 4 and the reading circuit board 2 are staggered in layout, which can also ensure that the area of ​​the main control board 4 is large enough to provide sufficient space for the layout of components. Convenient design.

[0154] In some embodiments, the main control board 4 has low-voltage circuits and high-voltage circuits, and the low-voltage circuits and high-voltage circuits are separately arranged in the circuit layout. Among them, the low-voltage circuit includes but is not limited to the controller 41 (FPGA, whose operating voltage is 1V), the memory (DDR, whose operating voltage is 1.5V), the signal circuit (operating voltage is 2.5V) for the controller 41 to interact with the reading sub-circuit 21 (ROIC), and the analog-to-digital conversion module (A / D module, whose operating voltage is 1V) on the main control board 4. The high-voltage circuit includes but is not limited to the power supply, and the first power line 481 (reference voltage -6V), the second power line 482 (reference voltage -6V), the third power line (VGH = 15V), the fourth power line (VGL = -8V), etc. derived from it. The operating voltage of the circuit is relatively low (low-voltage circuit is below 5V).

[0155] In some embodiments, the board material of the main control board 4, the reading circuit board 2 and the gate driving circuit board 3 can be selected from high-speed boards with a small dielectric constant, such as TU872, which is beneficial to improving the signal transmission rate.

[0156] The above is a complete description of the flat panel detector provided in the embodiment of the present disclosure.

[0157] In addition, an embodiment of the present disclosure also provides an exposure control system.

[0158] It should be noted that the exposure method of high frame rate dynamic detectors is different from that of traditional low speed static detectors. Fig.18 Schematic diagram of the exposure control system of the low-speed static detector in the related art. The exposure control process of the low-speed static detector is as follows: as shown in 18, the control host 181 is configured to send a preparation request to the hand brake control box 182 according to the user's front-end operation instruction; the hand brake control box 182 is configured to parse the information in the preparation request and send it to the high-voltage generator control box 183; the high-voltage generator control box 183 is configured to control the static tube high-voltage generator to enter the preparation state according to the information in the preparation request. The control host 181 is also configured to determine whether the flat panel detector 186 is normal through the Gigabit network, and when receiving the feedback signal of the flat panel detector 186, determine that the flat panel detector 186 is normal, and further send an exposure request to the hand switch control box 182, and the hand switch control box 182 is configured to parse the information in the exposure request and send it to the high voltage generator control box 183; the high voltage generator control box 183 is configured to control the static tube high voltage generator 184 to enter the exposure state according to the information in the exposure request, and the static tube high voltage generator 184 is illuminated by the light source 185. At the same time, the control host 181 sends a picture acquisition request to the flat panel detector 186 after software delay; the flat panel detector 186 collects image data in response to the picture acquisition request, and transmits the image data back through the Gigabit network.

[0159] The static tube high voltage generator used with the above-mentioned traditional static detector requires the operation of request-prepare-exposure for each exposure, and the synchronization requirements between the static tube high voltage generator and the flat-panel detector are not high. During automatic control, the control host serves as the main control core, and all operations are automatically completed by the control host.

[0160] Due to the increase in frame rate, the high-speed dynamic detector needs to continuously and quickly expose the tube to meet the requirements of image acquisition. During the exposure control process of the low-speed static detector, on the one hand, the control host performs a large number of operations, and when the computing resources are insufficiently allocated, the exposure request will be delayed; on the other hand, the control host will initiate an exposure request, which will first pass through the high-voltage generator control box, and then the high-voltage generator control box will control the static tube high-voltage generator to enter the exposure state, so there will be a delay when the static tube high-voltage generator receives the exposure instruction.

[0161] Fig.19 A schematic diagram of an exposure control system provided by an embodiment of the present disclosure is shown in FIG. Fig.19As shown, the flat panel detector 100 including the above-mentioned embodiments and their combinations, a high voltage generator 200, a host 300 and a light source 400. The flat panel detector 100 and the light source 400 are in the same darkroom.

[0162] The host 300 is configured to send an image acquisition instruction to the main control board 4 of the flat panel detector 100 and send exposure configuration information to the high voltage generator 200. The exposure configuration information includes parameter information for instructing the high voltage generator 200 how to expose, including but not limited to how many seconds of light to emit, how many volts of voltage to emit, etc.

[0163] The main control board 4 is configured to send a preparation signal to the high voltage generator 200 in response to an image acquisition instruction; and send an exposure control signal to the high voltage generator 200 in response to receiving a feedback signal sent by the high voltage generator 200.

[0164] The high voltage generator 200 is configured to respond to the preparation signal, configure the pre-exposure parameters according to the exposure configuration information, and generate a feedback signal to send to the main control board 4 when the configuration is completed; and, in response to receiving the exposure control signal, control the light source 400 to illuminate.

[0165] Compared with the traditional exposure control system, the exposure control system provided by the embodiment of the present disclosure adopts the method of direct connection and communication between the flat panel detector 100 (main control board 4) and the high voltage generator 200, eliminates the host 300 as the control core, reduces the transmission delay of the exposure control signal, and enables the high voltage generator 200 to be exposed quickly. At the same time, there is only a small amount of interaction between the flat panel detector 100 and the high voltage generator 200. The parameter configuration of the high voltage generator 200 before exposure is still controlled by the host 300. The host 300 can synchronously send image acquisition instructions to the main control board 4 of the flat panel detector 100 and send exposure configuration information to the high voltage generator 200. At the same time, the high voltage generator 200 can synchronously receive the exposure configuration information and the preparation signal, thereby saving preparation time and further improving the exposure speed.

[0166] In some embodiments, Figure 20a to Figure 20c A circuit diagram between the high voltage generator 200 and the flat panel detector 100 provided in an embodiment of the present disclosure is shown in FIG. Figure 20a to Figure 20c As shown, the exposure control system further includes a photocoupler 500, and the main control board 4 is electrically connected to the high voltage generator 200 via the photocoupler 500. Exemplarily, the photocoupler 500 includes a light emitting diode 501 and a photosensitive diode 502, the light emitting diode 501 emits light, the photosensitive diode 502 is turned on, and a preparation signal or an exposure control signal is sent to the high voltage generator 200, or the high voltage generator 200 sends a feedback signal to the main control board 4.

[0167] Specifically, the main control board 4 includes a first interface M1, a second interface M2 and a third interface M3, and a first photoelectric coupler 51 electrically connected to the first interface M1, a second photoelectric coupler 52 electrically connected to the second interface M2, and a third photoelectric coupler 53 electrically connected to the third interface M3. The high voltage generator 200 includes a fourth interface M4, a fifth interface M5 and a sixth interface M6, and a fourth photoelectric coupler 54 electrically connected to the fourth interface M4, a fifth photoelectric coupler 55 electrically connected to the fifth interface M4, and a sixth photoelectric coupler 56 electrically connected to the sixth interface M6. The first photoelectric coupler 51 is electrically connected to the fourth photoelectric coupler 54, the second photoelectric coupler 52 is electrically connected to the fifth photoelectric coupler 55, and the third photoelectric coupler 53 is electrically connected to the sixth photoelectric coupler 56.

[0168] The main control board 4 sends a preparation signal through the first photocoupler 51, and the high voltage generator 200 receives the preparation signal through the fourth photocoupler 54. The high voltage generator 200 sends a feedback signal through the fifth photocoupler 55, and the main control board 4 receives the feedback signal through the second photocoupler 52. The main control board 4 sends an exposure control signal through the third photocoupler 500, and the high voltage generator 200 receives the exposure control signal through the fourth photocoupler 500.

[0169] In this embodiment, the photoelectric coupler 500 is used for isolation and information exchange between the high voltage generator 200 and the flat panel detector 100, so as to avoid the problem of the output signal of either the high voltage generator 200 or the flat panel detector 100 affecting the other device. For example, when the line of the exposure control signal output by the flat panel detector 100 is short-circuited, or is broken, or is short-connected to a higher voltage, the photoelectric coupler 500 will only transmit the on or off signal, and the high voltage signal will not be transmitted to the high voltage generator 200 through the connecting cable, thereby ensuring the safety of each device.

[0170] In some embodiments, the high voltage generator 200 is a tube high voltage generator. The light source 400 is a tube, that is, a cathode ray diode. The tube high voltage generator controls the light source 400 to illuminate, that is, controls the process of the tube generating X-rays.

[0171] In some embodiments, in addition to being controlled by the flat panel detector 100 to automatically perform the exposure process, the high voltage generator 200 can also be manually controlled by the user to implement the exposure process. Fig.21 A schematic diagram of another exposure control system provided by an embodiment of the present disclosure, such as Fig.21 As shown, the exposure control system includes a console 600, and the host 300 is a part of the console 600; in addition, the console 600 also includes a high-voltage generator control box 700 and a high-voltage generator built-in control hand brake 800.

[0172] like Fig.21 As shown, the high-voltage generator has a built-in control hand switch 800, which is configured to send a manual exposure instruction to the high-voltage generator control box 700 in response to the user's opening operation; the high-voltage generator control box 700 is configured to control the high-voltage generator 200 to enter an exposure state in response to the manual exposure instruction, so as to control the high-voltage generator 200 to illuminate through the light source 400.

[0173] In some embodiments, Fig.21 As shown, the high voltage generator control box 700 is also configured to control and adjust the exposure parameters of the high voltage generator 200 in response to the user's parameter adjustment operation, including but not limited to how many seconds of light to emit, how many volts of voltage to emit, etc.

[0174] In addition, the present disclosure also provides an X-ray detection system. Fig. 22 A schematic diagram of an X-ray detection system provided in an embodiment of the present disclosure, such as Fig. 22 As shown, the X-ray detection system includes an exposure control system as described in any of the above embodiments and combinations thereof, and a display panel 900. The host 300 of the exposure control system is configured to receive the bright field image sent by the main control board 4 and send it to the display panel; the display panel 900 is configured to display the bright field image.

[0175] In addition, the embodiment of the present disclosure also provides an exposure control method, which is applied to the above-mentioned exposure control system. The exposure control system includes a flat panel detector, a high voltage generator, a host and a light source.

[0176] The host sends image acquisition instructions to the main control board of the flat panel detector and sends exposure configuration information to the high voltage generator.

[0177] The main control board sends a preparation signal to the high voltage generator in response to the image acquisition instruction.

[0178] The high voltage generator responds to the preparation signal, performs pre-exposure parameter configuration according to the exposure configuration information, and generates a feedback signal to send to the main control board when the configuration is completed.

[0179] In response to receiving the feedback signal sent by the high voltage generator, the main control board sends an exposure control signal to the high voltage generator.

[0180] The high voltage generator controls the light source to illuminate in response to receiving the exposure control signal.

[0181] Those skilled in the art can understand that in the above method of the specific implementation, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic. The exposure control method provided in the embodiment of the present disclosure corresponds to the above exposure control system. The principles of solving technical problems of the two are similar. Therefore, the implementation of the method can refer to the implementation of the system, and the repeated parts will not be repeated.

[0182] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A flat panel detector, comprising a sensing panel, a reading circuit board, a gate driving circuit board and a main control board; the main control board comprises a start signal terminal; The sensing panel includes a plurality of pixel units, a plurality of readout lines extending along a first direction, and a plurality of scan lines extending along a second direction; the pixel units are electrically connected to one of the scan lines and one of the readout lines; the plurality of readout lines are divided into a plurality of readout line groups arranged side by side in the second direction, each of the readout line groups includes two readout lines arranged side by side and spaced apart in the first direction; The readout circuit board comprises two readout circuits, which are respectively arranged on two sides of the sensing panel that are arranged opposite to each other along the first direction; the readout circuit comprises a plurality of readout sub-circuits arranged side by side along the second direction, and the readout sub-circuits in the readout circuits on different sides are arranged one by one correspondingly; the two readout sub-circuits arranged correspondingly are respectively electrically connected to different readout lines in a group of the readout line groups; The gate driving circuit board comprises a plurality of shift registers arranged side by side along a first direction, and the shift registers are connected to the scan lines in a one-to-one correspondence; The two sides of the gate driving circuit board that are relatively arranged along the first direction are recorded as the first side and the second side. A part of the shift registers in the direction from the target center of the gate driving circuit board to the first side are cascaded in sequence, and another part of the shift registers in the direction from the target center to the second side are cascaded in sequence. The first shift register cascaded on different sides is electrically connected to the start signal terminal.

2. The flat panel detector according to claim 1, wherein: The gate driving circuit includes N shift registers; When N is an even number greater than or equal to 2, the N / 2th shift register and the N / 2+1th shift register are both electrically connected to the start signal terminal; the N / 2th shift register is sequentially cascaded to the first gate drive chip; the N / 2+1th shift register is sequentially cascaded to the Nth shift register; When N is an odd number greater than 1, the (N+1) / 2th shift register is electrically connected to the start signal terminal, the output terminal of the (N+1) / 2th shift register is electrically connected to the input terminal of the (N+1) / 2-1th shift register and the input terminal of the (N+1) / 2+1th shift register; the (N+1) / 2th shift register is cascaded to the first gate drive chip in sequence; The (N+1) / 2th shift register to the Nth shift register are cascaded in sequence.

3. The flat panel detector according to claim 1, wherein: The shift register is configured to provide a gate drive signal to the pixel unit in response to receiving a frame start signal sent by the start signal terminal; The pixel unit is configured to collect image data of the object under test in response to the gate drive signal transmitted by the scanning line; The reading subcircuit is configured to receive the image data transmitted by the reading line and send it to the main control board; The main control board is configured to convert the image data into a bright field image and output it.

4. The flat panel detector according to claim 3, wherein: The main control board includes a controller and a data transmission line; the data transmission line electrically connects the controller and the reading sub-circuit; the data transmission line is used to transmit the image data; The data transmission line is a differential signal line; the differential signal line includes a group of differential sub-line pairs with equal lengths.

5. The flat panel detector according to claim 4, wherein: The flat panel detector further comprises an outer frame and a middle frame; the reading circuit board is arranged on a side of the middle frame close to the outer frame, the sensing panel is arranged on a side of the middle frame away from the reading circuit board, and the main control board is arranged on a side of the outer frame close to the reading circuit board; The data transmission line comprises a first sub-segment and a second sub-segment which are electrically connected and are in different layers. The first sub-segment and the second sub-segment are bridged by a first connecting via. The first sub-segment is closer to the reading sub-circuit than the second sub-segment. One end of the first sub-segment is electrically connected to the reading sub-circuit, and one end of the second sub-segment is electrically connected to the controller. A second connection via is disposed around the first connection via, and the second connection via is grounded.

6. The flat panel detector according to claim 1, wherein: The readout circuit board further comprises a grounding layer arranged on a side of the readout subcircuit close to the sensing panel and a first grounding terminal arranged on a side of the readout subcircuit away from the grounding layer, wherein the first grounding terminal is electrically connected to the grounding layer; the flat panel detector further comprises a first connector arranged on a side of the readout circuit board close to the main control board, wherein the first connector electrically connects the readout subcircuit and the main control board; The housing of the first connector is in direct contact with the first ground terminal.

7. The flat panel detector according to claim 6, wherein: The flat panel detector further includes an adapter; the first connector is electrically connected to the main control board through the adapter; and the spacing between output pads of the adapter is greater than the spacing between pads of the first connector.

8. The flat panel detector according to claim 6, wherein: The reading circuit board also includes a plurality of first connecting pads and a plurality of second connecting pads arranged on the side of the reading subcircuit away from the ground layer, and the second connecting pads are arranged between adjacent first connecting pads; the first connecting pads are bound and connected to the first connector, and the second connecting pads are electrically connected to the ground layer.

9. The flat panel detector according to claim 6, wherein: The flat panel detector further includes a middle frame arranged on a side of the reading subcircuit close to the sensing panel; The reading circuit board also includes a solder resist layer arranged on a side of the ground layer close to the sensing panel; the solder resist layer has an opening, the opening exposes the ground layer, the ground layer is in direct contact with the middle frame, and the middle frame is grounded.

10. The flat panel detector according to claim 1, wherein: The flat panel detector further comprises an outer frame and a middle frame; the reading circuit board is arranged on a side of the middle frame close to the outer frame, the sensing panel is arranged on a side of the middle frame away from the reading circuit board, and the main control board is arranged on a side of the outer frame close to the reading circuit board; The reading subcircuit, the shift register and the main control board are all fixed on the middle frame through different grounding holes, and the middle frame is grounded.

11. The flat panel detector according to claim 1, wherein: The main control board includes a power supply; the flat panel detector also includes a second connector and a third connector arranged on a side of the reading circuit board close to the main control board, and the second connector and the third connector are electrically connected to different reading circuits; The power supply is electrically connected to the second connector via a first power line, and is used to supply power to each of the read sub-circuits in one of the read circuits electrically connected to the second connector; the power supply is electrically connected to the third connector via a second power line, and is used to supply power to each of the read sub-circuits in another of the read circuits electrically connected to the third connector; The first power line and the second power line have the same resistance.

12. The flat panel detector according to claim 1, wherein: The main control board further includes a second ground terminal, a first power signal terminal and a second power signal terminal, wherein the second ground terminal is arranged between the adjacent first power signal terminal and the second power signal terminal; The first power signal terminal and the second power signal terminal are both electrically connected to the shift register and are used to provide power signals with different voltages to the shift register.

13. The flat panel detector according to claim 1, wherein: The flat panel detector also includes an outer frame, a middle frame, a first heat-conducting structure and a second heat-conducting structure; The reading circuit board is arranged on a side of the middle frame close to the outer frame, the sensing panel is arranged on a side of the middle frame away from the reading circuit board, and the main control board is arranged on a side of the outer frame close to the reading circuit board; The first heat-conducting structure is arranged between the reading subcircuit and the middle frame; and the second heat-conducting structure is arranged between the main control board and the outer frame.

14. An exposure control system, comprising a flat panel detector according to any one of claims 1 to 13, a high voltage generator, a host and a light source; The host is configured to send an image acquisition instruction to the main control board of the flat panel detector; sending exposure configuration information to the high voltage generator; The main control board is configured to send a preparation signal to the high voltage generator in response to the image acquisition instruction; and, in response to receiving a feedback signal sent by the high voltage generator, sending an exposure control signal to the high voltage generator; The high voltage generator is configured to respond to the preparation signal, perform pre-exposure parameter configuration according to the exposure configuration information, and generate a feedback signal to send to the main control board when the configuration is completed; And, in response to receiving the exposure control signal, controlling the light source to illuminate.

15. The exposure control system according to claim 14, wherein: The exposure control system further includes a photoelectric coupler, and the main control board is electrically connected to the high voltage generator via the photoelectric coupler.

16. An X-ray detection system, comprising the image exposure control system according to claim 14 or 15, and a display panel; The host is configured to receive the bright field image sent by the main control board and send it to the display panel; The display panel is configured to display the bright field image.

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