Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a substrate; the N + 1 data line groups are located on the substrate, and N is an integer greater than or equal to 1; the plurality of pixels are arranged in the row direction and the column direction, and one data line group is located in one column of pixels; each data line group comprises a first data line and a second data line, pixels located in odd-numbered rows and odd-numbered columns are connected with the first data line, and pixels located in odd-numbered rows and even-numbered columns are connected with the second data line; the pixels in the even-numbered rows and odd-numbered columns are connected with the second data lines, and the pixels in the even-numbered rows and even-numbered columns are connected with the first data lines; the first data line and the second data line are opposite in polarity; each pixel comprises a first pixel electrode, each first pixel electrode comprises a first longitudinal trunk and a second longitudinal trunk which extend in the column direction, the first longitudinal trunks and the second longitudinal trunks are arranged in a staggered mode, the adjacent first pixel electrodes are arranged in a mirroring mode in the row direction, and the adjacent first pixel electrodes are arranged in a mirroring mode in the column direction.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In the related art, there are generally two options for the arrangement of the array substrate. The first option is to set a shielding electrode in the array substrate to prevent the liquid crystal molecules from being affected by the data line and the gate electric field. The second option is to remove the shielding electrode and move the pixel electrode away from the data line to increase the aperture ratio. However, no matter which of the above methods is adopted, there are certain problems:

[0003] The first option is to set a shielding electrode, which can effectively prevent the liquid crystal molecules from being deflected by the data line, but the existence of the shielding electrode will reduce the aperture ratio of the pixel;

[0004] The second option, although eliminating the shielding electrode and moving the pixel electrode away from the data line can increase the aperture ratio, the data line in the array substrate may affect the deflection of the liquid crystal molecules, resulting in inconsistent brightness in the picture displayed on the array substrate, and even dark lines in some areas. Summary of the invention

[0005] In view of this, the present application provides an array substrate and a display panel, which are used to improve the problem that the array substrate sacrifices the aperture ratio in order to solve the dark pattern problem.

[0006] The technical solution adopted by this application to solve the above technical problems is:

[0007] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0008] substrate;

[0009] N+1 data line groups, the data line groups are located on the substrate, and N is an integer greater than or equal to 1;

[0010] A plurality of pixels, the pixels are arranged along a row direction and a column direction, and a data line group is located in a column of the pixels;

[0011] Wherein, the data line group comprises a first data line and a second data line, the pixels located in odd rows and odd columns are connected to the first data line, and the pixels located in odd rows and even columns are connected to the second data line; the pixels located in even rows and odd columns are connected to the second data line, and the pixels located in even rows and even columns are connected to the first data line; the first data line and the second data line have opposite polarities;

[0012] The pixel includes a first pixel electrode, the first pixel electrode includes a first longitudinal trunk and a second longitudinal trunk extending along the column direction, and the first longitudinal trunk and the second longitudinal trunk are staggered, and along the row direction, adjacent first pixel electrodes are mirror-arranged, and along the column direction, adjacent first pixel electrodes are mirror-arranged.

[0013] In some embodiments of the present application, the first longitudinal trunk overlaps with at least a portion of the first data line, and the second longitudinal trunk overlaps with at least a portion of the second data line.

[0014] In some embodiments of the present application, the first data line in the Nth data line group and the first data line in the N+Mth data line group are connected in parallel, and M is an integer multiple of 3.

[0015] In some embodiments of the present application, the first pixel electrode also includes a first horizontal trunk and a plurality of first branches, the first longitudinal trunk and the second longitudinal trunk are respectively connected to both sides of the first horizontal trunk in the column direction, and the plurality of first branches connect the first longitudinal trunk, the second longitudinal trunk and the first horizontal trunk.

[0016] In some embodiments of the present application, the pixel further includes a second pixel electrode, the first pixel electrode and the second pixel electrode are alternately arranged along the column direction, the second pixel electrode includes a third longitudinal trunk, a fourth longitudinal trunk, a second transverse trunk and a plurality of second branches, the third longitudinal trunk and the fourth longitudinal trunk are respectively arranged on both sides of the second transverse trunk in the column direction, and the plurality of second branches connect the second transverse trunk, the third longitudinal trunk and the fourth longitudinal trunk;

[0017] Wherein, along the row direction, adjacent second pixel electrodes are arranged in a mirror image, and along the column direction, adjacent second pixel electrodes are arranged in a mirror image.

[0018] In some embodiments of the present application, the array substrate further includes a plurality of scan lines, a first thin film transistor, a second thin film transistor and a voltage dividing line; wherein

[0019] The scan lines extend along the row direction;

[0020] The first thin film transistor and the second thin film transistor are located between the first pixel electrode and the second pixel electrode, the source of the first thin film transistor is connected to the corresponding first data line or the second data line, the first pixel electrode is connected to the drain of the first thin film transistor, and the second pixel electrode is connected to the drain of the second thin film transistor;

[0021] The voltage dividing line extends along the column direction and is located between two adjacent columns of pixels. The voltage dividing line is connected to the source of the second thin film transistor. The voltage dividing line is arranged in the same layer as the data line group.

[0022] In some embodiments of the present application, two adjacent columns of pixels share one voltage dividing line.

[0023] In some embodiments of the present application, the array substrate further includes a third thin film transistor, a source of the third thin film transistor is connected to the source of the first thin film transistor, and a drain of the third thin film transistor is connected to the drain of the second thin film transistor.

[0024] In some embodiments of the present application, the first thin film transistor and the third thin film transistor are located on the same side of the data line group.

[0025] In some embodiments of the present application, the first thin film transistor and the third thin film transistor are located at opposite sides of the first data line or the second data line of the corresponding data line group.

[0026] In a second aspect, an embodiment of the present application provides a display panel, wherein the display panel comprises the array substrate as described in the first aspect, and

[0027] An opposing substrate, located at one side of the array substrate;

[0028] A liquid crystal layer is disposed between the array substrate and the counter substrate.

[0029] In summary, due to the adoption of the above technical solution, this application has at least the following beneficial effects:

[0030] The embodiment of the present application provides an array substrate and a display panel, by connecting pixels located in odd rows and odd columns to a first data line, connecting pixels located in odd rows and even columns to a second data line; connecting pixels located in even rows and odd columns to a second data line, and connecting pixels located in even rows and even columns to a first data line, and staggering the first longitudinal trunk and the second longitudinal trunk so that a part of the first data line will be blocked by the first longitudinal trunk, and a part of the second data line will be blocked by the second longitudinal trunk, thereby achieving the purpose of increasing the pixel aperture ratio. Furthermore, by making the polarities of the first data line and the second data line opposite, and adjacent first pixel electrodes are arranged in a mirror image along the row direction, and adjacent first pixel electrodes are arranged in a mirror image along the column direction, so as to avoid the data lines affecting the deflection of liquid crystal molecules, it is beneficial to improve the brightness uniformity of the array substrate. In detail, firstly, by setting the first data line and the second data line in the data line group, and connecting the pixels located in odd rows and odd columns to the first data line, and connecting the pixels located in odd rows and even columns to the second data line; connecting the pixels located in even rows and odd columns to the second data line, and connecting the pixels located in even rows and even columns to the first data line, and the first data line and the second data line have opposite polarities, so as to balance the coupling caused by the positive and negative frames; then, by making the first pixel electrode include the first longitudinal trunk and the second longitudinal trunk, the first longitudinal trunk and the second longitudinal trunk are staggered, so that a part of the first data line can be blocked by the first longitudinal trunk, and a part of the second data line can be blocked by the second longitudinal trunk, so that the longitudinal trunk can play the role of shielding the signal, thereby increasing the aperture ratio. In addition, by mirroring the adjacent first pixel electrodes in the row direction, and mirroring the adjacent first pixel electrodes in the column direction, the mirrored and adjacent pixels can balance the influence of the data lines with opposite polarities on the liquid crystal molecules, realize the compensation of the brightness difference of adjacent pixels, and improve the brightness uniformity of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of an array substrate provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of a pixel electrode in an array substrate provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of the connection between a thin film transistor and a data line group in an array substrate provided by an embodiment of the present application;

[0034] Figure 4 A schematic diagram of the connection between a gate layer and a common electrode in an array substrate provided in an embodiment of the present application;

[0035] Figure 5A schematic diagram of a pixel electrode in another array substrate provided in an embodiment of the present application;

[0036] Figure 6 A schematic diagram of connecting a thin film transistor and a data line group in another array substrate provided by an embodiment of the present application;

[0037] Figure 7 A schematic diagram of the connection between a gate layer and a common electrode in another array substrate provided in an embodiment of the present application;

[0038] Figure 8 A schematic diagram of a pixel unit provided in an embodiment of the present application.

[0039] Description of reference numerals:

[0040] 100, array substrate; 110, pixel; 111, first pixel electrode; 1111, first longitudinal trunk; 1112, second longitudinal trunk; 1113, first transverse trunk; 1114, first branch; 1115, display domain area; 112, second pixel electrode; 1121, third longitudinal trunk; 1122, fourth longitudinal trunk; 1123, second transverse trunk; 1124, second branch; 113, gate layer; 1131 , a first gate electrode; 1132, a second gate electrode; 114, a common electrode; 1141, a longitudinal electrode line; 11411, a first segment line; 11412, a second segment line; 1142, a transverse electrode line; 115, a gate region; 120, a data line group; 121, a first data line; 122, a second data line; 130, a first thin film transistor; 140, a second thin film transistor; 150, a third thin film transistor; 160, a voltage divider line. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0042] In the description of this application, it should be understood that the words "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0043] In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0044] See also Figures 1 to 7, an embodiment of the present application provides an array substrate 100, the array substrate 100 comprising:

[0045] substrate;

[0046] N+1 data line groups 120, the data line groups 120 are located on the substrate, and N is an integer greater than or equal to 1;

[0047] A plurality of pixels 110 are arranged along row directions and column directions, and a data line group 120 is located in a column of pixels 110;

[0048] A data line group 120 includes a first data line 121 and a second data line 122. The pixels 110 located in odd rows and odd columns are connected to the first data line 121, and the pixels 110 located in odd rows and even columns are connected to the second data line 122; the pixels 110 located in even rows and odd columns are connected to the second data line 122, and the pixels 110 located in even rows and even columns are connected to the first data line 121; the first data line 121 and the second data line 122 have opposite polarities;

[0049] A pixel 110 includes a first pixel electrode, which includes a first longitudinal trunk 1111 and a second longitudinal trunk 1112 extending along the column direction, and the first longitudinal trunk 1111 and the second longitudinal trunk 1112 are staggered. Along the row direction, adjacent first pixel electrodes are mirror-arranged, and along the column direction, adjacent first pixel electrodes are mirror-arranged.

[0050] Two data lines with opposite polarities are arranged in different layers from the pixel 110 electrodes, and the two data lines are arranged to overlap at least partially with the longitudinal trunk. The two data lines carry opposite electrical signals respectively, and are used to drive the pixels 110. In addition, the plurality of pixels 110 are arranged in row and column directions, and the adjacent pixels 110 are arranged in mirror images in the row direction, and the adjacent pixels 110 are also arranged in mirror images in the column direction, so as to balance the electric field and signal transmission, and reduce interference and brightness difference.

[0051] The technical solution provided by the present application connects the pixels 110 located in odd rows and odd columns to the first data line 121, and the pixels 110 located in odd rows and even columns to the second data line 122; the pixels 110 located in even rows and odd columns to the second data line 122, and the pixels 110 located in even rows and even columns to the first data line 121, and the first longitudinal trunk 1111 and the second longitudinal trunk 1112 are staggered, so that a part of the first data line 121 is blocked by the first longitudinal trunk 1111, and a part of the second data line 122 is blocked by the second longitudinal trunk 1112, thereby achieving the purpose of increasing the aperture ratio of the pixels 110. In addition, the polarities of the first data line 121 and the second data line 122 are opposite, and the adjacent first pixel electrodes are mirrored in the row direction and in the column direction, so as to avoid the data lines affecting the deflection of the liquid crystal molecules, which is conducive to improving the brightness uniformity of the array substrate 100. Specifically, first, a first data line 121 and a second data line 122 are arranged in the data line group 120, and the pixels 110 located in odd rows and odd columns are connected to the first data line 121, and the pixels 110 located in odd rows and even columns are connected to the second data line 122; the pixels 110 located in even rows and odd columns are connected to the second data line 122, and the pixels 110 located in even rows and even columns are connected to the first data line 121, and the first data line 121 is connected to the first data line 121. The polarity of the first pixel electrode is opposite to that of the second data line 122, thereby balancing the coupling caused by the positive and negative frames; then, the first pixel electrode includes a first longitudinal trunk 1111 and a second longitudinal trunk 1112, and the first longitudinal trunk 1111 and the second longitudinal trunk 1112 are staggered, so that a part of the first data line 121 can be blocked by the first longitudinal trunk 1111, and a part of the second data line 122 can be blocked by the second longitudinal trunk 1112, so that the longitudinal trunks can play the role of shielding signals, thereby increasing the aperture ratio. In addition, the adjacent first pixel electrodes are mirror-set in the row direction, and the adjacent first pixel electrodes are also mirror-set in the column direction, so that the mirrored and adjacent pixels 110 can balance the influence of the data lines with opposite polarities on the liquid crystal molecules, so as to achieve compensation for the brightness difference of adjacent pixels 110 and improve the brightness uniformity of the array substrate 100.

[0052] For further information, see Figure 1 and Figure 2, the first longitudinal trunk 1111 and the second longitudinal trunk 1112 are arranged in a staggered and spaced manner. The first data line 121 is arranged in alignment with the first longitudinal trunk 1111, so that the first longitudinal trunk 1111 covers at least a portion of the first data line 121, and the second data line 122 is arranged in alignment with the second longitudinal trunk 1112, so that the second longitudinal trunk 1112 covers at least a portion of the second data line 122. The first longitudinal trunk 1111 and the second longitudinal trunk 1112 are arranged in parallel along the longitudinal direction, which is conducive to ensuring that the electric field distribution of the pixel 110 electrode is uniform. Coverage here means overlap, that is, the first longitudinal trunk 1111 overlaps at least a portion of the first data line 121, and the second longitudinal trunk 1112 overlaps at least a portion of the second data line 122, which is conducive to minimizing the electric field interference of the data line, improving the display effect, and reducing dark lines. Furthermore, due to the reasonable layout of the longitudinal trunk and the data line, the longitudinal trunk can play a shielding role, avoiding the use of shielding electrodes in traditional designs, thereby increasing the aperture ratio of pixel 110, allowing more light to pass through the pixel 110 area, and improving display brightness.

[0053] Furthermore, the first pixel electrode further includes a first transverse trunk 1113 and a plurality of first branches 1114. The first longitudinal trunk 1111 and the second longitudinal trunk 1112 are respectively connected to the two sides of the first transverse trunk 1113 in the column direction, and the plurality of first branches 1114 connect the first longitudinal trunk 1111, the second longitudinal trunk 1112 and the first transverse trunk 1113. Specifically, the first transverse trunk 1113 intersects with the first longitudinal trunk 1111 and the second longitudinal trunk 1112 to define a plurality of display domain areas 1115, and a plurality of first branches 1114 are arranged in the display domain area 1115, and the first branches 1114 are connected to the first transverse trunk 1113, the first longitudinal trunk 1111 and the second longitudinal trunk 1112. In addition, the first branches 1114 in adjacent display domain areas 1115 are arranged in a mirror image. In this embodiment, the first pixel electrode includes a first transverse trunk 1113 and two longitudinal trunks, and the two longitudinal trunks are respectively a first longitudinal trunk 1111 and a second longitudinal trunk 1112. The first transverse trunk 1113 intersects with both longitudinal trunks to form a plurality of display domain areas 1115. In each display domain area 1115, a plurality of first branches 1114 are arranged, and the first branches 1114 are connected to both the first transverse trunk 1113 and the two longitudinal trunks. The first branches 1114 in adjacent display domain areas 1115 are arranged in a mirror image, that is, the first branches 1114 in one display domain area 1115 extend to the left, and the first branches 1114 in another display domain area 1115 extend to the right. This mirror image arrangement can balance the electric field and reduce the non-uniform deflection of the liquid crystal molecules. By arranging the first transverse trunk 1113, the first longitudinal trunk 1111, and the second longitudinal trunk 1112 in the first pixel electrode, and arranging the first branch 1114 in the display domain area 1115, it is possible to ensure that the electric field is evenly distributed in the pixel 110 area, which is conducive to reducing the interference of the electric field on the liquid crystal molecules and improving the uniformity of the display brightness. The arrangement of the first branch 1114 makes the electric field in the display domain area 1115 more uniform, which can reduce unnecessary shading areas and improve the aperture ratio of the pixel 110. By mirroring the first branches 1114 in adjacent display domain areas 1115, the force of the electric field on the liquid crystal molecules can be balanced, and the light and dark differences and dark stripes caused by the uneven electric field can be reduced.

[0054] See also Figure 2 or Figure 5In some embodiments, a pixel 110 further includes a second pixel electrode. Along the column direction, the first pixel electrode and the second pixel electrode are arranged alternately, and the second pixel electrode includes a third longitudinal trunk 1121, a fourth longitudinal trunk 1122, a second transverse trunk 1123, and a plurality of second branches 1124. The third longitudinal trunk 1121 and the fourth longitudinal trunk 1122 are respectively arranged on both sides of the second transverse trunk 1123 in the column direction, and a plurality of second branches 1124 connect the second transverse trunk 1123, the third longitudinal trunk 1121, and the fourth longitudinal trunk 1122. In which, along the row direction, adjacent second pixel electrodes are arranged in a mirror image, and along the column direction, adjacent second pixel electrodes are arranged in a mirror image. The second pixel electrode structure here is the same as the first pixel electrode structure, and the beneficial effects are also the same, and the specific details of the second pixel electrode are not described in detail separately here.

[0055] However, it should be noted that the first pixel electrode and the second pixel electrode are arranged in the column direction and are mirror-imaged. Specifically, the first branch 1114 of the first pixel electrode and the second branch 1124 of the second pixel electrode are mirror-imaged, and the first longitudinal trunk 1111 and the second longitudinal trunk 1112 respectively shield the first data line 121 and the second data line 122, and the third longitudinal trunk 1121 and the fourth longitudinal trunk 1122 respectively shield the first data line 121 and the second data line 122 are also mirror-imaged.

[0056] In some embodiments, see Figures 1 to 4In two adjacent pixels 110, the pixel 110 electrode in one pixel 110 is mirrored with the pixel 110 electrode in the other pixel 110, and the two data lines in one pixel 110 are mirrored with the two data lines in the other pixel 110. For example, if the first longitudinal trunk 1111 in one pixel 110 is located on the left, then in the other pixel 110, the first longitudinal trunk 1111 will be located on the right. This can ensure that the electric field between adjacent pixels 110 is evenly distributed and reduce electric field interference. Similarly, in the transverse direction, the longitudinal trunks of the two pixels 110 are mirrored, and the branch electrodes of the two pixels 110 are also mirrored in the longitudinal and transverse directions. For the mirrored data lines, for example, if the first data line 121 in one pixel 110 is located on the left and the second data line 122 is located on the right, then in the other pixel 110, the first data line 121 will be located on the right and the second data line 122 will be located on the left. This mirror setting can balance the electric field effect of the data lines and reduce the brightness difference. The mirror image arrangement reduces the mutual interference between the data lines and the electrodes, and the effect of the electric field is more balanced, thereby reducing the difference between light and dark and the dark pattern phenomenon, and improving the stability and clarity of the display effect. Since the mirror image arrangement of the electrodes and the data lines reduces the electric field interference, no additional shielding electrode is required to prevent the deflection of the liquid crystal molecules, thereby improving the aperture ratio of the pixel 110.

[0057] In some embodiments, see Figure 4 or Figure 7 , the pixel 110 also includes a gate layer 113 and a common electrode 114. The common electrode 114 is arranged in the same layer as the gate layer 113, and the common electrode 114 is arranged in different layers from the data line and the pixel 110 electrode, and a parasitic capacitor is formed between the common electrode 114 and the gate layer 113. In each pixel 110, the gate layer 113 and the common electrode 114 are in the same layer, the gate layer 113 is used to control the switching state of the liquid crystal molecules, and the common electrode 114 is used to provide a reference voltage. The gate layer 113 and the common electrode 114 are connected to the data line and the pixel 110 electrode respectively to ensure the correct transmission and display of the signal. The common electrode 114 is in the same layer as the gate layer 113, and is in a different layer from the data line and the pixel 110 electrode. In this way, mutual interference between electrodes can be reduced, and the uniformity and stability of electric field distribution can be improved. The common electrode 114 is arranged in the same layer as the gate layer 113, which reduces mutual interference between electrodes, especially interference between data lines and pixel 110 electrodes. In this way, the electric field effect can be balanced and brightness differences and dark streaks can be reduced.

[0058] Further, in two adjacent pixels 110, the gate layer 113 in one pixel 110 is mirrored with the gate layer 113 in the other pixel 110, and the common electrode 114 in one pixel 110 is mirrored with the common electrode 114 in the other pixel 110. In two adjacent pixels 110, the gate layer 113 structure of one pixel 110 is mirrored with the gate layer 113 structure of the other adjacent pixel 110. For example, if the gate layer 113 in one pixel 110 is located on the left, then in the other adjacent pixel 110, the gate layer 113 will be located on the right. This can ensure that the electric field between adjacent pixels 110 is evenly distributed and reduce electric field interference. In two adjacent pixels 110, the common electrode 114 in one pixel 110 is mirrored with the common electrode 114 in the other adjacent pixel 110. For example, if the common electrode 114 in one pixel 110 is located on the left, then in the other adjacent pixel 110, the common electrode 114 will be located on the right. This mirror setting can balance the electric field effect and reduce brightness differences and dark streaks.

[0059] In some embodiments, the common electrode 114 includes two longitudinal electrode lines 1141 and two transverse electrode lines 1142. The longitudinal electrode lines 1141 include first segment lines 11411 and second segment lines 11412 that are arranged opposite to each other in the longitudinal direction. The two ends of one transverse electrode line 1142 are respectively connected to one end of the two first segment lines 11411. The two ends of another transverse electrode line 1142 are respectively connected to one end of the two second segment lines 11412. The gate layer 113 is provided in the area surrounded by the two transverse electrode lines 1142, the two first segment lines 11411 and the two second segment lines 11412, which is the gate area 115. Through this arrangement, the structure of the common electrode 114 can be further optimized, and the uniformity and stability of the electric field distribution can be improved.

[0060] In this embodiment, the two ends of a horizontal electrode line 1142 are respectively connected to one end of the two first segment lines 11411, and the two ends of the other horizontal electrode line 1142 are respectively connected to one end of the two second segment lines 11412 close to the first segment lines 11411, so that the two first segment lines 11411 are connected to one horizontal electrode line in a concave shape, and the two second segment lines 11412 are connected to another horizontal electrode line in an inverted concave shape. A gate area 115 can be defined between the two concave shapes, that is, between the two horizontal electrode lines 1142, and the gate layer 113 can be directly electrically connected to the two horizontal electrode lines 1142. The two longitudinal electrode lines 1141 can also be connected through the horizontal electrode lines 1142, thereby forming a circuit in which the gate layer 113 is connected to the common electrode 114, and is used to control the switching state of the liquid crystal molecules.

[0061] In some embodiments, see Figure 1 and Figure 5 The common electrode 114 includes two oppositely arranged longitudinal electrode lines 1141 and two oppositely arranged transverse electrode lines 1142. The longitudinal electrode line 1141 includes a first segment line 11411 and a second segment line 11412 that are oppositely arranged along the longitudinal direction. The two first segment lines 11411 and the two second segment lines 11412 jointly define a gate region 115. The gate layer 113 is disposed in the gate region 115. The two transverse electrode lines 1142 are respectively located on both sides of the gate layer 113 along the longitudinal direction, and two ends of one of the transverse electrode lines 1142 are respectively connected to one end of the two first segment lines 11411 that is away from the second segment line 11412, and two ends of the other transverse electrode line 1142 are respectively connected to one end of the two second segment lines 11412 that is away from the first segment line 11411.

[0062] In each pixel 110, the common electrode 114 includes two longitudinal electrode lines 1141 and two transverse electrode lines 1142. The two longitudinal electrode lines 1141 are arranged opposite to each other and are connected by two transverse electrode lines 1142 respectively. The two first segment lines 11411 and the two second segment lines 11412 jointly define a gate region 115, and a gate layer 113 is arranged in the gate region 115 for controlling the switching state of the liquid crystal molecules. By making the two transverse electrode lines 1142 away from each other, so that the two transverse electrodes are respectively located at the ends of the first segment line 11411 and the second segment line 11412 away from each other, compared with the close arrangement of the two transverse electrode lines 1142, the area occupied by the transverse electrode lines in the display domain area 1115 can be effectively reduced, thereby achieving the reduction of the black matrix shading area corresponding to the gate, and further improving the aperture ratio.

[0063] In some embodiments, see Figures 2 to 4 , or see Figures 5 to 7, the array substrate 100 further includes a plurality of scan lines, a first thin film transistor 130, a second thin film transistor 140 and a voltage dividing line 160; wherein the scan lines extend in the row direction. The first thin film transistor 130 and the second thin film transistor 140 are located between the first pixel electrode and the second pixel electrode, and the source of the first thin film transistor 130 is connected to the corresponding first data line 121 or the second data line 122. In other words, the source of a part of the first thin film transistor 130 is connected to the first data line 121, and the source of another part of the first thin film transistor 130 is connected to the second data line 122. Specifically, in odd rows and odd columns, the source of the first thin film transistor 130 is connected to the first data line 121, in even rows and odd columns, the source of the first thin film transistor 130 is connected to the second data line 122, in odd rows and even columns, the source of the first thin film transistor 130 is connected to the second data line 122, and in even rows and even columns, the source of the first thin film transistor 130 is connected to the first data line 121, so that the first thin film transistors 130 in the pixels 110 adjacent in the row direction and column direction are connected to different data lines, and then the pixels 110 adjacent in the row direction and column direction have opposite charges. In another embodiment, the first thin film transistors 130 in even rows and odd columns and odd rows and even columns are connected to the first data line 121, and the first thin film transistors 130 in odd rows and odd columns and even rows and even columns are connected to the second data line 122. Similarly, the first thin film transistors 130 in the pixels 110 that are adjacent in the row direction and the column direction are connected to different data lines, so that the pixels 110 that are adjacent in the row direction and the column direction have opposite charges.

[0064] In the above two embodiments, the first pixel electrode is connected to the drain of the first thin film transistor 130 , and the second pixel electrode is connected to the drain of the second thin film transistor 140 .

[0065] The voltage dividing line 160 extends along the column direction and is located between two adjacent columns of pixels 110 . The voltage dividing line 160 is connected to the source of the second thin film transistor 140 . The voltage dividing line 160 is disposed in the same layer as the data line group 120 .

[0066] Furthermore, two adjacent columns of pixels 110 share a voltage dividing line 160, that is, the voltage dividing line 160 is routed in the butt joint gap between two adjacent pixels 110 along the row direction. The voltage dividing line 160 is arranged in a different layer from the common electrode 114, and is arranged in the same layer as the first data line 121 and the second data line 122, and is connected to the common electrode 114 through a line, which is conducive to uniformly distributing the common voltage between adjacent pixels 110, ensuring the stability of the electric field between the pixel 110 electrode and the common electrode 114, and reducing the influence of the uneven electric field on the liquid crystal molecules.

[0067] In some embodiments, the array substrate 100 further includes a third thin film transistor 150. The source of the third thin film transistor 150 is connected to the source of the first thin film transistor 130, and the drain of the third thin film transistor 150 is connected to the drain of the second thin film transistor 140, thereby connecting the second thin film transistor 140 to the first thin film transistor 130, and then making the second thin film transistor 140 and the first thin film transistor 130 electrically connected to the same data line.

[0068] Further, in the row direction, the first thin film transistors 130 in adjacent pixels 110 are arranged in a mirror image with the voltage dividing line 160 as the symmetry axis, the second thin film transistors 140 in adjacent pixels 110 are arranged in a mirror image with the voltage dividing line 160 as the symmetry axis, and the third thin film transistors 150 in adjacent pixels 110 are arranged in a mirror image with the voltage dividing line 160 as the symmetry axis. Similarly, in the column direction, the first thin film transistors 130, the second thin film transistors 140 and the third thin film transistors 150 in adjacent pixels 110 are arranged in a mirror image with the voltage dividing line 160 as the symmetry axis.

[0069] In some embodiments, see Figure 3 , the first thin film transistor 130 and the third thin film transistor 150 are located on the same side of a data line group 120. The first thin film transistor 130 and the third thin film transistor 150 are both located on the same side of the data line group 120, which is mainly determined by the structure of the gate layer 113. The gate layer 113 includes a first gate electrode 1131. When the first thin film transistor 130 and the third thin film transistor 150 are both connected to the first gate electrode 1131, the first thin film transistor 130 and the third thin film transistor 150 are located on the same side of the data line group 120, which facilitates the connection between the thin film transistor and the gate electrode.

[0070] In some embodiments, see Figure 6The first thin film transistor 130 and the third thin film transistor 150 are located at opposite sides of the first data line 121 or the second data line 122 of the corresponding data line group 120. The gate layer 113 includes a first gate electrode 1131 and a second gate electrode 1132. The first gate electrode 1131 and the second gate electrode 1132 are staggered and located at two sides of the projection of the first data line 121 or the second data line 122 in the data line group 120 toward the substrate. Since the first thin film transistor 130 is connected to the first gate electrode 1131 and the third thin film transistor 150 is connected to the second gate electrode 1132, the first thin film transistor 130 and the third thin film transistor 150 are located at opposite sides of the first data line 121 or the second data line 122 of the corresponding data line group 120. Specifically, along the row direction, the first thin film transistor 130 and the third thin film transistor 150 in one of the adjacent pixels 110 are located on both sides of the first data line 121, and the first thin film transistor 130 and the third thin film transistor 150 in the other pixel 110 are located on both sides of the second data line 122. Similarly, along the column direction, the first thin film transistor 130 and the third thin film transistor 150 in one of the adjacent pixels 110 are located on both sides of the first data line 121, and the first thin film transistor 130 and the third thin film transistor 150 in the other pixel 110 are located on both sides of the second data line 122.

[0071] In some embodiments, see Figure 1 and Figure 8, the plurality of pixels 110 include a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels. The colors of the first pixel, the second pixel, and the third pixel are all different. In the present embodiment, the first pixel is red, the second pixel is green, and the third pixel is blue. By utilizing the three primary colors, a screen display of multiple colors is realized. A first pixel, a second pixel, and a third pixel are arranged adjacent to each other in sequence to form a pixel 110 unit. The plurality of pixel 110 units are arranged adjacent to each other. In two pixels 110 of the same color in adjacent pixel 110 units, the two pixels 110 share two data lines, and one data line is connected to one pixel 110, and the two data lines respectively connecting the two pixels 110 have opposite polarities. That is, in two adjacent pixels 110 of the same color, there are two data lines located in both pixels 110, but each pixel 110 is connected to only one of the data lines, and the other data line located in the pixel 110 is not connected to the pixel 110, but is connected to another adjacent pixel 110 of the same color. In this way, there are two data lines with opposite polarities in one pixel 110, which effectively balances the positive and negative frame coupling effects in the pixel 110. In addition, pixels 110 of adjacent colors share two data lines, which is conducive to reducing the number of data lines and maintaining the driving cost unchanged.

[0072] In some embodiments, the first data line 121 in the Nth data line group 120 is connected in parallel with the first data line 121 in the N+Mth data line group 120, and M is an integer multiple of 3. Specifically, in this embodiment, a pixel 110 unit includes six pixels 110, namely, a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel. The six pixels 110 are arranged in sequence along the row direction, and the first pixel and the fourth pixel have the same color, both are red, the second pixel and the fifth pixel have the same color, both are green, and the third pixel and the sixth pixel have the same color, both are blue. The two data lines in the first pixel are respectively connected to the two data lines in the fourth pixel, the two data lines in the second pixel are respectively connected to the two data lines in the fifth pixel, and the two data lines in the third pixel are respectively connected to the two data lines in the sixth pixel, which is conducive to reducing the driving cost. In addition, by connecting the pixels 110 of the same color to the same data line, it is ensured that the pixels 110 of the same color receive consistent data signals, thereby improving the uniformity of the displayed color and avoiding color distortion.

[0073] The present application also provides a display panel, which includes an array substrate, an opposing substrate, and a liquid crystal layer. The array substrate is the array substrate described in any of the aforementioned embodiments, and the specific structure of the array substrate is not described in detail here. The opposing substrate is located on one side of the array substrate, and the liquid crystal layer is arranged between the array substrate and the opposing substrate. Because the display panel provided in this embodiment includes the array substrate described in any of the aforementioned embodiments, the display panel has the same structure and beneficial effects as the array substrate, and is not described in detail here.

[0074] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0075] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of the present application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of the present application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

Claims

1. An array substrate, characterized in that: include: substrate; N+1 data line groups, the data line groups are located on the substrate, and N is an integer greater than or equal to 1; A plurality of pixels, the pixels are arranged along a row direction and a column direction, and a data line group is located in a column of the pixels; Wherein, the data line group comprises a first data line and a second data line, the pixels located in odd rows and odd columns are connected to the first data line, and the pixels located in odd rows and even columns are connected to the second data line; the pixels located in even rows and odd columns are connected to the second data line, and the pixels located in even rows and even columns are connected to the first data line; the first data line and the second data line have opposite polarities; The pixel includes a first pixel electrode, the first pixel electrode includes a first longitudinal trunk and a second longitudinal trunk extending along the column direction, and the first longitudinal trunk and the second longitudinal trunk are staggered, and along the row direction, adjacent first pixel electrodes are mirror-arranged, and along the column direction, adjacent first pixel electrodes are mirror-arranged.

2. The array substrate according to claim 1, characterized in that: The first longitudinal trunk overlaps at least a portion of the first data line, and the second longitudinal trunk overlaps at least a portion of the second data line.

3. The array substrate according to claim 1, characterized in that: The first data line in the Nth data line group and the first data line in the N+Mth data line group are connected in parallel, where M is an integer multiple of 3.

4. The array substrate according to claim 1, wherein: The first pixel electrode also includes a first transverse trunk and a plurality of first branches. The first longitudinal trunk and the second longitudinal trunk are respectively connected to both sides of the first transverse trunk in the column direction. The plurality of first branches connect the first longitudinal trunk, the second longitudinal trunk and the first transverse trunk.

5. The array substrate according to claim 4, characterized in that: The pixel further comprises a second pixel electrode, wherein the first pixel electrode and the second pixel electrode are alternately arranged along the column direction, the second pixel electrode comprises a third longitudinal trunk, a fourth longitudinal trunk, a second transverse trunk and a plurality of second branches, the third longitudinal trunk and the fourth longitudinal trunk are respectively arranged at both sides of the second transverse trunk in the column direction, and the plurality of second branches connect the second transverse trunk, the third longitudinal trunk and the fourth longitudinal trunk; Wherein, along the row direction, adjacent second pixel electrodes are arranged in a mirror image, and along the column direction, adjacent second pixel electrodes are arranged in a mirror image.

6. The array substrate according to claim 5, characterized in that: The array substrate further comprises a plurality of scanning lines, a first thin film transistor, a second thin film transistor and a voltage dividing line; in The scan lines extend along the row direction; The first thin film transistor and the second thin film transistor are located between the first pixel electrode and the second pixel electrode, the source of the first thin film transistor is connected to the corresponding first data line or the second data line, the first pixel electrode is connected to the drain of the first thin film transistor, and the second pixel electrode is connected to the drain of the second thin film transistor; The voltage dividing line extends along the column direction and is located between two adjacent columns of pixels. The voltage dividing line is connected to the source of the second thin film transistor. The voltage dividing line is arranged in the same layer as the data line group.

7. The array substrate according to claim 6, characterized in that: Two adjacent columns of pixels share one voltage dividing line.

8. The array substrate according to claim 6, wherein: The array substrate further includes a third thin film transistor, a source of the third thin film transistor is connected to the source of the first thin film transistor, and a drain of the third thin film transistor is connected to the drain of the second thin film transistor.

9. The array substrate according to claim 8, characterized in that: The first thin film transistor and the third thin film transistor are located at a same side of a data line group.

10. The array substrate according to claim 8, characterized in that: The first thin film transistor and the third thin film transistor are located at opposite sides of the first data line or the second data line of the corresponding data line group.

11. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 10, and An opposing substrate, located at one side of the array substrate; A liquid crystal layer is disposed between the array substrate and the counter substrate.

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