High-precision base current compensation device

Abstract

The invention provides a high-precision base current compensation device, relates to the technical field of current compensation, and is used for solving the technical problems of large compensation error and high power consumption of a base current compensation method in the prior art. The apparatus comprises: a differential amplifier; and the base current compensation circuit is connected with the differential amplifier, is used for compensating the base current of the input transistor N1 and the input transistor N2, and comprises transistors N5 to N10, a load resistor RR3 and a resistor R4. According to the device, transistors N5-N10, a load resistor RR3 and a resistor R4 are used for forming a base current compensation circuit of an input transistor of the differential amplifier, the matching relation of resistance and current is combined, the influence caused by the base current of the transistors is reduced, and compared with a traditional transistor sampling compensation method, the theoretical compensation error is eliminated, and the compensation precision is improved. And the compensation precision is higher.

Description

Technical Field

[0001] The present disclosure relates to the technical field of current compensation, and more specifically, to a high-precision base current compensation device. Background Art

[0002] There are usually two methods for base current compensation at present: one method is to use the base current of the Cascode (common source and common gate) tube of the input stage amplifier to mirror compensate the base current of the input transistor. The disadvantage of this method is that the amplifier coefficients of the sampling tube and the input collective tube do not match, and the amplification factor of the pnp transistor (a transistor with a p-type semiconductor as the emitter, an n-type semiconductor as the base, and a p-type semiconductor as the collector) is generally small. Due to the existence of the Early voltage, the compensation error is 1 / 20-1 / 5. When the input transistor is a super-β transistor, the error is further amplified; another method is to use a replica input transistor to form a replica amplifier current, and then mirror the base current of the replica amplifier through a Wilson current mirror to compensate for the base current of the signal input transistor. However, this method uses a large number of transistors, wastes area and power consumption, and has high requirements for the layout (considering the existence of the process). When the amplification factor of the pnp transistor is not high, the circuit error will be further amplified.

[0003] It can be seen that the base current compensation method in the prior art has a large compensation error and high power consumption. Therefore, how to improve the accuracy of base current compensation of transistor amplifiers and reduce the error is an important issue currently faced. Summary of the invention

[0004] In view of this, the present disclosure provides a high-precision base current compensation device to solve the technical problems of large compensation error and high power consumption in the base current compensation method in the prior art.

[0005] One aspect of the present disclosure provides a high-precision base current compensation device, including: a differential amplifier, including: an input transistor N1 and an input transistor N2, respectively used to receive an input signal; a current bias transistor N3, connected to the emitters of the input transistor N1 and the input transistor N2, used to provide a bias voltage; a current bias transistor N4, connected to the current bias transistor N3, used to provide a bias current; a resistor R3, connected to the current bias transistor N4, used to adjust the magnitude of the bias current; a base current compensation circuit, connected to the differential amplifier, used to compensate for the base currents of the input transistors N1 and N2, including: a transistor N5, connected to the current bias transistor N3; a transistor N6, connected to the current bias transistor N4; a transistor N7, connected to the current bias transistor N8, connected to the current bias transistor N9; a transistor N8, connected to the current bias transistor N10, connected to the current bias transistor N111; a transistor N9, connected to the current bias transistor N112; a transistor N10, connected to the current bias transistor N113; a transistor N11, connected to the current bias transistor N114; a transistor N11, connected to the current bias transistor N115; a transistor N11, connected to the current bias transistor N116; a transistor N11, connected to the current bias transistor N117; a transistor N11, connected to the current bias transistor N118; a transistor N11, connected to the current bias transistor N119; a transistor N12 The body transistor N7 is connected to the transistor N5; the transistor N8 is connected to the input transistor N1; the transistor N9 is connected to the input transistor N2; the transistor N10 is connected to the collectors of the transistors N8 and N9, and is connected to the transistor N7 to form a loop; the load resistor RR3 is connected to the transistor N7 to provide a load; the resistor R4 is connected to the transistor N6 to adjust the size of the compensation current; wherein, the emitter area of ​​the current bias transistor N4 is twice that of the transistor N6, and the resistance value of the resistor R4 is twice that of the resistor R3. By controlling the resistance value of the resistor R4, the collector currents of the transistors N8 and N9 are equal to the base currents of the input transistors N1 and N2, thereby completing the compensation of the base current of the differential amplifier.

[0006] According to an embodiment of the present disclosure, the differential amplifier is configured as a symmetrical differential input structure so that the currents flowing through the input transistor N1 , the input transistor N2 , and the transistor N7 are equal in magnitude.

[0007] According to an embodiment of the present disclosure, the differential amplifier further includes: a load resistor RR1 connected to the input transistor N1; a load resistor RR2 connected to the input transistor N2; wherein the resistance values ​​of the load resistor RR1, the load resistor RR2 and the load resistor RR3 are equal.

[0008] According to an embodiment of the present disclosure, the differential amplifier further includes: an input bias resistor R1 connected to the input transistor N1; an input bias resistor R2 connected to the input transistor N2; wherein the resistance values ​​of the input bias resistor R1 and the input bias resistor R2 are equal.

[0009] According to an embodiment of the present disclosure, the input transistors N1 , N2 and N7 are configured to have the same bias conditions, so that the currents flowing through the bases of the input transistors N1 , N2 and N7 are equal in magnitude.

[0010] According to an embodiment of the present disclosure, the collector current of the transistor N10 is equal to the base current of the transistor N7 .

[0011] According to an embodiment of the present disclosure, transistors N8 , N9 and N10 are configured to have the same emitter area, the same transistor type and the same emitter voltage, so that the current amplification factors of transistors N8 , N9 and N10 are equal.

[0012] According to an embodiment of the present disclosure, a voltage bias circuit is connected to the differential amplifier and is used to provide a bias voltage to ensure the stability of the circuit.

[0013] According to an embodiment of the present disclosure, the voltage bias circuit includes: a resistor R5 connected to the collectors of the transistors N8 and N9; a resistor R6 connected to the resistor R5; and a resistor R7 connected to the resistor R6.

[0014] According to an embodiment of the present disclosure, the resistance values ​​of the resistors R5 , R6 and R7 are equal.

[0015] The high-precision base current compensation device provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0016] (1) The high-precision base current compensation device provided in the embodiment of the present disclosure uses transistors N5 to N10, load resistor RR3 and resistor R4 to form a base current compensation circuit of the differential amplifier input transistor, and combines the matching relationship between resistance and current to reduce the influence of the transistor base current. Compared with the traditional transistor sampling compensation method, the theoretical compensation error is eliminated, making the compensation accuracy higher.

[0017] (2) The high-precision base current compensation device provided in the embodiment of the present disclosure changes the compensation method of using a current mirror structure to replicate the amplifier current in the traditional method, so that the circuit implementation area is smaller and the power consumption is lower.

[0018] (3) The high-precision base current compensation device provided in the embodiment of the present disclosure can realize the compensation of the base current of the transistor amplifier without theoretical error, thereby realizing zero bias current input of the transistor amplifier, greatly improving the amplifier input impedance and current detection accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1 The structure diagram of a high-precision base current compensation device according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0022] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0023] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0024] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0025] There are usually two methods for base current compensation:

[0026] One method is to use the base current of the cascode tube of the input stage amplifier to mirror compensate the base current of the input transistor. The disadvantage of this method is that the amplifier coefficients of the sampling tube and the input collective tube do not match, and the amplification factor of the pnp transistor is generally small. Due to the existence of the Early voltage, the compensation error is 1 / 20-1 / 5. When the input transistor is a super-β transistor, the error will be further amplified.

[0027] Another method is to use a replica input transistor to form a replica amplifier current, and then use a Wilson current mirror to mirror the base current of the replica amplifier to compensate for the base current of the signal input transistor. However, this method uses a large number of transistors, wastes area and power consumption, and has high requirements for the layout (considering the existence of the process). When the amplification factor of the pnp transistor is not high, the circuit error will be further amplified.

[0028] Based on this, an embodiment of the present disclosure provides a high-precision base current compensation device to solve the technical problems of large compensation error and high power consumption in the base current compensation method in the prior art.

[0029] Figure 1 The structure diagram of a high-precision base current compensation device according to an embodiment of the present disclosure is schematically shown.

[0030] like Figure 1 As shown, the high-precision base current compensation device of the embodiment of the present disclosure may include, for example: a differential amplifier and a base current compensation circuit.

[0031] The differential amplifier may specifically include: an input transistor N1, an input transistor N2, a current bias transistor N3, a current bias transistor N4 and a resistor R3.

[0032] The input transistor N1 and the input transistor N2 are respectively used for receiving input signals.

[0033] The current bias transistor N3 is connected to the emitters of the input transistor N1 and the input transistor N2 for providing a bias voltage.

[0034] The current bias transistor N4 is connected to the current bias transistor N3 for providing a bias current.

[0035] The resistor R3 is connected to the current bias transistor N4 and is used to adjust the magnitude of the bias current.

[0036] The base current compensation circuit is connected to the differential amplifier and is used to compensate the base currents of the input transistor N1 and the input transistor N2 in the differential amplifier. Specifically, the circuit may include transistors N5 to N10, a load resistor RR3 and a resistor R4.

[0037] Among them, transistor N5 is connected to current bias transistor N3; transistor N6 is connected to current bias transistor N4; transistor N7 is connected to transistor N5; transistor N8 is connected to input transistor N1; transistor N9 is connected to input transistor N2; transistor N10 is connected to collectors of transistor N8 and transistor N9, and is connected to transistor N7 to form a loop.

[0038] The load resistor RR3 is connected to the transistor N7 to provide a load.

[0039] The resistor R4 is connected to the transistor N6 and is used to adjust the magnitude of the compensation current.

[0040] In this embodiment, the emitter area of ​​the current bias transistor N4 is twice that of the transistor N6, and the resistance of the resistor R4 is twice that of the resistor R3.

[0041] By controlling the resistance of the resistor R4, the collector currents of the transistors N8 and N9 are made equal to the base currents of the input transistors N1 and N2, thereby completing the compensation of the base current of the differential amplifier.

[0042] The high-precision base current compensation device provided in the embodiment of the present disclosure uses transistors N5 to N10, load resistor RR3 and resistor R4 to form a base current compensation circuit of the differential amplifier input transistor, and combines the matching relationship between resistance and current to reduce the influence of the transistor base current. Compared with the traditional transistor sampling compensation method, the theoretical compensation error is eliminated, making the compensation accuracy higher.

[0043] According to an embodiment of the present disclosure, the differential amplifier is configured as a symmetrical differential input structure so that the currents flowing through the input transistor N1 , the input transistor N2 , and the transistor N7 are equal in magnitude.

[0044] In this embodiment, since the emitter area of ​​the current bias transistor N4 is twice that of the transistor N6, it can be obtained that the saturation current of the current bias transistor N4 is twice that of the transistor N6, that is:

[0045] I s4 =2×I s6 (Formula 1)

[0046] Among them, I s4 represents the saturation current of the current bias transistor N4, I s6 represents the saturation current of transistor N6.

[0047] The resistance of resistor R4 is twice that of resistor R3, that is:

[0048] R 4= 2×R 3 (Formula 2)

[0049] Among them, R 4 Represents the resistance value of resistor R4, R 3 Indicates the resistance value of resistor R3.

[0050] According to Kirchhoff's voltage law, we can get:

[0051] (Formula 3)

[0052] Among them, I c4 represents the collector current of the current bias transistor N4, I c6 represents the collector current of transistor N6, V T Represents thermal voltage.

[0053] Combining Formula 1, Formula 2, and Formula 3, we can get that the collector current of the current bias transistor N4 is twice that of the transistor N6, that is:

[0054] I c4 =2×I c6 (Formula 4)

[0055] In this embodiment, since the differential amplifier is a symmetrical differential input structure, the currents flowing through the input transistor N1, the input transistor N2 and the transistor N7 are equal in magnitude, all being I c6 , that is:

[0056] I c1 = I c2 = I c7 = I c6 (Formula 5)

[0057] Among them, I c1 represents the collector current of input transistor N1, I c2 represents the collector current of input transistor N2, I c7 represents the collector current of transistor N7.

[0058] According to an embodiment of the present disclosure, the differential amplifier further includes: a load resistor RR1 and a load resistor RR2 for providing a load.

[0059] The load resistor RR1 is connected to the input transistor N1.

[0060] The load resistor RR2 is connected to the input transistor N2; wherein the resistance values ​​of the load resistors RR1, RR2 and RR3 are equal.

[0061] According to an embodiment of the present disclosure, the differential amplifier further includes: input bias resistors R1 and R2, which are used to control the bias current of the bases of input transistors N1 and N2 to ensure that the transistors operate in a linear region to avoid saturation or cutoff.

[0062] The input bias resistor R1 is connected to the input transistor N1.

[0063] The input bias resistor R2 is connected to the input transistor N2; wherein the resistance values ​​of the input bias resistor R1 and the input bias resistor R2 are equal.

[0064] According to an embodiment of the present disclosure, the input transistors N1 , N2 and N7 are configured to have the same bias conditions, so that the currents flowing through the bases of the input transistors N1 , N2 and N7 are equal in magnitude.

[0065] According to an embodiment of the present disclosure, the collector current of the transistor N10 is equal to the base current of the transistor N7 .

[0066] In this embodiment, since the resistance values ​​of the load resistors RR1, RR2 and RR3 are equal, the types and DC working environments (bias conditions) of the input transistors N1, N2 and N7 are also exactly the same, therefore, the magnitudes of the currents flowing through the bases of the input transistors N1, N2 and N7 should be equal, that is:

[0067] I b7 =I b1 = I b2 (Formula 6)

[0068] Among them, I b7 represents the base current of transistor N7, I b1 represents the base current of input transistor N1, I b2 represents the base current of input transistor N2.

[0069] The collector current of transistor N10 is equal to the base current of transistor N7, that is:

[0070] I c10 =I b7 (Formula 7)

[0071] Among them, I c10 represents the collector current of transistor N10, I b7 represents the base current of transistor N7.

[0072] According to an embodiment of the present disclosure, transistors N8 , N9 and N10 are configured to have the same emitter area, the same transistor type and the same emitter voltage, so that the current amplification factors of transistors N8 , N9 and N10 are equal.

[0073] In this embodiment, since the transistors N8, N9 and N10 have the same emitter area, the same transistor type and the same emitter voltage, according to the equation:

[0074] (Formula 8)

[0075] Among them, I b Represents the base current, I ss represents the saturation current, V BE Represents the BE junction voltage of the transistor.

[0076] It can be seen that the base currents of transistors N8, N9 and N10 are the same, and because the transistor types are the same, the current amplification factors are also the same, that is:

[0077] I c8 =I c9 =I c10 (Formula 9)

[0078] Among them, I c8 represents the collector current of transistor N8, I c9 represents the collector current of transistor N9.

[0079] Combining Formula 6, Formula 7 and Formula 9, we can get:

[0080] I c8 =I c9 =I b1 =I b2 (Formula 10)

[0081] Therefore, the collector currents of the transistors N8 and N9 compensate the base currents of the differential amplifier input transistors N1 and N2, and the differential amplifier achieves an input with zero bias current.

[0082] The high-precision base current compensation device provided by the embodiment of the present disclosure changes the compensation method of using a current mirror structure to replicate the amplifier current in the traditional method, so that the circuit implementation area is smaller and the power consumption is lower.

[0083] According to an embodiment of the present disclosure, the high-precision base current compensation device may further include, for example: a voltage bias circuit.

[0084] The voltage bias circuit is connected to the differential amplifier and is used to provide a bias voltage to ensure the stability of the circuit.

[0085] In this embodiment, the voltage bias circuit may specifically include: a resistor R5, a resistor R6, and a resistor R7.

[0086] The resistor R5 is connected to the collectors of the transistor N8 and the transistor N9.

[0087] The resistor R6 is connected to the resistor R5.

[0088] The resistor R7 is connected to the resistor R6 , wherein the resistance values ​​of the resistors R5 , R6 and R7 are equal.

[0089] The high-precision base current compensation device provided in the embodiment of the present disclosure can realize the compensation of the base current of the transistor amplifier without theoretical error through a differential amplifier, a base current compensation circuit and a voltage bias circuit, thereby realizing 0 bias current input of the transistor amplifier, greatly improving the amplifier input impedance and current detection accuracy.

[0090] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments of the present disclosure can be combined and / or combined in a variety of ways, even if such a combination or combination is not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teaching of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0091] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A high-precision base current compensation device, characterized in that: The device comprises: Differential amplifiers, including: The input transistor N1 and the input transistor N2 are respectively used for receiving input signals; A current bias transistor N3 connected to the emitters of the input transistor N1 and the input transistor N2, and configured to provide a bias voltage; A current bias transistor N4, connected to the current bias transistor N3, for providing a bias current; A resistor R3, connected to the current bias transistor N4, for adjusting the magnitude of the bias current; A base current compensation circuit, connected to the differential amplifier, for compensating the base currents of the input transistor N1 and the input transistor N2, comprising: A transistor N5 connected to the current bias transistor N3; A transistor N6 connected to the current bias transistor N4; A transistor N7 connected to the transistor N5; A transistor N8 connected to the input transistor N1; A transistor N9 connected to the input transistor N2; A transistor N10 connected to the collectors of the transistor N8 and the transistor N9, and connected to the transistor N7 to form a loop; A load resistor RR3 is connected to the transistor N7 and is used to provide a load; A resistor R4 is connected to the transistor N6 and is used to adjust the magnitude of the compensation current; Among them, the emitter area of ​​the current bias transistor N4 is twice that of the transistor N6, and the resistance value of the resistor R4 is twice that of the resistor R3. By controlling the resistance value of the resistor R4, the collector currents of the transistors N8 and N9 are equal to the base currents of the input transistors N1 and N2, thereby completing the compensation of the base current of the differential amplifier.

2. The high-precision base current compensation device according to claim 1, characterized in that: The differential amplifier is configured as a symmetrical differential input structure so that the currents flowing through the input transistor N1 , the input transistor N2 , and the transistor N7 are equal in magnitude.

3. The high-precision base current compensation device according to claim 2, characterized in that: The differential amplifier further comprises: A load resistor RR1 connected to the input transistor N1; A load resistor RR2 connected to the input transistor N2; The load resistor RR1, the load resistor RR2 and the load resistor RR3 have the same resistance value.

4. The high-precision base current compensation device according to claim 2, characterized in that: The differential amplifier further comprises: An input bias resistor R1 connected to the input transistor N1; An input bias resistor R2 connected to the input transistor N2; The input bias resistor R1 and the input bias resistor R2 have the same resistance value.

5. The high-precision base current compensation device according to claim 4, characterized in that: The input transistor N1 , the input transistor N2 , and the transistor N7 are configured to have the same bias conditions, so that the currents flowing through the bases of the input transistor N1 , the input transistor N2 , and the transistor N7 are equal in magnitude.

6. The high-precision base current compensation device according to claim 5, characterized in that: The collector current of the transistor N10 is equal to the base current of the transistor N7.

7. The high-precision base current compensation device according to claim 6, characterized in that: The transistor N8 , the transistor N9 , and the transistor N10 are configured to have the same emitter area, the same transistor type, and the same emitter voltage, so that the current amplification factors of the transistor N8 , the transistor N9 , and the transistor N10 are equal.

8. The high-precision base current compensation device according to any one of claims 1 to 7, characterized in that: The device also includes: The voltage bias circuit is connected to the differential amplifier and is used to provide a bias voltage to ensure the stability of the circuit.

9. The high-precision base current compensation device according to claim 8, characterized in that: The voltage bias circuit comprises: A resistor R5 connected to collectors of the transistor N8 and the transistor N9; A resistor R6 connected to the resistor R5; The resistor R7 is connected to the resistor R6.

10. The high-precision base current compensation device according to claim 9, characterized in that: The resistance values ​​of the resistor R5, the resistor R6 and the resistor R7 are equal.

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