Power utilization information acquisition terminal and watchdog reset time adjusting circuit of electric energy meter

Abstract

The invention discloses a watchdog reset time adjusting circuit for an electricity consumption information acquisition terminal and an electric energy meter, which comprises a watchdog chip D1 and a time delay circuit connected between a watchdog power supply end VDOG and a reset signal output pin RST of the watchdog chip D1, the voltage output end of the time delay circuit is connected with a voltage monitoring input pin PFI of the watchdog chip D1; when the watchdog chip D1 sends a reset signal, a voltage signal used for triggering voltage alarm for a certain time length is sent to a voltage monitoring input pin PFI of the watchdog chip D1 through the time delay circuit; and the manual reset input pin MR of the watchdog chip D1 is also connected with the voltage monitoring output pin PFO through a diode V4. According to the invention, the duration of the reset signal is prolonged and freely adjusted, the problems of repeated restart and incomplete restart when the equipment is reset are solved, and the normal operation of the equipment after restart is ensured.

Description

Technical Field

[0001] The invention relates to a protection circuit, in particular to a watchdog reset time adjustment circuit. Background Art

[0002] In order to ensure the reliability of power-on and reset, the power consumption information collection terminal and the energy meter usually use a dedicated watchdog chip to reset the control unit or directly control the power supply. Figure 3 , the front-stage power supply is connected to the rear-stage power supply through the controlled circuit. The rear-stage power supply is responsible for supplying power to the control unit, functional modules, etc., and the front-stage power supply also supplies power to the watchdog circuit. When the control unit operates normally, it sends a dog-feeding signal to the watchdog circuit regularly. When the control unit is abnormal and cannot send a dog-feeding signal, the watchdog circuit will send a reset signal of a certain length to the controlled circuit, so that the rear-stage power supply is temporarily turned off and then turned on again, thereby restarting the control unit and functional modules. This method can realize the reset of power on and off, and can also perform power supply monitoring.

[0003] However, the reset time of traditional watchdog chips is usually fixed, for example, the typical value of the 706 series is 200 milliseconds. With the continuous upgrading of power consumption information collection terminals and energy meter configurations, the requirements for performance are getting higher and higher, and the functions are increasing. Many devices have begun to adopt operating system architectures. At the same time, peripheral circuits have become more complex and contain a large number of electrolytic capacitors. In this case, during the power-off reset and restart process of the device, the 200-millisecond reset time may not be enough to ensure that the power supply voltage drops to 0 volts, resulting in the system being unable to completely restart and freezing. In more serious cases, the device may still work normally after the reset signal is generated, which poses a hidden danger to the normal operation of the device. Therefore, it is necessary to extend the reset time to ensure that the device can be reliably and completely powered off, reset and restarted. Summary of the invention

[0004] The present invention proposes a watchdog reset time adjustment circuit for an electricity consumption information collection terminal and an electric energy meter, the purpose of which is to solve the problem that the equipment cannot be restarted normally due to the short reset time of the watchdog circuit.

[0005] The technical solution of the present invention is as follows: A watchdog reset time adjustment circuit for an electricity consumption information collection terminal and an electric energy meter, comprising a watchdog chip D1 and a watchdog power supply terminal VDOG connected to a power supply pin VCC of the watchdog chip D1, and also comprising a delay circuit connected between the watchdog power supply terminal VDOG and a reset signal output pin RST of the watchdog chip D1, wherein the voltage output terminal of the delay circuit is connected to a voltage monitoring input pin PFI of the watchdog chip D1; when the watchdog chip D1 sends a reset signal, a voltage signal for triggering a voltage alarm of a certain duration is sent to the voltage monitoring input pin PFI of the watchdog chip D1 through the delay circuit; The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter also includes a diode V4, the anode of the diode V4 is connected to the manual reset input pin MR of the watchdog chip D1, and the cathode is connected to the voltage monitoring output pin PFO of the watchdog chip D1.

[0006] As a further improvement of the watchdog reset time adjustment circuit of the electricity consumption information collection terminal and the electric energy meter: the delay circuit includes a resistor R9, a capacitor C2 and a resistor R8 which are sequentially connected between the watchdog power supply terminal VDOG and the reset signal output pin RST of the watchdog chip D1; the connection point between the resistor R9 and the capacitor C2 is the voltage output end of the delay circuit.

[0007] As a further improvement of the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter: the delay circuit also includes a diode V3, the anode of the diode V3 is connected to the voltage monitoring input pin PFI of the watchdog chip D1, and the cathode is connected to the watchdog power supply terminal VDOG.

[0008] As a further improvement of the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter: the watchdog output pin WDO of the watchdog chip D1 is connected to the manual reset input pin MR of the watchdog chip D1 through the resistor R10.

[0009] As a further improvement of the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter: it also includes a button SW1 and a resistor R11, and the manual reset input pin MR of the watchdog chip D1 is grounded through the resistor R11 and the button SW1 in sequence.

[0010] As a further improvement of the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter: the manual reset input pin MR of the watchdog chip D1 is also grounded through a capacitor C4.

[0011] As a further improvement of the watchdog reset time adjustment circuit of the electricity consumption information collection terminal and the electric energy meter: it also includes a controlled circuit connected between the positive terminal of the front-stage power supply and the positive terminal of the rear-stage power supply, and the reset signal output pin RST of the watchdog chip D1 is connected to the control end of the controlled circuit.

[0012] As a further improvement of the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter: the controlled circuit includes a PMOS tube V1 and a transistor V50, the source of the PMOS tube V1 is connected to the positive terminal of the front-stage power supply, and the drain is connected to the positive terminal of the rear-stage power supply; The control end of the controlled circuit is connected to the transistor V50, and the transistor V50 is used to control the PMOS tube V1 to be turned on and off according to the reset signal of the watchdog chip D1.

[0013] As a further improvement of the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter: the controlled circuit further includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7 and a capacitor C1; The watchdog power supply terminal VDOG is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the base of the transistor V50 through the resistor R4; R5 is connected between the base and emitter of the transistor V50, and the emitter of the transistor V50 is grounded; The collector of the transistor V50 is connected to the gate of the PMOS tube V1 through the resistor R2, and is also connected to the source of the PMOS tube V1 through the resistor R3; the capacitor C1 is also connected between the gate and source of the PMOS tube V1.

[0014] As a further improvement of the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter: the controlled circuit also includes an NMOS tube V2, a resistor R1 and a resistor R6; The collector of the transistor V50 is connected to the gate of the NMOS transistor V2, the source of the NMOS transistor V2 is grounded, the drain is connected to the positive terminal of the subsequent power supply through the resistor R1, and is connected to the positive terminal of the previous power supply through the resistor R5.

[0015] Compared with the prior art, the present invention has the following positive effects: 1. The present invention sends a voltage signal of a certain duration to the voltage monitoring input pin PFI of the watchdog chip through a delay circuit while sending a reset signal, and then pulls down the manual reset pin MR of the watchdog chip through the voltage monitoring output pin PFO, and cleverly uses the voltage monitoring function of the watchdog chip to keep the watchdog chip in a reset state within the duration until the voltage signal is eliminated. After the watchdog chip maintains the reset signal for a certain duration, the reset signal is eliminated, thereby extending the duration of the reset signal (the duration of the reset signal can be extended from 200ms to seconds), solving the problem of repeated restarts and incomplete restarts caused by too long startup time and the control unit failing to send a dog feeding signal in time when using a complex operating system (such as Linux), and ensuring that the device can operate normally after restarting.

[0016] 2. By adjusting the resistance and capacitance of the delay circuit, the time of the voltage signal sent to the PFI can be flexibly changed to meet the needs of different devices.

[0017] 3. The present invention also realizes a power-off reset function through a controlled circuit, and realizes reliable and rapid power discharge through resistors R1 and R6. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the schematic diagram of the watchdog reset time adjustment circuit; Figure 2 A schematic diagram of a voltage conversion circuit for converting a front-stage power supply into a watchdog power supply; Figure 3 This is a topological diagram of the power supply relationship. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0020] like Figure 3 In the electricity consumption information collection terminal and the electric energy meter, the front-stage power supply (+5V) is connected to the rear-stage power supply (5V) through the controlled circuit. The rear-stage power supply is responsible for supplying power to the control unit, functional modules, etc. At the same time, the front-stage power supply also supplies power to the watchdog circuit. The watchdog circuit controls the controlled circuit.

[0021] like Figure 2 The front-stage power supply is stepped down through a voltage conversion circuit composed of an LDO step-down chip D2, capacitors C5, C6 and C7. The voltage output terminal OUT of the LDO step-down chip D2 is connected to the watchdog power supply terminal VDOG. Capacitors C5 and C6 are used for decoupling, and capacitor C7 is an output bypass capacitor.

[0022] like Figure 1 The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter in this embodiment includes a watchdog chip D1. This embodiment takes the 706 series watchdog as an example, and the watchdog chip D1 has 8 pins: (1) Manual reset input pin MR: Normally, it is a high-impedance input. When a low-level signal is input, the pin RST of the watchdog chip is triggered to send a reset signal.

[0023] (2) Power supply pin VCC: connected to the positive pole of the power supply. In this embodiment, it is connected to the watchdog power supply terminal VDOG.

[0024] (3) Ground pin GND: ground.

[0025] (4) Voltage monitoring input pin PFI: used to monitor voltage signals.

[0026] (5) Voltage monitoring output pin PFO: When the voltage at pin PFI is lower than 1.25V, pin PFO outputs a low level, indicating a power failure or performing other operations.

[0027] (6) Watchdog input pin WDI: receives the watchdog feeding signal from the control unit.

[0028] (7) Reset signal output pin RST: When pin MR is pulled low, pin RST outputs a low-level reset signal, disconnecting the downstream power supply through the controlled circuit to achieve restart. By default, this signal only lasts for 200ms.

[0029] (8) Watchdog output pin WDO: When pin WDI does not receive a watchdog feeding signal within 1.6 seconds, pin WDO sends a low-level alarm signal to trigger other operations.

[0030] The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter also includes a delay circuit connected between the watchdog power supply terminal VDOG and the reset signal output pin RST of the watchdog chip D1, and the voltage output end of the delay circuit is connected to the voltage monitoring input pin PFI of the watchdog chip D1.

[0031] The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter also includes a diode V4, the anode of the diode V4 is connected to the manual reset input pin MR of the watchdog chip D1, and the cathode is connected to the voltage monitoring output pin PFO of the watchdog chip D1.

[0032] When the watchdog chip D1 sends a reset signal, a voltage signal (i.e., a voltage signal lower than 1.25V) for triggering a voltage alarm is sent to the voltage monitoring input pin PFI of the watchdog chip D1 through a delay circuit. At this time, the pin PFO outputs a low level, and then pulls down the pin MR, so that the watchdog chip is always in a reset state within this time, thereby achieving the purpose of extending the duration of the reset signal.

[0033] Specifically, the delay circuit includes a resistor R9, a capacitor C2 and a resistor R8 connected in sequence between the watchdog power supply terminal VDOG and the reset signal output pin RST of the watchdog chip D1. The connection point between the resistor R9 and the capacitor C2 is the voltage output terminal of the delay circuit.

[0034] Furthermore, the watchdog output pin WDO of the watchdog chip D1 is connected to the manual reset input pin MR of the watchdog chip D1 through the resistor R10.

[0035] Furthermore, the delay circuit also includes a diode V3, the anode of the diode V3 is connected to the voltage monitoring input pin PFI of the watchdog chip D1, and the cathode is connected to the watchdog power supply terminal VDOG, so that after the entire system loses power, the voltage across the capacitor C2 can be quickly discharged to 0V, ensuring reliable reset of the system.

[0036] When powered on, after the supply voltage VDOG of the watchdog chip is generated, because the voltage across the capacitor C2 cannot change suddenly, the pin PFI and the pin RST reset pin are both low level. At this time, the delay circuit acts as a slow charging circuit, and the voltage at the pin PFI rises slowly from 0V. Before it rises to 1.25V, the pin PFO always outputs a low level (equivalent to a voltage alarm). Because the pin PFO is connected to the pin MR through the diode V4, the pin MR is pulled low, and the watchdog chip is always in a reset state. The pin RST will continue to maintain a low level and is not limited by 200ms. After charging for a period of time (assuming that the duration is T), the pin PFI voltage is higher than 1.25V, and the pin PFO flips to output a high level. At this time, the pin MR level begins to follow the pin WDO. Because there is no dog feeding signal at this time, the pin WDO is low, so the watchdog is activated, and the pin RST outputs a reset low level for 200ms and then becomes a high level. Therefore, during this period, the time that the pin RST maintains a low level is actually T+200ms. By adjusting the parameters of resistors R8, R9, and C2, the time it takes for the PFI voltage to reach 1.25V can be changed, thereby achieving the purpose of externally adjusting the duration of the reset signal of the watchdog chip.

[0037] When the reset is triggered through pins WDO and MR because the dog feeding signal is not received for a long time during normal operation, pin RST outputs a low level first. At this time, capacitor C2 discharges to pin RST through resistor R8, causing pin PFI to drop rapidly to 0V (this time can be ignored). Then, the circuit starts to charge capacitor C2 in the same state and change process as when powered on. The duration of the reset signal is also T+200ms.

[0038] Furthermore, the watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter also includes a button SW1 and a resistor R11, and the manual reset input pin MR of the watchdog chip D1 is grounded through the resistor R11 and the button SW1 in sequence. When the button SW1 is pressed, the pin MR is pulled low, the watchdog chip is activated, and the pin RST outputs a reset low-level signal. The reset process is the same as the above, and the signal duration is T+200ms.

[0039] Furthermore, the manual reset input pin MR of the watchdog chip D1 is also grounded through a capacitor C4. The capacitor C4 is connected in parallel for de-jittering to prevent the pin MR from being disturbed.

[0040] The controlled circuit is connected between the positive terminal of the front-stage power supply and the positive terminal of the rear-stage power supply. The reset signal output pin RST of the watchdog chip D1 is connected to the control terminal of the controlled circuit.

[0041] The controlled circuit includes a PMOS tube V1 and a triode V50, wherein the source of the PMOS tube V1 is connected to the positive terminal of the front-stage power supply, and the drain is connected to the positive terminal of the rear-stage power supply. The control end of the controlled circuit is connected to the triode V50, and the triode V50 is used to control the conduction and cut-off of the PMOS tube V1 according to the reset signal of the watchdog chip D1.

[0042] Specifically, the controlled circuit further includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7 and a capacitor C1.

[0043] The watchdog power supply terminal VDOG is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the base of the transistor V50 through the resistor R4. R5 is connected between the base and emitter of the transistor V50, and the emitter of the transistor V50 is grounded.

[0044] The collector of the transistor V50 is connected to the gate of the PMOS transistor V1 through the resistor R2, and is also connected to the source of the PMOS transistor V1 through the resistor R3. The capacitor C1 is also connected between the gate and source of the PMOS transistor V1.

[0045] When the pin RST sends a low-level reset signal, the transistor V50 is turned off, the gate of the PMOS tube V1 is high and turned off, and the power supply of the subsequent stage stops. At this time, the functional module and the control unit are powered off. When the reset signal is eliminated, when the voltage at the pin RST of the watchdog chip D1 is pulled up by the pull-up resistor R7, the transistor V50 is turned on, the gate of the PMOS tube V1 is low and turned on, and the power supply of the subsequent stage is restored, thereby restarting the device. The resistor R2 and the capacitor C1 form a slow-start circuit, which can reduce the impact of the PMOS tube V1 on the previous stage power supply when it is turned on.

[0046] Furthermore, the controlled circuit also includes an NMOS tube V2, a resistor R1 and a resistor R6. The collector of the transistor V50 is connected to the gate of the NMOS tube V2, the source of the NMOS tube V2 is grounded, the drain is connected to the positive terminal of the rear-stage power supply through the resistor R1, and is connected to the positive terminal of the front-stage power supply through the resistor R5. When the pin RST sends a low-level reset signal, while the controlled circuit turns off the rear-stage power supply, the NMOS tube V2 is turned on, and the rear-stage power supply and the front-stage power supply are quickly discharged through the resistors R1 and R6.

[0047] It should be noted that it is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. The scope of the present invention is defined by the claims rather than the above description.

Claims

1. A watchdog reset time adjustment circuit for an electricity consumption information collection terminal and an electric energy meter, comprising a watchdog chip D1 and a watchdog power supply terminal VDOG connected to a power pin VCC of the watchdog chip D1, characterized in that: It also includes a delay circuit connected between the watchdog power supply terminal VDOG and the reset signal output pin RST of the watchdog chip D1, and the voltage output terminal of the delay circuit is connected to the voltage monitoring input pin PFI of the watchdog chip D1; when the watchdog chip D1 sends a reset signal, a voltage signal for triggering a voltage alarm with a certain duration is sent to the voltage monitoring input pin PFI of the watchdog chip D1 through the delay circuit; The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter also includes a diode V4, the anode of the diode V4 is connected to the manual reset input pin MR of the watchdog chip D1, and the cathode is connected to the voltage monitoring output pin PFO of the watchdog chip D1.

2. The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter according to claim 1, characterized in that: The delay circuit includes a resistor R9, a capacitor C2 and a resistor R8 which are sequentially connected between the watchdog power supply terminal VDOG and the reset signal output pin RST of the watchdog chip D1; the connection point between the resistor R9 and the capacitor C2 is the voltage output terminal of the delay circuit.

3. The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter as claimed in claim 2, characterized in that: The delay circuit further includes a diode V3, the anode of the diode V3 is connected to the voltage monitoring input pin PFI of the watchdog chip D1, and the cathode of the diode V3 is connected to the watchdog power supply terminal VDOG.

4. The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter as claimed in claim 1, characterized in that: The watchdog output pin WDO of the watchdog chip D1 is connected to the manual reset input pin MR of the watchdog chip D1 through the resistor R10.

5. The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter as claimed in claim 1, characterized in that: It also includes a button SW1 and a resistor R11. The manual reset input pin MR of the watchdog chip D1 is grounded through the resistor R11 and the button SW1 in sequence.

6. The power consumption information collection terminal and the watchdog reset time adjustment circuit of the electric energy meter according to claim 1, characterized in that: The manual reset input pin MR of the watchdog chip D1 is also grounded through a capacitor C4.

7. The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter according to any one of claims 1 to 6, characterized in that: It also includes a controlled circuit connected between the positive terminal of the front-stage power supply and the positive terminal of the rear-stage power supply, and the reset signal output pin RST of the watchdog chip D1 is connected to the control terminal of the controlled circuit.

8. The power consumption information collection terminal and the watchdog reset time adjustment circuit of the electric energy meter as claimed in claim 7, characterized in that: The controlled circuit includes a PMOS tube V1 and a triode V50, wherein the source of the PMOS tube V1 is connected to the positive terminal of the front-stage power supply, and the drain is connected to the positive terminal of the rear-stage power supply; The control end of the controlled circuit is connected to the transistor V50, and the transistor V50 is used to control the PMOS tube V1 to be turned on and off according to the reset signal of the watchdog chip D1.

9. The power consumption information collection terminal and the watchdog reset time adjustment circuit of the electric energy meter as claimed in claim 8, characterized in that: The controlled circuit further includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7 and a capacitor C1; The watchdog power supply terminal VDOG is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the base of the transistor V50 through the resistor R4; R5 is connected between the base and emitter of the transistor V50, and the emitter of the transistor V50 is grounded; The collector of the transistor V50 is connected to the gate of the PMOS tube V1 through the resistor R2, and is also connected to the source of the PMOS tube V1 through the resistor R3; the capacitor C1 is also connected between the gate and source of the PMOS tube V1.

10. The watchdog reset time adjustment circuit of the power consumption information collection terminal and the power meter according to claim 9, characterized in that: The controlled circuit also includes an NMOS tube V2, a resistor R1 and a resistor R6; The collector of the transistor V50 is connected to the gate of the NMOS transistor V2, the source of the NMOS transistor V2 is grounded, the drain is connected to the positive terminal of the subsequent power supply through the resistor R1, and is connected to the positive terminal of the previous power supply through the resistor R5.

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