Chip verification platform, system, method and device and medium

Abstract

The invention discloses a chip verification platform, system, method and device and a medium, and belongs to the technical field of communication. Wherein the chip verification platform comprises an image signal processor ISP simulation unit, the ISP simulation unit is used for simulating behaviors of each function unit of the ISP to obtain a simulation result, and the simulation result is used for verifying the system performance of the ISP; wherein the ISP simulation unit is obtained by carrying out behavior level abstract processing on each functional unit of the ISP; and the ISP simulation unit is connected with a second data interface of an application processor in the electronic equipment through the first data interface so as to establish a data transmission path between the chip verification platform and the application processor.

Description

Technical Field

[0001] The present application belongs to the field of communication technology, and specifically relates to a chip verification platform, system, method, device and medium. Background Art

[0002] At present, the shooting function is one of the most important functions of electronic devices such as mobile phones, and the computing power of the application processor (AP) responsible for image processing is the basis for improving the overall shooting effect and performance. In some application scenarios, plug-in chips can be used in electronic devices, that is, additional image processing chips can be added to improve the overall computing power of the platform to superimpose more image processing algorithms, thereby improving the shooting image effect. In order to ensure that the performance of the plug-in chip system meets the product design requirements, it is usually necessary to test and verify the performance of the plug-in chip system during the design and development stage of the product.

[0003] In existing system verification platforms, electronic design automation (EDA) verification environments are usually used. However, since the actual operating speed of these verification platforms is usually only one ten-thousandth of the actual chip system, it is difficult to meet the performance requirements of system evaluation, which leads to poor accuracy of verification results. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a chip verification platform, system, method, device and medium, which can solve the problem that the existing chip verification schemes are difficult to meet the performance requirements of system evaluation and the accuracy of verification results is poor.

[0005] In a first aspect, an embodiment of the present application provides a chip verification platform, including:

[0006] An image signal processor ISP simulation unit, the ISP simulation unit is used to simulate the behavior of each functional unit of the ISP to obtain a simulation result, and the simulation result is used to verify the system performance of the ISP; wherein the ISP simulation unit is obtained by performing behavioral level abstract processing on each functional unit of the ISP;

[0007] A first data interface, through which the ISP simulation unit is connected to a second data interface of an application processor in an electronic device, so as to establish a data transmission path between the chip verification platform and the application processor.

[0008] In a second aspect, an embodiment of the present application provides a chip verification system, including an image sensor, an application processor, and the chip verification platform described in the first aspect, wherein the image sensor is connected to the application processor;

[0009] A first data interface in the chip verification platform is connected to a corresponding second data interface in the application processor to establish a data transmission path between the chip verification platform and the application processor;

[0010] Wherein, the image sensor is used to collect raw image data;

[0011] The application processor is used to transmit first image data to the chip verification platform, wherein the first image data is the original image data, or is image data after processing the original image data;

[0012] The first data interface is used to receive the first image data;

[0013] The ISP simulation unit in the chip verification platform is used to process the first image data to obtain second image data;

[0014] The first data interface is also used to transmit the second image data and the operation status data of the ISP simulation unit to the application processor;

[0015] The application processor is further configured to verify the system performance of the ISP according to the second image data and the operation status data.

[0016] In a third aspect, an embodiment of the present application provides a chip verification method, including:

[0017] Collecting raw image data through an image sensor;

[0018] Transmitting first image data to the chip verification platform through an application processor, wherein the first image data is the original image data, or is image data after processing the original image data;

[0019] receiving the first image data through a first data interface in the chip verification platform; processing the first image data through an ISP simulation unit in the chip verification platform to obtain second image data; and transmitting the second image data and the operating status data of the ISP simulation unit to the application processor through the first data interface;

[0020] The system performance of the ISP is verified by the application processor based on the second image data and the operating status data.

[0021] In a fourth aspect, an embodiment of the present application provides a chip verification device, including:

[0022] An image sensor, used to collect raw image data;

[0023] An application processor, configured to transmit first image data to a chip verification platform, wherein the first image data is the original image data, or is image data after processing the original image data;

[0024] A chip verification platform, comprising a first data interface and an ISP simulation unit, wherein the chip verification platform is used to receive the first image data through the first data interface; process the first image data through the ISP simulation unit to obtain second image data; and transmit the second image data and the running status data of the ISP simulation unit to the application processor through the first data interface;

[0025] The application processor is further configured to verify the system performance of the ISP according to the second image data and the operation status data.

[0026] In a fifth aspect, an embodiment of the present application provides a chip verification system, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0027] In a sixth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0028] In a seventh aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.

[0029] In an eighth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the first aspect.

[0030] In an embodiment of the present application, a chip verification platform includes: an image signal processor ISP simulation unit, the ISP simulation unit is used to simulate the behavior of each functional unit of the ISP to obtain a simulation result, and the simulation result is used to verify the system performance of the ISP; wherein the ISP simulation unit is obtained by performing behavioral-level abstract processing on each functional unit of the ISP; a first data interface, the ISP simulation unit is connected to a second data interface of an application processor in an electronic device through the first data interface to establish a data transmission path between the chip verification platform and the application processor.

[0031] A chip verification system includes an image sensor, an application processor and the above-mentioned chip verification platform, wherein the image sensor is connected to the application processor; a first data interface in the chip verification platform is connected to a corresponding data interface in the application processor to establish a data transmission path between the chip verification platform and the application processor; wherein the image sensor is used to collect original image data; the application processor is used to transmit first image data to the chip verification platform, wherein the first image data is the original image data, or is image data after processing the original image data; the first data interface is used to receive the first image data; the ISP simulation unit in the chip verification platform is used to process the first image data to obtain second image data; the first data interface is also used to transmit the second image data and the operating status data of the ISP simulation unit to the application processor; the application processor is also used to verify the system performance of the ISP based on the second image data and the operating status data.

[0032] The chip verification method includes: collecting original image data through an image sensor; transmitting first image data to a chip verification platform through an application processor, wherein the first image data is the original image data, or is image data after processing the original image data; receiving the first image data through a first data interface in the chip verification platform; and processing the first image data through an ISP simulation unit in the chip verification platform to obtain second image data; and transmitting the second image data and the operating status data of the ISP simulation unit to the application processor through the first data interface; and verifying the system performance of the ISP based on the second image data and the operating status data by the application processor.

[0033] The embodiment of the present application designs a verification platform and system for the system performance of an external ISP chip. Specifically, by designing the system paths and interfaces of the external ISP chip and performing behavioral-level abstract processing on the entire ISP chip function, the logic scale and processing time of the entire ISP chip can be reduced, so that the verification platform can meet the performance requirements of the ISP chip system evaluation and improve the verification efficiency and the accuracy of the verification results. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of the chip verification platform provided in the embodiment of the present application;

[0035] Figure 2 It is a framework design flow chart of the chip verification system provided in the embodiment of the present application;

[0036] Figure 3It is a schematic diagram of the structure of a chip verification system with a DUMP / LOAD function provided in an embodiment of the present application;

[0037] Figure 4 is a flowchart of a chip verification method provided in an embodiment of the present application;

[0038] Figure 5 is a schematic diagram of the structure of a chip verification device provided in an embodiment of the present application;

[0039] Figure 6 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0040] Figure 7 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0042] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0043] In order to make the embodiments of the present application clearer, the relevant technical knowledge involved in the embodiments of the present application is further described in detail below, and the purpose of the embodiments of the present application is briefly introduced, as follows:

[0044] AP: Application Processor, application processor;

[0045] ISP: Image Signal Processor, image signal processing unit;

[0046] MIPI: Mobile Industry Processor Interface, mobile industry processor interface;

[0047] FPGA: Field Programmable Gate Arrays, field programmable logic gate array;

[0048] EDA: Electronic Design Automation, electronic design automation;

[0049] PCIE: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard;

[0050] SDIO: Secure Digital Input and Output, secure digital input and output;

[0051] CSI: Camera Serial Interface, camera serial interface;

[0052] DSI: Display Serial Interface, display serial interface;

[0053] DSP: Digital Signal Processing, digital signal processor;

[0054] DDR: Double Data Rate Synchronous Dynamic Random Access Memory, high-performance double data rate synchronous dynamic random access memory.

[0055] At present, multimedia systems, especially functions such as video / image shooting, are very important to electronic devices such as smart phones, tablet computers, and car displays. The computing power of the multimedia computing platform is the basis for improving the overall effect and performance. Therefore, mobile phone and other multimedia device manufacturers improve the overall computing power of the platform by developing their own ISP processing chips based on AP chips to superimpose more image processing algorithms, thereby improving the system's imaging effect and performance.

[0056] At the same time, as a co-processing accelerator of the system-on-chip (SOC), the design of the system path of the ISP chip, namely the AP and ISP control path, such as command issuance, neural network weight parameter download, synchronous information interaction, etc., and the AP and ISP data path, such as multimedia raw image data reception and transmission, intermediate image processing results, etc., plays a vital role in the performance and power consumption of the overall system. Therefore, in the specification definition, system solution design and system acceptance stages of the self-developed ISP chip, it is particularly important to build a high-performance prototype verification system based on the system path.

[0057] Among the existing verification platforms, whether it is the EDA verification environment or the full-featured FPGA prototype verification environment provided by chip design companies, these platforms cannot meet the system performance requirements because the actual operating frequency of these platforms is only one ten-thousandth of the actual chip.

[0058] To this end, the embodiment of the present application proposes a behavioral-level system verification platform and system based on a high-performance ISP chip. The solution can adopt a high-performance FPGA platform, and the platform integrates high-performance interfaces such as MIPI, PCIE and SDIO, and its performance is close to that of the AP platform; it also integrates hardware processing units such as a central processing unit (CPU) and DSP, whose actual computing power is greater than that of the ISP chip, and a DDR large-capacity cache; and it can also integrate a large-capacity programmable logic unit.

[0059] The embodiments of the present application can perform behavioral-level abstraction and modeling of the entire ISP chip function based on the system path and interface design of the ISP chip and the linear communication model (pipeline) inside the ISP chip on the basis of a high-performance FPGA platform, and improve the parallelism of functional unit processing to reduce the logic scale and processing time of the entire ISP chip, so as to meet the performance requirements of system evaluation and improve verification efficiency and accuracy.

[0060] The chip verification platform, system and method provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0061] See also Figure 1 , Figure 1 A schematic diagram of the framework structure of the chip verification platform provided in the embodiment of the present application is shown in FIG. Figure 1 As shown, the chip verification platform 100 includes:

[0062] An image signal processor ISP simulation unit 101, wherein the ISP simulation unit 101 is used to simulate the behavior of each functional unit of the ISP to obtain a simulation result, and the simulation result is used to verify the system performance of the ISP; wherein the ISP simulation unit 101 is obtained by performing behavioral level abstract processing on each functional unit of the ISP;

[0063] The first data interface 102 , the ISP simulation unit 101 is connected to the second data interface 210 of the application processor 200 in the electronic device through the first data interface 102 , so as to establish a data transmission path between the chip verification platform 100 and the application processor 200 .

[0064] In the embodiment of the present application, considering that the operation speed of the general verification platform is far lower than the operation speed of the actual chip, the function of the ISP chip to be tested is subjected to behavioral level abstraction processing, specifically, each functional unit of the ISP is subjected to behavioral level abstraction and modeling processing, and the ISP system behavioral level circuit unit is obtained, such as the ISP sensor front end (Sensorfront end, SFE), high dynamic range imaging (High Dynamic Range Imaging, HDR) and other functional units, that is, the ISP simulation unit 101, and the ISP simulation unit 101 is deployed to the verification platform, such as the FPGA platform; so that during verification, the ISP simulation unit 101 can be used to simulate the behavior of each functional unit of the ISP, such as simulating the ISP noise reduction function, image synthesis function and other behaviors, and the ISP function and system performance can be evaluated or verified through the simulation results of the behavior of each functional unit of the ISP, including image processing results, processing delay, power consumption, etc. Among them, the behavioral level abstraction can be specifically understood as downgrading and simplifying the functional complexity of the ISP, which can reduce the logic scale and processing time of the entire ISP chip.

[0065] At the same time, the system path and interface requirements of the ISP chip in actual applications can be referred to, and the system path and interface of the chip verification platform can be designed accordingly to establish a pipeline communication model inside the ISP chip.

[0066] In this way, you can build Figure 1 The ISP chip verification platform shown.

[0067] Specifically, the first data interface 102 may include different types of interfaces such as an interface for transmitting image data, an interface for transmitting configuration information and interactive instructions, and an interface for reporting debugging data and performance indicators. Correspondingly, the application processor 200, i.e., the AP platform, is also provided with corresponding interfaces of various types. In this way, the chip verification platform 100 and the application processor 200 in the electronic device can be connected via the corresponding first data interface 102 and the second data interface 210, thereby establishing a data transmission path between the chip verification platform 100 and the application processor 200.

[0068] In this way, the chip verification platform can be connected to the AP of the electronic device to form a chip prototype verification system, and the entire system path can be opened. According to the ISP simulation unit 101 simulating the behavior of each functional unit of the ISP, a simulation result can be obtained, which specifically includes the operation status data and processing result data of the ISP simulation unit 101. The system performance of the ISP can be verified through the simulation result, such as processing delay, processing rate, power consumption, achievable frame rate, etc. The function of the ISP can also be verified, such as verifying whether the functions of each module of the ISP can be realized and whether it can work normally. It should be noted that the hardware structure and software program of the ISP simulation unit 101 can also be debugged according to each test result until the performance of the ISP meets the design requirements.

[0069] It should also be noted that if Figure 1 As shown, the AP platform of the electronic device may also be integrated with chips such as ISP processing, CPU, and neural processing unit (NPU).

[0070] Optionally, the first data interface 102 includes a first MIPI11 and a second MIPI12, and the second data interface 210 includes a third MIPI21 and a fourth MIPI22; the first MIPI11 is connected to the third MIPI21, and the second MIPI12 is connected to the fourth MIPI22;

[0071] Among them, the first MIPI11 is used to receive image data transmitted by the application processor 200;

[0072] The second MIPI 12 is used to transmit the image data processed by the ISP simulation unit 101 to the application processor 200 .

[0073] like Figure 1 As shown, both the chip verification platform 100 and the application processor 200 may be integrated with a MIPI interface, and the chip verification platform 100 and the application processor 200 may transmit camera (Sensor) data, i.e., image data, through the MIPI interface. Specifically, the third MIPI 21 on the application processor 200 may be a DSI interface, and the fourth MIPI 22 on the application processor 200 may be a CSI interface, both of which are used to transmit image data.

[0074] In this way, the application processor 200 can transmit the image data to the chip verification platform 100 through the third MIPI21 such as the DSI interface, and the chip verification platform 100 is used to receive the image data transmitted by the application processor 200 through the first MIPI11. Specifically, the application processor 200 can transmit the original image data that has not been processed by the application processor 200 to the chip verification platform 100, that is, the original image data collected by the camera; the application processor 200 can also transmit the processed image data to the chip verification platform 100, that is, the application processor 200 can first perform certain processing on the original image data of the camera, and then transmit it to the chip verification platform 100.

[0075] The image data received by the chip verification platform 100 through the first MIPI11 can be transmitted to the ISP simulation unit 101, and the received image data is further processed by the ISP simulation unit 101 to simulate the ISP's behavior of processing the image data. The processing result data is transmitted to the application processor 200 through the second MIPI12, and the application processor 200 receives the processing result data through the fourth MIPI22 such as the CSI interface, so that the application processor 200 can verify whether the various functions of the ISP simulation unit 101 are operating normally and whether they can meet the functional design requirements of the ISP chip based on the processing result data.

[0076] Optionally, the first data interface 102 further includes a secure digital input and output SDIO interface 13 and a high-speed serial computer expansion bus standard PCIE interface 14;

[0077] The SDIO interface 13 is used to send meta information of the chip verification platform 100 to the application processor 200;

[0078] The PCIE interface 14 is used to send system debugging data to the application processor 200 .

[0079] like Figure 1 As shown, the chip verification platform 100 may also be integrated with an SDIO interface 13 and a PCIE interface 14. Correspondingly, the application processor 200 is also integrated with an SDIO interface and a PCIE interface, and the SDIO interface 13 is connected to the SDIO interface on the application processor 200, and the PCIE interface 14 is connected to the PCIE interface on the application processor 200.

[0080] The chip verification platform 100 and the application processor 200 can transmit platform meta information and some algorithm configuration information through the SDIO interface. Meta information generally refers to metadata about code or data, which provides additional information about the code or data itself, such as creation date, author, version, etc. This information is very important for understanding, maintaining and debugging the code. That is, the chip verification platform 100 and the application processor 200 can perform system debugging by exchanging meta information, and can transmit system debugging data through the PCIE interface.

[0081] That is to say, in some embodiments, the chip verification platform 100 is integrated with basic interfaces, including PCIE interface, SDIO interface and high-speed CSI and DSI interfaces. The AP can read the meta information of the prototype platform through the SDIO configuration to complete the information flow interaction; the AP can send the image and video stream information to the prototype platform through the MIPI interface for behavioral level processing.

[0082] The chip verification platform 100 and the application processor 200 can transmit different data information through different types of data interfaces, which can facilitate the platform to extract different types of data.

[0083] Optionally, the chip verification platform 100 is an FPGA prototype verification platform.

[0084] In some embodiments, a high-performance FPGA platform can be used as the ISP chip behavior-level system verification platform. In this way, the high-performance interfaces such as MIPI, PCIE and SDIO integrated on the FPGA platform, as well as the integrated CPU and DSP and other powerful hardware processing units and DDR large-capacity cache can be used to build a good Figure 1 The chip verification platform 100 of the shown architecture ensures higher system performance.

[0085] In order to better explain the design and verification and debugging process of the chip verification platform 100 in the embodiment of the present application, the following is combined with Figure 2 The system framework design flow chart shown is used for explanation, including the following implementation steps:

[0086] 201. Determine the system path design according to the ISP chip application scenario and system specifications;

[0087] 202. Build FPGA hardware platform based on ISP chip interface requirements, mainly including basic interfaces such as MIPI / PCIE / SDIO, as well as CPU, DDR, etc.;

[0088] 203. Determine the system interface data format and AP interaction behavior based on the algorithm model and pipeline of the ISP chip;

[0089] 204. Perform behavioral level abstraction on the functions of the entire ISP pipeline, and implement the corresponding behavioral level circuit using register transfer level (RTL);

[0090] 205. Deploy RTL to the FPGA platform and perform parallel processing and optimization according to the performance of the actual chip;

[0091] 206. Connect in series with the AP system and open up the entire path design to conduct system-level debugging and evaluation.

[0092] The embodiments of the present application effectively improve the efficiency of ISP chip prototype verification and the accuracy of system solution performance and power consumption evaluation.

[0093] Alternatively, if Figure 3 As shown, the chip verification platform 100 also includes:

[0094] Cache unit 103;

[0095] Central processing unit CPU104, CPU104 is used to simulate the software control function of the ISP;

[0096] A data dump / data load function unit 105, wherein the dump function unit is connected to the first data interface 102, the CPU 104 and the cache unit 103 respectively;

[0097] The Dump function unit is used to write the data transmitted by the application processor 200 received through the first data interface 102 into the cache unit 103, and transmit it to the CPU 104 for correctness verification;

[0098] The Load function unit is used to read the algorithm simulation data from the cache unit 103 and transmit the data to the application processor 200 through the first data interface 102 .

[0099] That is, in some embodiments, based on the behavioral-level ISP path of the FPGA prototype system, i.e., the chip verification platform 100, data dump and / or offline material loading functions can be added at key nodes of the path, such as the input / output of the interface, the input and output of the ISP pipeline, and the input and output of the CPU processing, so as to improve the efficiency of system path debugging.

[0100] Among them, the cache unit 103 can adopt a high-performance DDR large-capacity cache to improve data storage efficiency. The CPU 104 is mainly used to realize the software simulation of the ISP chip, that is, the software code on the ISP can be written into the CPU 104 and run to cooperate with the ISP simulation unit 101 to complete the information interaction with the AP and realize the processing of software functions.

[0101] like Figure 3 As shown, the Dump / Load functional unit 105 has established data connection paths with the first data interface 102 such as MIPI, SDIO, PCIE, etc., the CPU 104, and the cache unit 103;

[0102] In specific implementation, the correctness check of input data can be implemented through the Dump function unit, that is, the correctness check of the data sent by the application processor 200 can be performed. For example, for the MIPI interface, the prototype platform can start the Dump function to write the data sent by the AP, that is, the data received by the prototype platform, into the DDR, and output the data to the prototype platform self-test module such as CPU104 to confirm whether it is correct, such as comparing it with the expected data to determine whether the received data is correct.

[0103] Accordingly, the output data loading can be realized through the Load functional unit, that is, the prototype platform can directly load the algorithm simulation material and send it to the AP through the MIPI interface as the data source of the AP. Specifically, the data can be output to the AP according to the performance and data format of the system design, and the system path connection on the AP side can be completed. The behavior of the system path can be truly simulated to complete the function, performance and power consumption evaluation on the AP side.

[0104] In this way, this implementation method improves the efficiency of system problem locating by automatically dumping and detecting the correctness of transmission data at key nodes of the prototype platform system link; by loading algorithm materials, it realizes the simulation of real path data and realizes the evaluation of the function, performance and power consumption of the overall system in the system prototype stage.

[0105] The chip verification platform in the embodiment of the present application includes: an image signal processor ISP simulation unit, the ISP simulation unit is used to simulate the behavior of each functional unit of the ISP to obtain a simulation result, and the simulation result is used to verify the system performance of the ISP; wherein the ISP simulation unit is obtained by performing behavioral-level abstract processing on each functional unit of the ISP; a first data interface, the ISP simulation unit is connected to the second data interface of the application processor in the electronic device through the first data interface to establish a data transmission path between the chip verification platform and the application processor. In this way, the embodiment of the present application designs a verification platform for the system performance of an external ISP chip, specifically by designing the system path and interface of the external ISP chip, and performing behavioral-level abstract processing on the entire ISP chip function, thereby reducing the logical scale and processing time of the entire ISP chip, so that the verification platform can meet the performance requirements of the ISP chip system evaluation, and improve the verification efficiency and the accuracy of the verification results.

[0106] See also Figure 1 and Figure 3 , Figure 1 and Figure 3 A framework diagram of a chip verification system provided in an embodiment of the present application, such as Figure 1 and Figure 3 As shown, the chip verification system includes an image sensor 300, an application processor 200 and the chip verification platform 100 introduced in the above-mentioned embodiment, and the image sensor 300 is connected to the application processor 200;

[0107] The first data interface 102 in the chip verification platform 100 is connected to the corresponding second data interface 210 in the application processor 200 to establish a data transmission path between the chip verification platform 100 and the application processor 200;

[0108] Wherein, the image sensor 300 is used to collect raw image data;

[0109] The application processor 200 is used to transmit first image data to the chip verification platform 100, wherein the first image data is the original image data, or is image data after processing the original image data;

[0110] The first data interface 102 is used to receive the first image data;

[0111] The ISP simulation unit 101 in the chip verification platform 100 is used to process the first image data to obtain second image data;

[0112] The first data interface 102 is also used to transmit the second image data and the operation status data of the ISP simulation unit 101 to the application processor 200;

[0113] The application processor 200 is further configured to verify the system performance of the ISP according to the second image data and the operating status data.

[0114] The operating status data of the above-mentioned ISP simulation unit 101 may include data such as normal or abnormal function, operating speed, processing delay, power consumption, etc. The operating status data can be collected by relevant modules such as CPU104 and then transmitted to the AP platform through the first data interface 102.

[0115] The application processor 200 can test whether the ISP function is normal or verify whether the ISP function meets the design requirements based on the image processing result of the ISP simulation unit 101, i.e., the second image data and the operating status data of the ISP simulation unit 101, and test the system performance of the ISP such as processing rate, latency, power consumption and other indicators, and verify whether these performance indicators meet the design requirements.

[0116] In addition, it should be noted that this embodiment is Figure 1 The specific implementation methods of the system side corresponding to the illustrated embodiment can be found in the relevant introduction of the aforementioned embodiment, and will not be described again here to avoid repetition.

[0117] The chip verification system in the embodiment of the present application includes an image sensor, an application processor and the above-mentioned chip verification platform, wherein the image sensor is connected to the application processor; the first data interface in the chip verification platform is connected to the corresponding second data interface in the application processor to establish a data transmission path between the chip verification platform and the application processor; wherein the image sensor is used to collect original image data; the application processor is used to transmit the first image data to the chip verification platform, wherein the first image data is the original image data, or is the image data after processing the original image data; the first data interface is used to receive the first image data; the ISP simulation unit in the chip verification platform is used to process the first image data to obtain the second image data; the first data interface is also used to transmit the second image data and the operating status data of the ISP simulation unit to the application processor; the application processor is also used to verify the system performance of the ISP based on the second image data and the operating status data. In this way, the embodiment of the present application designs a verification system for the system performance of an external ISP chip, specifically by designing the system paths and interfaces of the external ISP chip, and performing behavioral-level abstract processing on the entire ISP chip function, thereby reducing the logical scale and processing time of the entire ISP chip, so that the verification platform can meet the performance requirements of the ISP chip system evaluation, and improve the verification efficiency and the accuracy of the verification results.

[0118] See also Figure 4 , Figure 4 A flowchart of a chip verification method provided in an embodiment of the present application, such as Figure 1 As shown, the method comprises the following steps:

[0119] Step 401: Collect original image data through an image sensor.

[0120] Step 402: Transmit first image data to a chip verification platform through an application processor, wherein the first image data is the original image data, or is image data after processing the original image data.

[0121] Step 403: receive the first image data through the first data interface in the chip verification platform; process the first image data through the ISP simulation unit in the chip verification platform to obtain second image data; and transmit the second image data and the operating status data of the ISP simulation unit to the application processor through the first data interface.

[0122] Step 404: Verify the system performance of the ISP according to the second image data and the operating status data by the application processor.

[0123] Optionally, the chip verification platform further includes a cache unit, a CPU, a Dump function unit and a Load function unit, the CPU is connected to the cache unit, and the Dump function unit and the Load function unit are connected to the first data interface, the CPU and the cache unit respectively;

[0124] Before the first image data is processed by the ISP simulation unit in the chip verification platform, the method further includes:

[0125] Writing the first image data transmitted by the application processor and received through the first data interface into the cache unit through the Dump function unit, and transmitting the first image data to the CPU for correctness verification;

[0126] Verifying the correctness of the first image data by the CPU;

[0127] The step of processing the first image data by the ISP simulation unit in the chip verification platform to obtain the second image data includes:

[0128] When the first image data passes the correctness verification, the first image data is processed by the ISP simulation unit to obtain second image data;

[0129] Writing the second image data and the operation status data of the ISP simulation unit into the cache unit through the Dump function unit;

[0130] The method further comprises:

[0131] Algorithm simulation data is loaded from the cache unit through the Load function unit and transmitted to the application processor through the first data interface.

[0132] It should be noted that this embodiment is Figure 1 and Figure 3 The implementation method of the method corresponding to the illustrated embodiment can be found in the relevant introduction of the aforementioned embodiment for its specific implementation method. To avoid repetition, it will not be described again here.

[0133] The chip verification method in the embodiment of the present application collects original image data through an image sensor; transmits first image data to a chip verification platform through an application processor, wherein the first image data is the original image data, or is image data after processing the original image data; receives the first image data through the first data interface; and processes the first image data through an ISP simulation unit in the chip verification platform to obtain second image data; and transmits the second image data and the operating status data of the ISP simulation unit to the application processor through the first data interface; and verifies the system performance of the ISP through the application processor based on the second image data and the operating status data.

[0134] The embodiments of the present application effectively improve the efficiency of the self-developed ISP chip prototype verification, the system solution performance, and the accuracy of the power consumption evaluation; by automatically dumping and detecting the correctness of the transmission data at the key nodes of the prototype platform system link, the efficiency of system problem locating is improved; by loading algorithm materials, the simulation of real path data is realized, and the function, performance and power consumption of the overall system are evaluated in the system prototype stage.

[0135] The chip verification method provided in the embodiment of the present application can be executed by a chip verification device. In the embodiment of the present application, the chip verification device provided in the embodiment of the present application is described by taking the chip verification method executed by the chip verification device as an example.

[0136] See also Figure 5 , Figure 5 A schematic diagram of the structure of a chip verification device provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the chip verification device 500 includes:

[0137] Image sensor 501, used to collect raw image data;

[0138] The application processor 502 is used to transmit first image data to the chip verification platform 503, wherein the first image data is the original image data, or is image data after processing the original image data;

[0139] The chip verification platform 503 includes a first data interface and an ISP simulation unit, wherein the chip verification platform is used to receive the first image data through the first data interface; process the first image data through the ISP simulation unit to obtain second image data; and transmit the second image data and the operating status data of the ISP simulation unit to the application processor through the first data interface;

[0140] The application processor 502 is further configured to verify the system performance of the ISP according to the second image data and the operation status data.

[0141] Optionally, the chip verification platform further includes a cache unit, a CPU, a Dump function unit and a Load function unit, the CPU is connected to the cache unit, and the Dump function unit and the Load function unit are connected to the first data interface, the CPU and the cache unit respectively;

[0142] The Dump function unit is used to write the first image data transmitted by the application processor and received through the first data interface into the cache unit, and transmit it to the CPU for correctness verification;

[0143] The CPU is used to verify the correctness of the first image data;

[0144] The ISP simulation unit is used to process the first image data to obtain second image data when the first image data passes the correctness verification;

[0145] The Dump function unit is used to write the second image data and the operation status data of the ISP simulation unit into the cache unit;

[0146] The Load function unit is used to load algorithm simulation data from the cache unit and transmit it to the application processor through the first data interface.

[0147] The chip verification method device in the embodiment of the present application comprises an image sensor for collecting raw image data; an application processor for transmitting the first image data to a chip verification platform, wherein the first image data is the raw image data or the image data after processing the raw image data; the chip verification platform comprises a first data interface and an ISP simulation unit, wherein the chip verification platform is used to receive the first image data through the first data interface; and to process the first image data through the ISP simulation unit to obtain the second image data; and to transmit the second image data and the running status data of the ISP simulation unit to the application processor through the first data interface; and the application processor is also used to verify the system performance of the ISP based on the second image data and the running status data. In this way, the embodiment of the present application designs a verification platform and system for the system performance of an external ISP chip, specifically by designing the system path and interface of the external ISP chip, and performing behavioral level abstract processing on the entire ISP chip function, thereby reducing the logic scale and processing time of the entire ISP chip, so that the verification platform can meet the performance requirements of the ISP chip system evaluation, and improve the verification efficiency and the accuracy of the verification results.

[0148] The chip verification device in the embodiment of the present application can be an electronic device, or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., and the embodiment of the present application is not specifically limited.

[0149] The chip verification device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0150] The chip verification device provided in the embodiment of the present application can achieve Figure 4 The various processes implemented by the method embodiment can achieve the same technical effect, and to avoid repetition, they will not be described here.

[0151] Alternatively, if Figure 6 As shown, an embodiment of the present application also provides a chip verification system 600, including a processor 601 and a memory 602, wherein the memory 602 stores programs or instructions that can be executed on the processor 601, and when the program or instructions are executed by the processor 601, the various steps of the above-mentioned chip verification method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not described here.

[0152] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0153] The embodiment of the present application also provides a chip verification system, including an electronic device and a chip verification platform, wherein: Figure 7 It is a schematic diagram of the hardware structure of the electronic equipment in the chip verification system.

[0154] The electronic device 700 includes but is not limited to: a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, and a processor 710 and other components, wherein the sensor 705 may include an image sensor, and the processor 710 includes an application processor.

[0155] Those skilled in the art will appreciate that the electronic device 700 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 710 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Figure 7 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0156] Wherein, the image sensor is used to collect raw image data;

[0157] The application processor is used to transmit first image data to the chip verification platform, wherein the first image data is the original image data, or is image data after processing the original image data;

[0158] A first data interface in the chip verification platform, used for receiving the first image data;

[0159] The ISP simulation unit in the chip verification platform is used to process the first image data to obtain second image data;

[0160] The first data interface is also used to transmit the second image data and the operation status data of the ISP simulation unit to the application processor;

[0161] The application processor is used to verify the system performance of the ISP according to the second image data and the operation status data.

[0162] Optionally, the chip verification platform further includes a cache unit, a CPU, a Dump function unit and a Load function unit, the CPU is connected to the cache unit, and the Dump function unit and the Load function unit are connected to the first data interface, the CPU and the cache unit respectively;

[0163] The Dump function unit is used to write the first image data transmitted by the application processor and received through the first data interface into the cache unit, and transmit it to the CPU for correctness verification;

[0164] The CPU is used to verify the correctness of the first image data;

[0165] The ISP simulation unit is used to process the first image data to obtain second image data when the first image data passes the correctness verification;

[0166] The Dump function unit is used to write the second image data and the operation status data of the ISP simulation unit into the cache unit;

[0167] The Load function unit is used to load algorithm simulation data from the cache unit and transmit it to the application processor through the first data interface.

[0168] It should be understood that in the embodiment of the present application, the input unit 704 may include a graphics processor (Graphics Processing Unit, GPU) 7041 and a microphone 7042, and the graphics processor 7041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 706 may include a display panel 7061, and the display panel 7061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 707 includes a touch panel 7071 and at least one of other input devices 7072. The touch panel 7071 is also called a touch screen. The touch panel 7071 may include two parts: a touch detection device and a touch controller. Other input devices 7072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0169] The memory 709 can be used to store software programs and various data. The memory 709 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 709 may include a volatile memory or a non-volatile memory, or the memory 709 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 709 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0170] The processor 710 may include one or more processing units; optionally, the processor 710 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 710.

[0171] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned chip verification method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0172] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0173] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned chip verification method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0174] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0175] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned chip verification method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0176] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0177] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0178] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip verification platform, characterized in that: include: An image signal processor ISP simulation unit, the ISP simulation unit is used to simulate the behavior of each functional unit of the ISP to obtain a simulation result, and the simulation result is used to verify the system performance of the ISP; wherein the ISP simulation unit is obtained by performing behavioral level abstract processing on each functional unit of the ISP; A first data interface, through which the ISP simulation unit is connected to a second data interface of an application processor in an electronic device, so as to establish a data transmission path between the chip verification platform and the application processor.

2. The chip verification platform according to claim 1, characterized in that: The first data interface includes a first mobile industry processor interface MIPI and a second MIPI, and the second data interface includes a third MIPI and a fourth MIPI; the first MIPI is connected to the third MIPI, and the second MIPI is connected to the fourth MIPI; Wherein, the first MIPI is used to receive image data transmitted by the application processor; The second MIPI is used to transmit the image data processed by the ISP simulation unit to the application processor.

3. The chip verification platform according to claim 2, characterized in that: The first data interface also includes a secure digital input and output SDIO interface and a high-speed serial computer expansion bus standard PCIE interface; The SDIO interface is used to send metadata meta information of the chip verification platform to the application processor; The PCIE interface is used to send system debugging data to the application processor.

4. The chip verification platform according to claim 1, characterized in that: The chip verification platform also includes: Cache unit; A central processing unit (CPU), the CPU being used to simulate the software control function of the ISP; A data dump function unit is connected to the first data interface, the CPU and the cache unit respectively; the Dump function unit is used to write the data transmitted by the application processor received through the first data interface into the cache unit, and transmit it to the CPU for correctness verification.

5. The chip verification platform according to claim 4, characterized in that: The chip verification platform also includes: A data loading Load functional unit, wherein the Load functional unit is respectively connected to the first data interface, the CPU and the cache unit; the Load functional unit is used to read algorithm simulation data from the cache unit and transmit it to the application processor through the first data interface.

6. A chip verification system, characterized in that: A chip verification platform comprising an image sensor, an application processor and any one of claims 1 to 5, wherein the image sensor is connected to the application processor; The first data interface in the chip verification platform is connected to the second data interface in the application processor to establish a data transmission path between the chip verification platform and the application processor; Wherein, the image sensor is used to collect raw image data; The application processor is used to transmit first image data to the chip verification platform, wherein the first image data is the original image data, or is image data after processing the original image data; The first data interface is used to receive the first image data; The ISP simulation unit in the chip verification platform is used to process the first image data to obtain second image data; The first data interface is also used to transmit the second image data and the operation status data of the ISP simulation unit to the application processor; The application processor is further configured to verify the system performance of the ISP according to the second image data and the operation status data.

7. A chip verification method, characterized in that: The method comprises: Collecting raw image data through an image sensor; Transmitting first image data to the chip verification platform through an application processor, wherein the first image data is the original image data, or is image data after processing the original image data; receiving the first image data through a first data interface in the chip verification platform; processing the first image data through an ISP simulation unit in the chip verification platform to obtain second image data; and transmitting the second image data and the operating status data of the ISP simulation unit to the application processor through the first data interface; The system performance of the ISP is verified by the application processor based on the second image data and the operating status data.

8. The method according to claim 7, characterized in that The chip verification platform also includes a cache unit, a CPU, a Dump function unit and a Load function unit, the CPU is connected to the cache unit, and the Dump function unit and the Load function unit are connected to the first data interface, the CPU and the cache unit respectively; Before the first image data is processed by the ISP simulation unit in the chip verification platform, the method further includes: Writing the first image data transmitted by the application processor and received through the first data interface into the cache unit through the Dump function unit, and transmitting the first image data to the CPU for correctness verification; Verifying the correctness of the first image data by the CPU; The step of processing the first image data by the ISP simulation unit in the chip verification platform to obtain the second image data includes: When the first image data passes the correctness verification, the first image data is processed by the ISP simulation unit to obtain second image data; Writing the second image data and the operation status data of the ISP simulation unit into the cache unit through the Dump function unit; The method further comprises: Algorithm simulation data is loaded from the cache unit through the Load function unit and transmitted to the application processor through the first data interface.

9. A chip verification device, characterized in that: include: An image sensor, used to collect raw image data; An application processor, configured to transmit first image data to a chip verification platform, wherein the first image data is the original image data, or is image data after processing the original image data; A chip verification platform, comprising a first data interface and an ISP simulation unit, wherein the chip verification platform is used to receive the first image data through the first data interface; process the first image data through the ISP simulation unit to obtain second image data; and transmit the second image data and the running status data of the ISP simulation unit to the application processor through the first data interface; The application processor is further configured to verify the system performance of the ISP according to the second image data and the operation status data.

10. A chip verification system, characterized in that: It comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the chip verification method as claimed in claim 7 or 8 are implemented.

11. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the chip verification method as claimed in claim 7 or 8 are implemented.

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