Multi-interface concurrent test device and method
By designing a multi-interface concurrent testing device in IoT chip testing, using the main control test module to control the communication timing of the controlled test module, the problems of long test time and analysis difficulties in the existing technology are solved, and multi-interface concurrent communication is realized Accurate control and quick testing.
Patent Information
- Application Number
- CN202411469012.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-01-07
AI Technical Summary
The prior art cannot accurately control the timing when testing the multi-interface concurrent communication of IoT chips, resulting in a long test time and difficulty in covering all concurrent timings. It is difficult to locate and analyze after problems, and is inefficient in efficiency.
Design a multi-interface concurrent testing device, controls the communication timing between the controlled test module and the unit to be tested through the main control test module, including the data preprocessing module and the result processing module, configures communication information and parameters, and realizes the timing of multiple interfaces Control to ensure the accuracy and efficiency of the test.
It realizes accurate control of multi-interface concurrent communication, completes tests quickly and correctly, simplifies problem positioning and analysis, is highly scalable, and is suitable for multiple interface concurrent scenarios.
Smart Images
Figure CN119271477A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of communication interface testing, and in particular to a multi-interface concurrent testing device and method. Background Art
[0002] In recent years, the Internet of Things technology has developed rapidly. As one of the core components of the Internet of Things, IoT chips and other devices play an increasingly important role in the security of the Internet of Things. Whether the IoT chip is a communication module chip or a security chip, there are more and more types of communication interfaces with various MCUs (Microcontroller Units), including SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver-Transmitter), 7816, TypeA and other interfaces.
[0003] Inevitably, in some application scenarios, multi-interface concurrent communication of IoT chips will be involved, that is, a single chip communicates with MCU1 through one of the interfaces, and communicates with another MCU2 through another interface, and even a third interface communicates with MCU3. In the prior art, when testing the multi-interface concurrent communication function of a chip, a common solution is random collision testing of multiple test modules. However, this solution has two major defects. Defect 1: It is impossible to control the concurrent timing, so it is impossible to accurately cover all timing scenarios of multi-interface concurrent communication, the test time is long, and it is difficult to determine whether all concurrent timings have been covered. Defect 2: It is difficult to locate and analyze the problem after it occurs. Since the timing cannot be controlled, it is difficult to reproduce the error scenario, and the efficiency of analyzing the problem is relatively low.
[0004] Therefore, it is hoped that there will be a new multi-interface concurrent testing device and method that can overcome the above problems. Summary of the invention
[0005] In view of the above problems, an object of the present invention is to provide a multi-interface concurrent testing device and method, so as to accurately control the timing and quickly and correctly implement multi-interface concurrent communication testing.
[0006] According to one aspect of the present invention, there is provided a multi-interface concurrent testing device, comprising:
[0007] A controlled test module, wherein the controlled test module is respectively connected to a first test port and a second test port of the unit to be tested;
[0008] A main control test module, the main control test module is connected to the controlled test module,
[0009] The main control test module controls the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port to control the timing of the communication between the controlled test module and the first test port and the second test port.
[0010] Optionally, the multi-interface concurrent testing device further includes:
[0011] a data preprocessing module, the data preprocessing module being used to configure the communication information and / or communication parameters between the controlled test module and the unit to be tested,
[0012] The communication parameters include an initial delay time between the controlled test module and the unit to be tested and / or a delay time for the end of the test, which is calculated according to the test requirements.
[0013] Optionally, the controlled test module includes a first controlled test submodule and a second controlled test submodule;
[0014] The first end of the first controlled test submodule is connected to the first test port; the second end of the first controlled test submodule is connected to the data preprocessing module to receive communication information and / or communication parameters between the first controlled test submodule and the first test port; the first controlled test submodule stores the received communication information and / or communication parameters;
[0015] The first end of the second controlled test submodule is connected to the second test port; the second end of the second controlled test submodule is connected to the data preprocessing module to receive communication information and / or communication parameters between the second controlled test submodule and the second test port; the second controlled test submodule stores the received communication information and / or communication parameters.
[0016] Optionally, the multi-interface concurrent testing device further includes:
[0017] A result processing module is used to obtain the communication results between the controlled test module and the first test port and the second test port; the result processing module compares the communication result with the expected result to obtain the test result.
[0018] According to another aspect of the present invention, a multi-interface concurrent testing method is provided, comprising the following steps:
[0019] Establishing connections between the controlled test module and the first test port and the second test port of the unit to be tested respectively;
[0020] Establishing a connection between a main control test module and the controlled test module;
[0021] The main control test module controls the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port to control the timing of the communication between the controlled test module and the first test port and the second test port.
[0022] Optionally, the multi-interface concurrent testing method further includes the following steps:
[0023] Obtaining communication results between the controlled test module and the first test port and the second test port;
[0024] The communication result is compared with the expected result to obtain a test result.
[0025] Optionally, the multi-interface concurrent testing method further includes the following steps:
[0026] configuring the communication information and / or communication parameters between the controlled test module and the unit to be tested,
[0027] The communication parameters include an initial delay time between the controlled test module and the unit to be tested and / or a delay time for the end of the test, which is calculated according to the test requirements.
[0028] Optionally, the multi-interface concurrent testing method further includes the following steps:
[0029] Configure a first data flow interacting between the controlled test module and the first test port, and configure a second data flow interacting between the controlled test module and the second test port, wherein at least a portion of the first data flow is used for testing the first test port, and at least a portion of the second data flow is used for testing the second test port;
[0030] Based on at least one of the command transmission time, the processing time of the first data stream and / or the second data stream, and the default delay time when sending data to the first test port and / or the second test port, calculate the initial delay time corresponding to the first test port and / or the second test port in the initial state of the multi-interface concurrent timing.
[0031] Optionally, the multi-interface concurrent testing method further includes the following steps:
[0032] Setting the interval time for the main control test module to control the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port;
[0033] The tests were performed at different time intervals.
[0034] Optionally, the accuracy of the timing of the communication between the controlled test module and the first test port and the second test port is determined according to the highest clock of the master test module and the controlled test module;
[0035] On the basis of the initial interval time, the time is increased or decreased by a set step size to obtain the different interval time.
[0036] The multi-interface concurrent testing device and method provided by the present invention, the main control test module controls the communication with the first test port and / or the second test port through the controlled test module, realizes the control of the timing of the communication between the first test port and the second test port, can accurately control the timing, and realize the (chip) multi-interface concurrent communication test quickly and correctly.
[0037] Furthermore, the solution of the present application can be easily expanded to other interfaces and has a wide range of applications.
[0038] Furthermore, the data preprocessing module configures the communication information and / or communication parameters between the controlled test module and the unit to be tested, so as to meet the tests with different requirements.
[0039] Furthermore, the first controlled test submodule connected to the first test port receives and stores communication information and / or communication parameters for the first test port, and the second controlled test submodule connected to the second test port receives and stores communication information and / or communication parameters for the second test port, thereby ensuring the efficiency and accuracy of the test.
[0040] Furthermore, the result processing module obtains the communication result of the test port and compares it with the expected result to obtain the test result, so that test feedback can be obtained in a timely and accurate manner without the problem of difficult and time-consuming reproduction.
[0041] Furthermore, the control step length of the test port is adjustable, which ensures that the test is comprehensive and covers all parallel timings.
[0042] Furthermore, the technical solution provided by the present application solves the problem of testing multi-interface parallel communication and realizes multi-interface concurrent testing; it is capable of controlling the communication timing of multiple interfaces and can construct various concurrent scenarios according to requirements, and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0044] Figure 1 It shows a schematic diagram of the structure of a multi-interface concurrent testing device according to the first embodiment of the present invention;
[0045] Figure 2 A method flow chart of a multi-interface concurrent testing method according to Embodiment 2 of the present invention is shown;
[0046] Figure 3 It shows a schematic diagram of the structure of a multi-interface concurrent testing device according to Embodiment 3 of the present invention;
[0047] Figure 4 A method flow chart of a multi-interface concurrent testing method according to Embodiment 3 of the present invention is shown. DETAILED DESCRIPTION
[0048] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.
[0049] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. Many specific details of the present invention, such as the structure, materials, dimensions, processing technology and techniques of the components are described below to provide a clearer understanding of the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.
[0050] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.
[0051] Figure 1 The structure diagram of the multi-interface concurrent testing device according to the first embodiment of the present invention is shown. Figure 1 As shown, the multi-interface concurrent test device according to the first embodiment of the present invention includes a controlled test module 100, a main control test module 200, a data preprocessing module 300 and a result processing module 400. The controlled test module 100 includes a first controlled test submodule 110 and a second controlled test submodule 120.
[0052] Specifically, the controlled test module 100 is respectively connected to the first test port and the second test port of the unit to be tested (not shown in the figure). Optionally, the unit to be tested includes a chip, the first test port is the SPI interface of the chip, and the second test port is the I2C interface of the chip; the multi-interface concurrent test device according to the embodiment of the present invention is used for concurrent communication testing of multiple interfaces (first test port, second test port, etc.) of the chip. Of course, the present application is not limited to two test sub-modules and two test ports, and may also include a third test port and a third controlled test sub-module connected to the third test port, a fourth test port and a fourth controlled test sub-module connected to the fourth test port, etc.
[0053] The main control test module 200 is connected to the controlled test module 100. The main control test module 200 controls the communication between the controlled test module 100 and the first test port and / or the communication between the controlled test module 100 and the second test port to control the timing of the communication between the controlled test module 100 and the first test port and the second test port.
[0054] In an optional embodiment of the present invention, the multi-interface concurrent test device also includes a data preprocessing module 300. The data preprocessing module 300 is used to configure the communication information and / or communication parameters between the controlled test module 100 and the unit to be tested. Among them, the communication parameters include the initial delay time between the controlled test module and the unit to be tested and / or the delay time for the end of the test calculated according to the test requirements. The communication information includes, for example, the data required for the test, the transmitted data, etc. The communication parameters include, for example, the baud rate, the communication protocol, etc. Optionally, the first end of the first controlled test submodule 110 is connected to the first test port, and the second end of the first controlled test submodule 110 is connected to the data preprocessing module 300 to receive the communication information and / or communication parameters between the first controlled test submodule 110 and the first test port. The first controlled test submodule 110 stores the received communication information and / or communication parameters. The first end of the second controlled test submodule 120 is connected to the second test port, and the second end of the second controlled test submodule 120 is connected to the data preprocessing module 300 to receive the communication information and / or communication parameters between the second controlled test submodule 120 and the second test port. The second controlled test submodule 120 stores the received communication information and / or communication parameters.
[0055] In an optional embodiment of the present invention, the multi-interface concurrent test device further includes a result processing module 400. The result processing module 400 obtains the communication result between the controlled test module 100 and the first test port and the second test port, and compares the communication result with the expected result to obtain the test result.
[0056] Figure 2A method flow chart of a multi-interface concurrent testing method according to Embodiment 2 of the present invention is shown. Figure 2 As shown, the multi-interface concurrent testing method according to the second embodiment of the present invention includes the following steps:
[0057] In step S101, connections are established between the controlled test module and the first test port and the second test port of the unit to be tested respectively;
[0058] Establish a connection between the controlled test module and the first test port of the unit to be tested; establish a connection between the controlled test module and the second test port of the unit to be tested.
[0059] In step S102, a connection is established between the main control test module and the controlled test module.
[0060] A connection is established between the main control test module and the controlled test module to realize the control of the controlled test module by the main control test module.
[0061] In step S103, the main control test module controls the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port to control the timing of the communication between the controlled test module and the first test port and the second test port.
[0062] In an optional embodiment of the present invention, the multi-interface concurrent testing method further includes the following steps:
[0063] Obtaining communication results between the controlled test module and the first test port and the second test port;
[0064] Compare the communication results with the expected results to obtain the test results.
[0065] In an optional embodiment of the present invention, the multi-interface concurrent testing method further includes the following steps:
[0066] Configure the communication information and / or communication parameters between the controlled test module and the unit to be tested, wherein the communication parameters include the initial delay time between the controlled test module and the unit to be tested calculated according to the test requirements and / or the delay time for the end of the test.
[0067] Specifically, a first data stream for interaction between the controlled test module and the first test port is configured, and a second data stream for interaction between the controlled test module and the second test port is configured, wherein at least a portion of the first data stream is used for testing the first test port, and at least a portion of the second data stream is used for testing the second test port.
[0068] Based on at least one of the command (data stream) transmission time, the processing time of the first data stream and / or the second data stream, and the default delay time when sending data to the first test port and / or the second test port, calculate the initial delay time corresponding to the first test port and / or the second test port in the initial state of the multi-interface concurrent timing.
[0069] In an optional embodiment of the present invention, the multi-interface concurrent testing method further includes the following steps:
[0070] The master test module is set to control the interval time of the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port; the tests are respectively performed at different interval times. Optionally, the accuracy of the timing of the communication between the controlled test module and the first test port and the second test port is determined according to the highest clock of the master test module and the controlled test module; on the basis of the initial interval time, the time is incremented or decremented by setting a step length to obtain the different interval time.
[0071] According to the multi-interface concurrent testing device and method of the embodiment of the present invention, the concurrent timing of multiple interfaces can be accurately controlled, various multi-interface concurrent scenarios can be constructed, and various test points can be covered, which can greatly improve the test quality and test efficiency; no test points will be missed, the test time is short, and the analysis of bugs is simpler and clearer; after the bug is found, the problem can be reproduced quickly (a few minutes or faster), which is convenient for problem analysis and improves the efficiency of problem solving; and the solution of the present application is easy to expand and is not limited to the concurrent testing of two interfaces, nor is it limited to 7816 and SWP interfaces, and can support any number of concurrent interfaces, and any interface such as I2C\SPI\SWP\TypeA can be implemented.
[0072] Figure 3 A schematic structural diagram of a multi-interface concurrent testing device according to Embodiment 3 of the present invention is shown. Figure 4 A method flow chart of a multi-interface concurrent testing method according to Embodiment 3 of the present invention is shown.
[0073] Combination Figure 3 and Figure 4 As shown, in a specific embodiment of the present invention, the multi-interface concurrent testing device includes a data preprocessing module (equivalent to Figure 1 The data preprocessing module 300 in the main control test equipment (equivalent to Figure 1 The main control test module 200 in the control test device A (equivalent to Figure 1 The first controlled test submodule 110 in the control unit), the controlled test device B (equivalent to Figure 1 The second controlled test submodule 120 in the Figure 1Result processing module 400 in the embodiment). Among them, the multi-interface concurrent test device is used for testing the tested object (equivalent to the unit to be tested in the first embodiment); the main control test device is connected to the controlled test device A through the trigger pipe (control channel) N1 and the trigger pipe M1, and the main control test device is connected to the controlled test device B through the trigger pipe N2 and the trigger pipe M2; the controlled test device A is connected to the tested object through the interface 1 (equivalent to the first test port in the first embodiment); the controlled test device B is connected to the tested object through the interface 2 (equivalent to the second test port in the first embodiment). When the multi-interface concurrent test device is in use, the data is stored in the controlled test device, and the main control test device uses the corresponding control channel to trigger the communication (communication) between the controlled test device and the tested object at the required timing, so as to control the relative concurrent timing of two interfaces or multiple interfaces. Optionally, the minimum accuracy can be set to a system clock clk of the controlled test device.
[0074] Specifically, the main control test module is used to control the communication timing between other test modules and the tested object, and monitor in real time whether other controlled test modules have completed the expected communication with the controlled test object. Figure 3 As shown, the main control test module controls the communication timing between the test module A and the controlled test module B and the tested object, and monitors in real time through N1 and N2 whether the controlled test module A and the controlled test module B have completed the expected communication with the tested object.
[0075] The controlled test module includes two or more controlled test sub-modules, which can be controlled by the main control test module and can configure the parameters related to the controlled test object, including but not limited to the communication baud rate and communication protection time. The initial delay time with the tested object can be set, and the communication status between the main control module and the tested object can be notified. Figure 3 As shown, the controlled test module A and the controlled test module B can accept the control of the main control test module, and can configure the relevant parameters of the controlled test object, including but not limited to the communication baud rate and the communication protection time; the initial delay time with the tested object can be set, and the communication status between the main control module and the tested object can be notified, and the communication data stream with the tested object can be cached.
[0076] The data preprocessing module is used to prepare the communication data stream between each controlled test module and the tested object, and cache the data stream in the controlled test module; calculate the initial delay time between the controlled test module and the tested object, as well as the delay time for the end of the test according to the test requirements; and configure the communication parameters of the controlled test module.
[0077] The result processing module can obtain the communication result between the controlled test module and the tested object, and compare it with the expected result. If they are consistent, it means that the concurrent sequential communication is normal, and if they are inconsistent, it means that the concurrent sequential communication is abnormal.
[0078] like Figure 4 As shown, the multi-interface concurrent testing method according to an embodiment of the present invention includes the following steps:
[0079] In step S201, the data preprocessing module sets the communication parameters of the controlled test module;
[0080] Configure the communication parameters between each controlled test module and the object under test, such as setting the communication rate and other related parameters between the controlled test module and the object under test.
[0081] In step S202, the data preprocessing module prepares the data stream required for the concurrent test;
[0082] Prepare the data streams that each controlled test module needs to interact with the tested object, which is not limited to one or more commands and can include the data streams expected to be received. The selected data streams are cached in the corresponding controlled test modules. Figure 3 As shown, the controlled test module is prepared to send data stream command_A and response data stream response_A to the tested object interface 1, and the controlled test module B is prepared to send data stream command_B and response response_B to the tested object interface 2. The corresponding data streams are cached in the controlled test module A and the controlled test module B respectively.
[0083] In step S203, the initial delay time and the end time required for the multi-interface concurrent test are calculated;
[0084] Through the command transmission time, the processing time of each data stream, and the default delay time when each controlled test module sends data, the delay time that each controlled test module needs to configure in the initial state under the multi-interface concurrent timing is calculated, and the delay time is allocated to each controlled test module. Specifically, the command_A transmission time Ttrans_A1, the time Tprocess_A for the tested object to process command_A, the transmission time Ttrans_A2 for responding to response_A, and the default time TdelayA for the controlled test module to be triggered to send command_A are calculated. The command_B transmission time Ttrans_B1, the time Tprocess_B for the tested object to process command_B, the transmission time Ttrans_B2 for responding to response_B, and the default time TdelayB for the controlled test module to be triggered to send command_B are calculated. The initial concurrent timing of the control interface can be set to start sending command_A when response_B is completed. Therefore, the initial delay TA_delay of the controlled test module A is set, and the size of TA_delay is TdelayB+ Ttrans_B1+Tprocess_B+ Ttrans_B2+TdelayA+redundancy time T_rec, and the initial delay of the controlled test module B is 0.
[0085] In step S204, the main control test module controls the timing of the controlled test module sending data streams to the object under test through the control pipeline;
[0086] The master test module controls the trigger pipeline state change and controls the timing of each controlled test module sending commands to the object under test. The accuracy of timing control is determined by the highest clock of the master test module and the controlled test module. Figure 3 As shown, the main control test module sets the state changes of the trigger (control) pipeline M1 and the trigger (control) pipeline M2, sets the timing control accuracy to 1us, and the change interval between the trigger (control) pipeline M1 and the trigger (control) pipeline M2 is i us, which controls the timing of the controlled test modules A and B sending commands to the object under test.
[0087] In step S205, the main control module detects whether the controlled test module and the object under test have completed communication through the status pipeline;
[0088] Each controlled test module will set a corresponding trigger (state) pipeline before interacting with the tested object to notify the main control test module that it is communicating with the tested object. When the communication is completed, it will also set a corresponding trigger (state) pipeline to notify the main control test module that the communication is completed. Figure 3As shown, each controlled test module will set trigger (state) pipeline N1 and trigger (state) pipeline N2 before exchanging commands with the tested object, to notify the main control test module that it is communicating with the tested object. After the communication is completed, trigger (state) pipeline N1 and trigger (state) pipeline N2 will also be set to notify the main control test module that the communication is completed.
[0089] In step S206, the communication results are obtained and compared;
[0090] When the main control test module detects that the controlled test module has completed communication with the tested object, if the data prepared in step S202 includes the data returned by the controlled test object, a comparison can be made in the controlled test module, and only the comparison result can be read out. If step S202 does not include the data returned by the controlled test object, the communication result between the controlled test module and the controlled test object can be obtained and compared with the expected result externally. If there is a difference, it indicates failure.
[0091] In step S207, the test is repeated until the test time ends.
[0092] Steps S204 to S206 are executed in a loop. The main control test module sets the trigger (control) pipeline change interval, which increases or decreases with a certain step length until the test end delay time in step S203. If no error occurs in this process, there is no problem with the concurrent communication of the dual interfaces in this case. Optionally, the change interval i us of the trigger pipeline M1 and the trigger pipeline M2 increases with a step length of 1us until the two interfaces complete the concurrency, that is, i is TA_delay+ TdelayA+ Ttrans_A1+Tprocess_A+Ttrans_A2+TdelayA+redundancy time T_rec. If no error occurs in this process, there is no problem with the concurrent communication of the dual interfaces in this case.
[0093] According to the multi-interface concurrent testing device and method of the embodiment of the present invention, the data preprocessing module is first used to obtain the communication parameters and interactive data flows in the concurrent scenarios that need to be tested; the main control test module controls the timing of the corresponding controlled test module to interact with the tested object through the state change of each trigger (control) pipeline; then the trigger (state) pipeline detects that the controlled test module and the tested object have completed communication, and the concurrent test results of this timing can be obtained. This cycle is repeated, and the main control test module sets the control pipeline change interval, increasing or decreasing by a certain step size until all required concurrent scenarios are covered. If no errors occur in this process, it means that there is no problem with the concurrent communication of the dual interfaces in this case. If an error occurs under a certain timing, the data flow and time parameters at this time can be recorded, and the problem can be directly reproduced under this timing for analysis. The solution of the present application can accurately control the interface sending / receiving timing between multiple controlled test modules and the objects under test. The accuracy of the timing control is determined by the highest clock of the main control test module and the controlled test module. The solution of the present application can be accurately controlled, highly efficient, simple and feasible, and can efficiently and quickly complete the testing of multi-interface concurrent communication test functions.
[0094] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0095] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A multi-interface concurrent testing device, comprising: A controlled test module, wherein the controlled test module is respectively connected to a first test port and a second test port of the unit to be tested; A main control test module, the main control test module is connected to the controlled test module, The main control test module controls the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port to control the timing of the communication between the controlled test module and the first test port and the second test port.
2. The multi-interface concurrent testing device according to claim 1, wherein: The multi-interface concurrent testing device also includes: a data preprocessing module, the data preprocessing module being used to configure the communication information and / or communication parameters between the controlled test module and the unit to be tested, The communication parameters include an initial delay time between the controlled test module and the unit to be tested and / or a delay time for the end of the test, which is calculated according to the test requirements.
3. The multi-interface concurrent testing device according to claim 2, wherein: The controlled test module includes a first controlled test submodule and a second controlled test submodule; The first end of the first controlled test submodule is connected to the first test port; The second end of the first controlled test submodule is connected to the data preprocessing module to receive communication information and / or communication parameters between the first controlled test submodule and the first test port; The first controlled test submodule stores received communication information and / or communication parameters; The first end of the second controlled test submodule is connected to the second test port; The second end of the second controlled test submodule is connected to the data preprocessing module to receive communication information and / or communication parameters between the second controlled test submodule and the second test port; the second controlled test submodule stores the received communication information and / or communication parameters.
4. The multi-interface concurrent testing device according to claim 1, wherein: The multi-interface concurrent testing device also includes: A result processing module is used to obtain the communication results between the controlled test module and the first test port and the second test port; the result processing module compares the communication result with the expected result to obtain the test result.
5. A multi-interface concurrent testing method, comprising the following steps: Establishing connections between the controlled test module and the first test port and the second test port of the unit to be tested respectively; Establishing a connection between a main control test module and the controlled test module; The main control test module controls the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port to control the timing of the communication between the controlled test module and the first test port and the second test port.
6. The multi-interface concurrent testing method according to claim 5, wherein: The multi-interface concurrent testing method also includes the following steps: Obtaining communication results between the controlled test module and the first test port and the second test port; The communication result is compared with the expected result to obtain a test result.
7. The multi-interface concurrent testing method according to claim 5, wherein: The multi-interface concurrent testing method also includes the following steps: configuring the communication information and / or communication parameters between the controlled test module and the unit to be tested, The communication parameters include an initial delay time between the controlled test module and the unit to be tested and / or a delay time for the end of the test, which is calculated according to the test requirements.
8. The multi-interface concurrent testing method according to claim 7, wherein: The multi-interface concurrent testing method also includes the following steps: Configure a first data flow interacting between the controlled test module and the first test port, and configure a second data flow interacting between the controlled test module and the second test port, wherein at least a portion of the first data flow is used for testing the first test port, and at least a portion of the second data flow is used for testing the second test port; Based on at least one of the command transmission time, the processing time of the first data stream and / or the second data stream, and the default delay time when sending data to the first test port and / or the second test port, calculate the initial delay time corresponding to the first test port and / or the second test port in the initial state of the multi-interface concurrent timing.
9. The multi-interface concurrent testing method according to claim 5, wherein: The multi-interface concurrent testing method also includes the following steps: Setting the interval time for the main control test module to control the communication between the controlled test module and the first test port and / or the communication between the controlled test module and the second test port; The tests were performed at different time intervals.
10. The multi-interface concurrent testing method according to claim 9, wherein: The accuracy of the timing of the communication between the controlled test module and the first test port and the second test port is determined according to the highest clock of the master test module and the controlled test module; On the basis of the initial interval time, the time is increased or decreased by a set step size to obtain the different interval time.