System-on-chip prototype verification method and device and electronic equipment
By introducing cache and counter mechanisms into the bus processing module of the system-level chip, exception responses are handled and verification continues, the problem of interruption due to data errors in prototype verification is solved, and verification efficiency is improved.
Patent Information
- Application Number
- CN202411142841.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-01-07
AI Technical Summary
In the prior art system-level chip prototype verification process, the write and read data error of the functional module will interrupt the test program, resulting in the end of the test process, and the inability to continue to verify other functional modules, which is relatively inefficient.
By introducing a request information cache unit, an exception information storage unit and a response exception counter into the bus processing module, the control processor core sends a request through the bus, and when the target function module returns an exception response, it performs correction processing before sending a response to the processor Core, avoid interruption of testing.
It realizes the system-level chip prototype verification when the functional module returns an exception response. Through one test, it obtains the exception information of multiple functional modules, rather than only obtaining the exception information of one functional module at a time, which improves the prototype verification. efficiency.
Smart Images
Figure CN119271478A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip verification technology, and in particular to a prototype verification method, device and electronic equipment for a system-level chip. Background Art
[0002] System on Chip (SoC) chips have a high degree of integration and often integrate multiple functional modules. The bus of the SoC chip is used to send access requests from the processor core of the SoC chip to the functional modules of the SoC chip, and to send data or responses returned by the functional modules of the SoC chip to the processor core of the SoC chip. If the bus of the SoC chip has a functional abnormality, the processor core of the SoC chip cannot normally access the functional modules of the SoC chip, which will cause the SoC chip to work abnormally and affect the functions of the SoC chip. Therefore, the bus-related functions of the SoC chip need to be verified during chip verification.
[0003] Prototype verification can provide a software development platform that can be verified in parallel, restore the actual usage scenarios of the chip as much as possible, and construct a variety of actual chip usage scenarios for cross-verification, which can fully verify whether the bus function of the SoC chip is abnormal. When using the prototype to verify the function of the SoC chip bus, you can run the test program in the processor core of the SoC chip, read and write access to the functional modules of the SoC chip, and compare the write and read data to determine whether the bus function of the SoC chip is abnormal.
[0004] However, currently when using a prototype to verify the function of the SoC chip bus, if read and write access is performed on a functional module of a certain SoC chip, errors in the write and read data of the functional module of the SoC chip will interrupt the execution of the prototype verification test program, causing the entire test process to end and the functional modules of other SoC chips to be unable to continue testing, resulting in relatively low efficiency in prototype verification of the SoC chip. Summary of the invention
[0005] The present application provides a prototype verification method, device and electronic device for a system-level chip, which are used to solve the defect in the prior art that a functional module of the system-level chip reads out data incorrectly and interrupts the prototype verification, thereby improving the prototype verification efficiency of the system-level chip.
[0006] The present application provides a prototype verification method for a system-level chip, which is applied to a system-level chip formed on a programmable logic chip, wherein the system-level chip includes a processor core, a bus, a bus processing module and multiple functional modules, and the method includes: controlling the processor core to send a request to the bus processing module through the bus, controlling the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus; controlling the target functional module to send a response to the bus processing module through the bus; when it is determined that the response is an abnormal response, controlling the bus processing module to store the response, and processing the response to obtain a corrected response, and sending the corrected response to the processor core through the bus.
[0007] According to a prototype verification method of a system-level chip provided in the present application, the bus processing module also includes a request information cache unit and an exception information storage unit; controlling the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus includes: controlling the bus processing module to store the request in the request information cache unit, and forwarding the request to the target functional module among the multiple functional modules through the bus; controlling the bus processing module to store the response includes: controlling the bus processing module to read the corresponding request from the request information cache unit, and storing the response and the request in association with each other in the exception information storage unit.
[0008] According to a prototype verification method of a system-level chip provided in the present application, controlling the bus processing module to store the request in a request information cache unit includes: controlling the bus processing module to store the request in the request information cache unit according to a write pointer; wherein the write pointer is incremented after the handshake of the request is completed; controlling the bus processing module to read the corresponding request from the request information cache unit according to a read pointer, including: controlling the bus processing module to read the corresponding request from the request information cache unit according to the read pointer; wherein the read pointer is incremented after confirming that the response of the target functional module is valid.
[0009] According to a prototype verification method of a system-level chip provided by the present application, the bus processing module also includes a response exception counter; controlling the bus processing module to store the request in a request information cache unit, including: controlling the bus processing module to store the request in a request information cache unit with a ring cache structure; controlling the bus processing module to read the corresponding request from the request information cache unit, and storing the response and the request in association with the exception information storage unit, including: when it is determined that the count value of the response exception counter is less than a count threshold, controlling the bus processing module to read the corresponding request from the request information cache unit, storing the response and the request in association with the exception information storage unit, and incrementing the count value.
[0010] According to a prototype verification method of a system-level chip provided by the present application, the bus processing module includes a write channel, and the write channel includes a write response exception counter, a write request information cache unit and an abnormal write information storage unit; the method specifically includes: controlling the processor core to send a write request to the write channel through the bus, controlling the write channel to store the write request in the write request information cache unit according to a first write pointer, and forwarding the write request to a target functional module among the multiple functional modules through the bus; wherein the first write pointer is incremented after the handshake of the write request is completed; controlling the target functional module to send a write response signal to the write channel through the bus; when it is determined that the write response signal is an abnormal write response signal, controlling the write channel to read the corresponding write request from the write request information cache unit according to a first read pointer, storing the write request and the write response signal in the abnormal write information storage unit in association, and processing the write response signal to obtain a modified write response signal, and controlling the bus processing module to send the modified write response signal to the processor core through the bus; wherein the first read pointer is incremented after confirming that the write response signal of the target functional module is valid.
[0011] According to a prototype verification method of a system-level chip provided by the present application, the bus processing module also includes a read channel, and the read channel includes a read response exception counter, a read request information cache unit and an abnormal read information storage unit; the method specifically includes: controlling the processor core to send a read request to the read channel through the bus, controlling the read channel to store the read request in the read request information cache unit according to a second write pointer, and forwarding the read request to a target functional module among the multiple functional modules through the bus; wherein the second write pointer is incremented after the handshake of the read request is completed; controlling the target functional module to send a read request to the read channel through the bus The read channel sends a read response signal; when it is determined that the read response signal is an abnormal read response signal, the read channel is controlled to read a corresponding read request from the read request information cache unit according to a second read pointer, the read request is associated with the read response signal and stored in the abnormal read information storage unit, and the read response signal is processed to obtain a corrected read response signal, the read data corresponding to the read response signal is replaced with a tag sequence, and the bus processing module is controlled to send the corrected read response signal and the tag sequence to the processor core through the bus; wherein the second read pointer is incremented after confirming that the read response signal of the target functional module is valid.
[0012] The present application also provides a prototype verification device for a system-level chip, which is applied to a system-level chip formed on a programmable logic chip, wherein the system-level chip includes a processor core, a bus, a bus processing module and multiple functional modules, and the method includes: a request sending module, which is used to control the processor core to send a request to the bus processing module through the bus, and control the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus; a response sending module, which is used to control the target functional module to send a response to the bus processing module through the bus; and a response transfer module, which is used to control the bus processing module to store the response when determining that the response is an abnormal response, and process the response to obtain a corrected response, and send the corrected response to the processor core through the bus.
[0013] The present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, a prototype verification method of the system-on-chip as described above is implemented.
[0014] The present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the prototype verification method of the system-on-chip as described in any one of the above is implemented.
[0015] The present application also provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, the prototype verification method of the system-on-chip as described above is implemented.
[0016] The prototype verification method, device and electronic device of the system-level chip provided in the present application determine whether the response returned by the target functional module is an abnormal response by controlling the bus processing module, so that when it is determined that the response is an abnormal response, the response is processed to obtain a corrected response, and the corrected response is sent to the processor core, which can avoid the processor core from receiving the abnormal response, so that when a certain functional module returns an abnormal response, the prototype verification of the system-level chip continues, and the abnormal information corresponding to multiple functional modules of the system-level chip can be obtained through one prototype verification, instead of obtaining the abnormal information corresponding to one functional module of the system-level chip each time the prototype verification is performed, thereby improving the prototype verification efficiency of the system-level chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0018] Figure 1 It is one of the architectural schematic diagrams of the prototype verification method of the system-level chip in the prior art.
[0019] Figure 2 This is the second schematic diagram of the architecture of the prototype verification method of the system-on-chip in the prior art.
[0020] Figure 3 This is one of the flow charts of the prototype verification method of the system-on-chip provided in this application.
[0021] Figure 4 This is one of the architectural schematic diagrams of the prototype verification method of the system-on-chip provided in this application.
[0022] Figure 5 This is the second schematic diagram of the architecture of the prototype verification method of the system-on-chip provided in this application.
[0023] Figure 6 It is a schematic diagram of a bus control module involved in the prototype verification method of the system-on-chip provided in this application.
[0024] Figure 7 It is a schematic diagram of a write request information cache unit of a bus control module involved in the prototype verification method of the system-on-chip provided in the present application.
[0025] Figure 8 This is the second flow chart of the prototype verification method of the system-on-chip provided in this application.
[0026] Fig. 9 This is the third flow chart of the prototype verification method of the system-on-chip provided in this application.
[0027] Fig.10 It is a schematic diagram of the structure of the prototype verification device of the system-on-chip provided in this application.
[0028] Fig.11 It is a structural schematic diagram of the electronic device provided by this application. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0030] like Figure 1 As shown, currently, the request of the processor core is generally forwarded to the functional module through the bus NIC, and the response of the functional module is fed back to the processor core. Generally, the test program can be run in the processor core to read and write access to each functional module in the SoC chip, and the bus in the SoC chip can be judged based on the comparison and matching of the written and read data to determine whether the bus in the SoC chip can normally access each functional module, thereby judging the correctness of the connection of the SoC chip bus.
[0031] However, currently, multiple functional modules are generally tested in a serial manner, such as Figure 2 As shown, when the response returned by a certain functional module to the processor core is a normal response, the next functional module can be tested. When the response returned by a certain functional module to the processor core is an abnormal response, the processor core determines that it is an underlying bus hardware-level error based on the abnormal response, and cannot handle it, thereby interrupting the prototype verification of the system-level chip. Only after eliminating the problem of abnormal response of the functional module can the subsequent other functional modules be tested. And in the subsequent testing of other functional modules, abnormal responses may still occur. In this way, the information provided by each prototype verification of the system-level chip is not comprehensive, resulting in a relatively low efficiency of the prototype verification of the system-level chip.
[0032] In order to solve the above technical problems, the present application provides a system-level chip prototype verification method, device and electronic equipment. Figure 3-Figure 11 The present invention describes a prototype verification method, device and electronic device for a system-on-chip.
[0033] Figure 3 It is one of the flow charts of the prototype verification method of the system-level chip provided by the present application, which is applied to the system-level chip formed on the programmable logic chip, such as Figure 4 As shown, the system-level chip includes a processor core, a bus, a bus processing module and multiple functional modules.
[0034] Programmable logic chips can be programmed according to user needs to implement a variety of logic functions in hardware. For example, programmable logic chips may include programmable logic arrays, programmable array logic devices, and field programmable gate arrays.
[0035] System-on-chip, also known as system on chip, is a highly integrated product that integrates multiple components in a computer system on a single chip. The processor core, also known as the processor core (Core) or processor core, is a component that executes instructions and processes data. Exemplarily, the bus may include a network interface controller (NIC). The functional module is a module that implements a specific function, for example, it may be a memory controller that manages data storage and access, or it may be a peripheral controller responsible for communication with external devices. The external interface can be regarded as a special functional module. Exemplarily, the external interface may include a USB interface, an SPI interface, and a PCIe interface. Exemplarily, prototype validation can form a register transfer level (RTL) code based on the system-on-chip design, form an executable file based on the RTL code, implement the system-on-chip function in the programmable logic chip, construct a variety of system-on-chip usage scenarios for cross-validation, restore the real usage scenario of the system-on-chip as much as possible, and fully test the function of the system-on-chip.
[0036] The bus processing module may be one or more. When there are more than one bus processing modules, the bus processing modules and the functional modules may correspond one to one.
[0037] like Figure 3 As shown, the method includes: Step 101: Control the processor core to send a request to the bus processing module through the bus, and control the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus.
[0038] The request sent by the processor core may be a write request or a read request, etc. In the case where the request is a write request, the processor core may send the address, data and control signal of the write request to the bus processing module through the bus, so that the address, data and control signal of the write request of the processor core are forwarded to the target functional module corresponding to the address of the write request through the bus through the bus processing module.
[0039] When the request is a read request, the processor core can send the address and control signals of the read request to the bus processing module through the bus, and the bus processing module can forward the address and control signals of the read request of the processor core through the bus to the target functional module corresponding to the address of the read request.
[0040] Step 102: Control the target functional module to send a response to the bus processing module through the bus.
[0041] As mentioned above, if the request is a write request, the target functional module can send a write response to the bus processing module through the bus. If the request is a read request, the target functional module can send both the read data and the read response to the bus processing module through the bus.
[0042] Step 103: When it is determined that the response is an abnormal response, control the bus processing module to store the response, process the response to obtain a modified response, and send the modified response to the processor core through the bus.
[0043] The bus processing module is a hardware-level exception response processing and recording mechanism that reflects error responses to the processor core during the prototype verification process of the isolated system-level chip. After receiving the response, the bus processing module can determine whether the response is an abnormal response. Exemplarily, the bus processing module can preset a response code meaning comparison table and determine whether the response is an abnormal response by looking up the table. For example, when the request is a write request, the abnormal response can be a write response returned when the target functional module cannot write the data of the received write request. When the request is a read request, the abnormal response can be a read response returned when the target functional module cannot return the requested read data, etc.
[0044] like Figure 5 As shown, the modified response is a response obtained after processing the abnormal response, which can avoid the processor core from judging the underlying bus hardware level error based on the abnormal response, thereby interrupting the prototype verification of the system-level chip. The modified response can be a normal response or a response with a preset identifier. The response with a preset identifier can cause the processor core to stop sending requests to the functional module and send requests to the next predetermined functional module to perform prototype verification of the system-level chip.
[0045] The prototype verification method of the system-level chip provided in the embodiment of the present application determines whether the response returned by the target functional module is an abnormal response by controlling the bus processing module, so that when it is determined that the response is an abnormal response, the response is processed to obtain a corrected response, and the corrected response is sent to the processor core, which can avoid the processor core from receiving the abnormal response, so that when a certain functional module returns an abnormal response, the prototype verification of the system-level chip continues, and the abnormal information corresponding to multiple functional modules of the system-level chip can be obtained through one prototype verification, instead of obtaining the abnormal information corresponding to one functional module of the system-level chip each time the prototype verification is performed, thereby improving the prototype verification efficiency of the system-level chip.
[0046] Based on the above embodiment, the bus processing module also includes a request information cache unit and an exception information storage unit. Among them, the request information cache unit is the part of the bus processing module that caches the request issued by the processor core. The exception information storage unit is the part of the bus processing module that stores the exception response information returned by the function module. The exception response information can be the exception response signal itself, and can also include information related to the exception response signal. For example, when the request is a read request, the information related to the exception response signal may include the exception response signal, the returned read request data, and the read request corresponding to the exception response signal.
[0047] Controlling the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus includes: controlling the bus processing module to store the request in a request information cache unit, and forwarding the request to a target functional module among the multiple functional modules through the bus.
[0048] Exemplarily, the bus processing module may decode the request and store it in the request information cache unit, and update the state to forward the request to a target functional module among the multiple functional modules based on a target address in the request, where the target address is the address of the target functional module.
[0049] Controlling the bus processing module to store the response includes: controlling the bus processing module to read the corresponding request from the request information cache unit, and storing the response and the request in association with each other in the abnormal information storage unit.
[0050] Exemplarily, the bus processing module can decode the response, read the corresponding request from the request information cache unit based on the sending address of the response and the target address in the request, and create a data structure to associate and store the response and the corresponding request. The data structure can be a structure or a class, etc. The response and the corresponding request can also be associated and stored in the exception information storage unit by adding the same identifier to the response and the request.
[0051] In this embodiment, in the process of the processor core sending a request to the target functional module through the bus processing module, the request is stored in the request information cache unit by controlling the bus processing module, which can facilitate the bus processing module to send requests to the target functional module in an orderly manner based on the scheduling strategy. In the process of the target functional module returning a response to the processor core through the bus processing module, when the bus processing module determines that the response is an abnormal response, the response and the corresponding request are associated and stored in the abnormal information storage unit, which can provide relatively complete context information when locating the cause of the abnormal response generated by the target functional module, so as to facilitate the reproduction and verification of whether the abnormal response is resolved by reproducing the request that generates the abnormal response.
[0052] Based on any of the above embodiments, controlling the bus processing module to store the request in the request information cache unit includes: controlling the bus processing module to store the request in the request information cache unit according to the write pointer; wherein the write pointer is incremented after the handshake of the request is completed.
[0053] The write pointer is a logical address pointing to the next free storage location in the request information cache unit, indicating that the request should be stored in the target location in the request information cache unit, enabling the request information to be stored in the request information cache unit in a first-in-first-out order, thus avoiding overwriting the request previously stored in the request information cache unit. The handshake completion indicates that the request has been successfully written into the request information cache unit, and the write pointer can be moved to the next free location in the request information cache unit to prepare for writing a new request.
[0054] Exemplarily, when the request is a write request, the handshake completion may be determined to increment the write pointer when the processor core sends a status signal indicating that the data of the write request is valid and the target functional module sends a status signal indicating that it is ready to receive the data of the write request. When the request is a read request, the handshake completion may be determined to increment the write pointer when the processor core sends a status signal indicating that the address of the read request is valid and the target functional module sends a status signal indicating that it is ready to send the corresponding data to the processor core.
[0055] Controlling the bus processing module to read the corresponding request from the request information cache unit according to the read pointer includes: controlling the bus processing module to read the corresponding request from the request information cache unit according to the read pointer; wherein the read pointer is incremented after confirming that the response of the target functional module is valid.
[0056] The read pointer points to the logical address of the next request to be read in the request information cache unit, indicating the target location where the request should be read in the request information cache unit, and enables the request information to be read in the request information cache unit in a first-in-first-out order to avoid missed or repeated read requests. Confirming that the response of the target functional module is valid indicates that the target functional module has sent a response to the bus processing module, and moving the write pointer to the logical address of the next request to be read in the request information cache unit can facilitate reading the corresponding request when the response is an abnormal response.
[0057] Exemplarily, when the request is a write request, the read pointer can be incremented when the target functional module sends a status signal indicating that the write response is valid. When the request is a read request, the read pointer can be incremented when the target functional module sends a status signal indicating that the data currently being transmitted is the last data of this transmission, the target functional module sends a status signal indicating that it is ready to send the read data to the processor core, and the processor core sends a status signal indicating that it is ready to receive the data to be sent by the target functional module.
[0058] In this embodiment, after the handshake is completed, the bus processing module can receive the request sent by the processor core, so the write pointer is incremented after the handshake is completed, which can facilitate the bus processing module to directly store the request at the specified location in the request information cache unit through the write pointer. After confirming that the response of the target functional module is valid, the bus processing module can receive the response sent by the target functional module. Therefore, the read pointer is incremented after confirming that the response of the target functional module is valid, which can facilitate reading the request directly from the specified location in the request information cache unit when the response is an abnormal response, thereby improving the efficiency of data access.
[0059] Based on any of the above embodiments, the bus processing module further includes a response exception counter, wherein the response exception counter is used to record the number of times the response is an abnormal response, and illustratively, the response exception counter may be a variable, and when the response is an abnormal response, the value of the variable is controlled to increase by 1.
[0060] Controlling the bus processing module to store the request in a request information cache unit includes: controlling the bus processing module to store the request in a request information cache unit of a ring buffer structure. The ring buffer structure may also be called a circular buffer or a circular buffer, which is a data storage structure.
[0061] In this embodiment, by storing requests in a request information cache unit of a ring cache structure, new requests can be continuously stored in the information cache unit as the prototype verification process of the system-level chip progresses. After the information cache unit is full, the first request written either corresponds to a normal response, or has been stored in the exception information storage unit under an exception response. Overwriting the first request written in the information cache unit will not affect the prototype verification of the system-level chip, and there is no need to dynamically allocate and release memory, which can reduce system overhead.
[0062] Control the bus processing module to read the corresponding request from the request information cache unit, and store the response and the request in association with each other in the exception information storage unit, including: when it is determined that the count value of the response exception counter is less than the count threshold, control the bus processing module to read the corresponding request from the request information cache unit, store the response and the request in association with each other in the exception information storage unit, and increment the count value.
[0063] The count threshold of the exception counter is used to determine whether the exception information storage unit is full. After the response and request are associated and stored in the exception information storage unit, the count value is incremented so that the count value of the response exception counter can reflect the storage space situation in the exception information storage unit. If the count value of the response exception counter is less than the count threshold, it can be determined that the exception information storage unit is not full, and storing the exception response information in the exception information storage unit will not overwrite the exception response information written for the first time.
[0064] In this embodiment, by setting the exception counter, when the count value of the response exception counter is less than the count threshold, the response and request are associated and stored in the exception information storage unit, and when the count value of the response exception counter is greater than the count threshold, the prototype verification of the system-level chip is stopped, so as to control the storage depth of the exception write information storage module while avoiding the exception response information written for the first time from being overwritten.
[0065] Based on any of the above embodiments, the bus processing module includes a write channel, and the write channel includes a write response exception counter, a write request information cache unit and an abnormal write information storage unit.
[0066] The write channel is a channel in the bus processing module for receiving write requests and write request data sent by the processor core, writing the write request and write request data to the target functional module, receiving the write response returned by the target functional module, and sending the write response to the processor core. Among them, the signal received by the bus processing module from the processor core can also be called the processor core end write channel signal, and the signal sent by the bus processing module to the target functional module can also be called the functional module end write channel signal.
[0067] The method specifically includes: controlling the processor core to send a write request to the write channel through the bus, controlling the write channel to store the write request in a write request information cache unit according to a first write pointer, and forwarding the write request to a target functional module among the multiple functional modules through the bus; wherein the first write pointer is incremented after the handshake of the write request is completed; controlling the target functional module to send a write response signal to the write channel through the bus; when it is determined that the write response signal is an abnormal write response signal, controlling the write channel to read the corresponding write request from the write request information cache unit according to a first read pointer, storing the write request in association with the write response signal in the abnormal write information storage unit, processing the write response signal to obtain a corrected write response signal, and controlling the bus processing module to send the corrected write response signal to the processor core through the bus; wherein the first read pointer is incremented after confirming that the write response signal of the target functional module is valid.
[0068] In this embodiment, the bus processing module is controlled to determine whether the write response signal returned by the target functional module is an abnormal write response signal. When it is determined that the write response signal is an abnormal write response signal, the write request and the write response signal are associated and stored in the abnormal write information storage unit. This can facilitate reading, recording and analyzing the abnormal response and the corresponding request information after the prototype verification of the system-level chip is completed, and help locate the cause of the abnormal response generated by each functional module. The write response signal is processed to obtain a corrected write response signal, which can avoid the processor core from receiving the abnormal write response signal. Therefore, when a certain functional module returns an abnormal write response signal, the prototype verification of the system-level chip can be continued. The abnormal write information corresponding to multiple functional modules of the system-level chip can be obtained through one prototype verification, instead of obtaining the abnormal write information corresponding to one functional module of the system-level chip each time the prototype verification is performed, thereby improving the prototype verification efficiency of the system-level chip.
[0069] Based on any of the above embodiments, the bus processing module further includes a read channel, and the read channel includes a read response exception counter, a read request information cache unit and an abnormal read information storage unit.
[0070] The read channel is a channel in the bus processing module for receiving read requests sent by the processor core, writing the read requests to the target functional module, receiving read response data returned by the target functional module, and sending the read response data to the processor core. Among them, the signal received by the bus processing module from the processor core can also be called the processor core end read channel signal, and the signal sent by the bus processing module to the target functional module can also be called the functional module end read channel signal.
[0071] The method specifically includes: controlling the processor core to send a read request to the read channel through the bus, controlling the read channel to store the read request in a read request information cache unit according to a second write pointer, and forwarding the read request to a target functional module among the multiple functional modules through the bus; wherein the second write pointer is incremented after the handshake of the read request is completed; controlling the target functional module to send a read response signal to the read channel through the bus; when it is determined that the read response signal is an abnormal read response signal, controlling the read channel to read a corresponding read request from the read request information cache unit according to the second read pointer, storing the read request in association with the read response signal in the abnormal read information storage unit, processing the read response signal to obtain a modified read response signal, replacing the read data corresponding to the read response signal with a tag sequence, and controlling the bus processing module to send the modified read response signal and the tag sequence to the processor core through the bus; wherein the second read pointer is incremented after confirming that the read response signal of the target functional module is valid.
[0072] In this embodiment, the working principle and technical effect of performing prototype verification of the system-level chip through the read channel are basically the same as the working principle and technical effect of performing prototype verification of the system-level chip through the write channel, except that the associated signals are different, which will not be repeated here.
[0073] The difference is that when the bus processing module determines that the read response returned by the target functional module is an abnormal read response signal, it performs special processing on the read data returned by the target functional module so that the processor core can determine whether to perform subsequent read operation tests on the target functional module based on the read data returned by the target functional module.
[0074] The tag sequence may also be called a magic number, which is a special number for quickly judging the response of the target functional module, such as 0xcdcd and 0xcccc.
[0075] In this embodiment, after using a tag sequence to replace the read data corresponding to the read response signal, the processor core can complete the test results of the target functional module after reading the agreed tag sequence, reflecting the end of the prototype verification of the target functional module, further improving the prototype verification efficiency of the system-level chip.
[0076] By controlling the bus processing module to determine whether the read response signal returned by the target functional module is an abnormal read response signal, when determining that the read response signal is an abnormal read response signal, the read request and the read response signal are associated and stored in the abnormal read information storage unit, which can facilitate reading and recording and analyzing the abnormal response and the corresponding request information after the prototype verification of the system-level chip is completed, and help locate the cause of the abnormal response generated by each functional module, and process the read response signal to obtain the corrected read response signal, which can avoid the processor core from receiving the abnormal read response signal, so that when a certain functional module returns an abnormal read response signal, the prototype verification of the system-level chip continues, and the abnormal read information corresponding to multiple functional modules of the system-level chip can be obtained through one prototype verification, instead of obtaining the abnormal read information corresponding to one functional module of the system-level chip each time the prototype verification is performed, thereby improving the prototype verification efficiency of the system-level chip.
[0077] In one embodiment, the bus processing module may further include a cache information reading unit, which is connected to the abnormal write information storage unit and the abnormal read information storage unit respectively. After the prototype verification of the system-level chip is completed, the cache information reading unit can obtain the abnormal response and corresponding request stored in the abnormal write information storage unit and the abnormal read information storage unit, and store and export the abnormal response and corresponding request information, so as to read and record and analyze the abnormal response and corresponding request information after the prototype verification of the system-level chip is completed, and help locate the cause of the abnormal response generated by each functional module. Among them, the cache information reading unit can be electrically connected or communicatively connected to the abnormal write information storage unit and the abnormal read information storage unit respectively.
[0078] In order to specifically illustrate the function of the system-on-chip prototype verification method provided by this embodiment, a specific example is provided below.
[0079] The prototype verification method of the system-level chip is applied to the system-level chip formed on the field programmable gate array (FPGA), wherein the system-level chip includes a processor core, a bus, a bus processing module and multiple functional modules, the bus processing module includes a write channel and a read channel, the write channel includes a write response exception counter, a write request information cache unit and an abnormal write information storage unit, and the read channel includes a read response exception counter, a read request information cache unit and an abnormal read information storage unit.
[0080] Among them, the bus processing module is a hardware-level error response processing and recording mechanism. The bus supports the high-performance Advanced eXtensible Interface (AXI) protocol. The AXI protocol is a key component of the Advanced Microcontroller Bus Architecture (AMBA). The AXI protocol is a high-performance, high-bandwidth, low-latency on-chip bus protocol. The AXI protocol defines five independent channels, including a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel. This design enables the AXI protocol to support simultaneous read and write operations, thereby improving the efficiency of data transmission. The write operation involves the write address channel, the write data channel, and the write response channel, in which the write response channel contains a write response signal; the read operation involves the read address channel and the read data channel, in which the read data channel contains read data and read response signals. In the AXI bus protocol, a complete write operation requires the functional module to return a correct write response signal, and a complete read operation requires the functional module to return read data and a correct read response signal.
[0081] The response signal encoding and meaning in the AXI protocol are shown in the following table.
[0082]
[0083] Among them, BRESP is a write response signal, and RRESP is a read response signal.
[0084] Control the processor core to send a write request to the write channel through the AXI protocol, control the write channel to store the write request in a write request information cache unit of a ring cache structure according to a first write pointer, and forward the write request to a target functional module among the multiple functional modules through the bus; wherein the stored write request includes a write address, a write length, a write burst type, etc.
[0085] The first write pointer can be expressed by the following formula: wr_pt_wrchan = wr_pt_wrchan + awvalid&awready
[0086] Among them, wr_pt_wrchan is the first write pointer; awvalid and awready are general explanations in the AXI protocol; & means that awvalid and awready are satisfied at the same time.
[0087] awvalid&awready can indicate that the handshake of the write request is complete. Figure 7As shown, the first write pointer is incremented after the handshake of the write request is completed, so that new write requests can be continuously written into the first write pointer position according to the test.
[0088] Control the target functional module to send BRESP to the write channel via the bus, such as Figure 8 As shown, when it is determined that BRESP is not SLVERR or DECERR, wait for the next bvalid; when it is determined that BRESP is SLVERR or DECERR, control the write channel to read the corresponding write request from the write request information cache unit according to the first read pointer, associate the write request with the write response signal and store it in the abnormal write information storage unit, process the write response signal to obtain a corrected write response signal, and control the bus processing module to send the corrected write response signal to the processor core through the bus.
[0089] The first read pointer increases after confirming that the write response signal of the target functional module is valid, which can be expressed by the following formula: rd_pt_wrchan = rd_pt_wrchan + bvalid
[0090] Among them, rd_pt_wrchan is the first read pointer, and bvalid is the general interpretation in the AXI protocol.
[0091] Control the processor core to send a read request to the read channel through the AXI protocol, control the read channel to store the read request in a read request information cache unit of a ring cache structure according to a second write pointer, and forward the read request to a target functional module among the multiple functional modules through the bus; wherein the stored read request includes a read address, a read length, a read burst type, etc.
[0092] The second write pointer can be expressed by the following formula: wr_pt_rdchan = wr_pt_rdchan + arvalid&arready
[0093] Among them, wr_pt_rdchan is the second write pointer, arvalid and arready are general explanations in the AXI protocol; & means that awvalid and awready are satisfied at the same time.
[0094] awvalid&awready may indicate that the handshake of the read request is completed. In this way, the second write pointer is incremented after the handshake of the write request is completed, so that new read requests can be continuously written to the first write pointer position according to the test.
[0095] Control the target functional module to send RRESP to the read channel via the bus, such as Fig. 9 As shown, when it is determined that RRESP is not SLVERR or DECERR, wait for the next rvalid&rready&rlast; when it is determined that RRESP is SLVERR or DECERR, control the read channel to read the corresponding read request from the read request information cache unit according to the second read pointer, associate the read request with the read response signal and store it in the abnormal read information storage unit, process the read response signal to obtain a corrected read response signal, and control the bus processing module to send the corrected read response signal to the processor core through the bus.
[0096] rd_pt_rdchan = rd_pt_rdchan + rvalid&rready&rlast
[0097] Among them, rd_pt_rdchan is the second read pointer, rvalid, rready and rlast are generally explained in the AXI protocol, and & means that rvalid, rready and rlast are satisfied at the same time.
[0098] The prototype verification device of the system-on-chip provided in the present application is described below. The prototype verification device of the system-on-chip described below and the prototype verification method of the system-on-chip described above can be referenced to each other.
[0099] Fig.10 Schematic diagram of the structure of the prototype verification device of the system-level chip provided by the present application, which is applied to the system-level chip formed on the programmable logic chip, and the system-level chip includes a processor core, a bus, a bus processing module and multiple functional modules, such as Fig.10 As shown, the device includes a request sending module 201, a response sending module 202 and a response transfer module 203.
[0100] The request sending module 201 is used to control the processor core to send a request to the bus processing module through the bus, and control the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus.
[0101] The response sending module 202 is used to control the target functional module to send a response to the bus processing module through the bus.
[0102] The response transfer module 203 is used to control the bus processing module to store the response when determining that the response is an abnormal response, and process the response to obtain a modified response, and send the modified response to the processor core through the bus.
[0103] Based on any of the above embodiments, the bus processing module also includes a request information cache unit and an exception information storage unit; the request sending module 201 is specifically used to: control the bus processing module to store the request in the request information cache unit, and forward the request to the target functional module among the multiple functional modules through the bus; the response transfer module 203 is specifically used to: control the bus processing module to read the corresponding request from the request information cache unit, and store the response and the request in association in the exception information storage unit.
[0104] Based on any of the above embodiments, the request sending module 201 is specifically used to: control the bus processing module to store the request in the request information cache unit according to the write pointer; wherein the write pointer is incremented after the handshake of the request is completed; the response transfer module 203 is specifically used to: control the bus processing module to read the corresponding request from the request information cache unit according to the read pointer; wherein the read pointer is incremented after confirming that the response of the target functional module is valid.
[0105] Based on any of the above embodiments, the bus processing module also includes a response exception counter; the request sending module 201 is specifically used to: control the bus processing module to store the request in a request information cache unit with a circular cache structure; the response transfer module 203 is specifically used to: when it is determined that the count value of the response exception counter is less than the count threshold, control the bus processing module to read the corresponding request from the request information cache unit, store the response and the request in association with each other in the exception information storage unit, and increment the count value.
[0106] Based on any of the above embodiments, the bus processing module includes a write channel, and the write channel includes a write response exception counter, a write request information cache unit and an abnormal write information storage unit; the request sending module 201 is specifically used to: control the processor core to send a write request to the write channel through the bus, control the write channel to store the write request in the write request information cache unit according to the first write pointer, and forward the write request to the target functional module among the multiple functional modules through the bus; wherein the first write pointer is incremented after the handshake of the write request is completed; the response sending module 202 is specifically used to: control the target function The energy module sends a write response signal to the write channel through the bus; the response forwarding module 203 is specifically used to: when it is determined that the write response signal is an abnormal write response signal, control the write channel to read the corresponding write request from the write request information cache unit according to the first read pointer, associate the write request with the write response signal and store it in the abnormal write information storage unit, and process the write response signal to obtain a corrected write response signal, and control the bus processing module to send the corrected write response signal to the processor core through the bus; wherein, the first read pointer is incremented after confirming that the write response signal of the target functional module is valid.
[0107] Based on any of the above embodiments, the bus processing module also includes a read channel, and the read channel includes a read response exception counter, a read request information cache unit and an abnormal read information storage unit; the request sending module 201 is specifically used to: control the processor core to send a read request to the read channel through the bus, control the read channel to store the read request in the read request information cache unit according to the second write pointer, and forward the read request to the target functional module among the multiple functional modules through the bus; wherein the second write pointer is incremented after the handshake of the read request is completed; the response sending module 202 is specifically used to: control the target functional module to send a read request to the read channel through the bus The response transfer module 203 is specifically used for: when it is determined that the read response signal is an abnormal read response signal, controlling the read channel to read the corresponding read request from the read request information cache unit according to the second read pointer, storing the read request and the read response signal in association with each other in the abnormal read information storage unit, processing the read response signal to obtain a corrected read response signal, replacing the read data corresponding to the read response signal with a tag sequence, and controlling the bus processing module to send the corrected read response signal and the tag sequence to the processor core through the bus; wherein the second read pointer is incremented after confirming that the read response signal of the target functional module is valid.
[0108] Fig.11 An example of a physical structure diagram of an electronic device is shown in FIG. Fig.11As shown, the electronic device may include: a processor 310, a communication interface 320, a memory 330 and a communication bus 340, wherein the processor 310, the communication interface 320 and the memory 330 communicate with each other through the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute the prototype verification method of the system-level chip, the method comprising: controlling the processor core to send a request to the bus processing module through the bus, controlling the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus; controlling the target functional module to send a response to the bus processing module through the bus; when determining that the response is an abnormal response, controlling the bus processing module to store the response, and processing the response to obtain a modified response, and sending the modified response to the processor core through the bus.
[0109] In addition, the logic instructions in the above-mentioned memory 330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.
[0110] On the other hand, the present application also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the system-on-chip prototype verification method provided by the above methods, which includes: controlling the processor core to send a request to the bus processing module through the bus, and controlling the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus; controlling the target functional module to send a response to the bus processing module through the bus; when it is determined that the response is an abnormal response, controlling the bus processing module to store the response, and processing the response to obtain a corrected response, and sending the corrected response to the processor core through the bus.
[0111] On the other hand, the present application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the prototype verification method of the system-on-chip provided by the above-mentioned methods, the method comprising: controlling the processor core to send a request to the bus processing module through the bus, controlling the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus; controlling the target functional module to send a response to the bus processing module through the bus; when determining that the response is an abnormal response, controlling the bus processing module to store the response, and processing the response to obtain a corrected response, and sending the corrected response to the processor core through the bus.
[0112] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0113] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.
[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A prototype verification method for a system-on-chip, characterized in that: Applied to a system-on-chip formed on a programmable logic chip, the system-on-chip includes a processor core, a bus, a bus processing module and a plurality of functional modules, the method includes: Control the processor core to send a request to the bus processing module through the bus, and control the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus; Controlling the target functional module to send a response to the bus processing module via the bus; When it is determined that the response is an abnormal response, the bus processing module is controlled to store the response, and the response is processed to obtain a modified response, and the modified response is sent to the processor core through the bus.
2. The prototype verification method of the system-on-chip according to claim 1, characterized in that: The bus processing module also includes a request information cache unit and an abnormal information storage unit; Controlling the bus processing module to forward the request to a target functional module among the plurality of functional modules through the bus, comprising: Control the bus processing module to store the request in a request information cache unit, and forward the request to a target functional module among the plurality of functional modules through the bus; Controlling the bus processing module to store the response includes: The bus processing module is controlled to read a corresponding request from the request information cache unit, and the response and the request are associated and stored in the abnormal information storage unit.
3. The prototype verification method of the system-on-chip according to claim 2, characterized in that: Controlling the bus processing module to store the request in a request information cache unit includes: Controlling the bus processing module to store the request in the request information cache unit according to the write pointer; wherein the write pointer is incremented after the handshake of the request is completed; Controlling the bus processing module to read the corresponding request from the request information cache unit includes: The bus processing module is controlled to read a corresponding request from the request information cache unit according to a read pointer; wherein the read pointer is incremented after confirming that a response from the target functional module is valid.
4. The prototype verification method of the system-on-chip according to claim 2, characterized in that: The bus processing module also includes a response exception counter; Controlling the bus processing module to store the request in a request information cache unit includes: Controlling the bus processing module to store the request in a request information cache unit having a ring cache structure; Controlling the bus processing module to read the corresponding request from the request information cache unit, and storing the response and the request in association with each other in the abnormal information storage unit, comprises: When it is determined that the count value of the response exception counter is less than the count threshold, the bus processing module is controlled to read the corresponding request from the request information cache unit, the response and the request are associated and stored in the exception information storage unit, and the count value is incremented.
5. The prototype verification method of the system-on-chip according to claim 1, characterized in that: The bus processing module includes a write channel, and the write channel includes a write response exception counter, a write request information cache unit and an abnormal write information storage unit; The method specifically comprises: Control the processor core to send a write request to the write channel through the bus, control the write channel to store the write request in a write request information cache unit according to a first write pointer, and forward the write request to a target functional module among the multiple functional modules through the bus; wherein the first write pointer is incremented after the handshake of the write request is completed; Controlling the target functional module to send a write response signal to the write channel through the bus; When it is determined that the write response signal is an abnormal write response signal, the write channel is controlled to read the corresponding write request from the write request information cache unit according to the first read pointer, the write request is associated with the write response signal and stored in the abnormal write information storage unit, and the write response signal is processed to obtain a corrected write response signal, and the bus processing module is controlled to send the corrected write response signal to the processor core through the bus; wherein the first read pointer is incremented after confirming that the write response signal of the target functional module is valid.
6. The prototype verification method of the system-on-chip according to claim 1, characterized in that: The bus processing module further includes a read channel, and the read channel includes a read response exception counter, a read request information cache unit, and an abnormal read information storage unit; the method specifically includes: Control the processor core to send a read request to the read channel through the bus, control the read channel to store the read request in a read request information cache unit according to a second write pointer, and forward the read request to a target functional module among the multiple functional modules through the bus; wherein the second write pointer is incremented after the handshake of the read request is completed; Controlling the target functional module to send a read response signal to the read channel through the bus; When it is determined that the read response signal is an abnormal read response signal, the read channel is controlled to read the corresponding read request from the read request information cache unit according to the second read pointer, the read request is associated with the read response signal and stored in the abnormal read information storage unit, and the read response signal is processed to obtain a corrected read response signal, and the read data corresponding to the read response signal is replaced with a tag sequence, and the bus processing module is controlled to send the corrected read response signal and the tag sequence to the processor core through the bus; wherein the second read pointer is incremented after confirming that the read response signal of the target functional module is valid.
7. A prototype verification device for a system-on-chip, characterized in that: The device is applied to a system-on-chip formed on a programmable logic chip, the system-on-chip comprising a processor core, a bus, a bus processing module and a plurality of functional modules, and the device comprises: a request sending module, used to control the processor core to send a request to the bus processing module through the bus, and control the bus processing module to forward the request to a target functional module among the multiple functional modules through the bus; a response sending module, used for controlling the target functional module to send a response to the bus processing module via the bus; The response transfer module is used to control the bus processing module to store the response when determining that the response is an abnormal response, process the response to obtain a modified response, and send the modified response to the processor core through the bus.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the prototype verification method of the system-on-chip according to any one of claims 1 to 6 is implemented.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the prototype verification method of the system-on-chip according to any one of claims 1 to 6 is implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the prototype verification method of the system-on-chip according to any one of claims 1 to 6 is implemented.