Acceleration device and method for graph data processing

Abstract

The invention provides an acceleration device and method for graph data processing, the device comprises at least one processing unit, each processing unit is used for processing a matching task of a matching sequence corresponding to an update edge and a pattern graph in a data graph to obtain a graph matching result, the isomorphic sub-graphs can be newly added or reduced due to the updated edges of the data graph. According to the acceleration device for graph data processing provided by the embodiment of the invention, a large amount of invalid exploration and expensive isomorphic test overhead are avoided through a dynamic graph matching increment algorithm based on mode perception.

Description

[0001] This application claims priority to Chinese patent application No. 202310835633.3, filed on July 7, 2023, entitled “A graph pattern matching method and accelerator based on pattern perception”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to an acceleration device and method for graph data processing. Background Art

[0003] Graph is an important data representation in computer science. It uses nodes (also called vertices) and edges (edges) between nodes to represent the relationship between objects. In order to make full use of the large amount of graph data in the network, effectively play the role of graph data, and mine and use valuable information, graph pattern matching technology has developed rapidly and is widely used in related fields such as biology, chemistry, information security network and social network. Graph pattern matching refers to finding all subgraphs H in the data graph G that are isomorphic to the pattern graph P (also called the query graph Q), that is, there is a bijective function f from the node set of the pattern graph P to the node set of the data graph G, so that if and only if (v, v`) is an edge in the pattern graph P, (f(v), f(v`)) is also an edge in the subgraph H. If there are labels for the nodes in the graph, the label of the node v in the pattern graph P is required to be the same as the label of the node f(v) in the subgraph H.

[0004] Graph data in the real world is large in scale, complex in structure, and updated in real time, such as social networks and biological protein structures. A dynamic graph refers to a graph whose structure or node information changes over time. Therefore, pattern matching on dynamic graphs has a wider range of application scenarios, greater market demand, higher algorithm calculation requirements, and greater research value. However, the existing dynamic graph pattern matching algorithms have poor matching efficiency due to a large amount of useless exploration and isomorphism testing overhead. Summary of the invention

[0005] The embodiments of the present application provide an acceleration device for graph data processing, which avoids a large amount of invalid exploration and expensive isomorphic testing overhead through a dynamic graph matching incremental algorithm based on pattern perception.

[0006] In a first aspect, the present application provides an acceleration device for graph data processing, comprising at least one processing element (PE), wherein each processing element is used to process the matching task of updating edges in a data graph and a matching sequence (matching order) corresponding to a pattern graph to obtain a graph matching result, wherein the matching result includes newly added or reduced isomorphic subgraphs caused by the updated edges of the data graph.

[0007] Exemplarily, the structure of a given pattern graph is analyzed to generate at least one matching sequence, and the processing unit processes the matching task of the assigned update edge and at least one matching sequence corresponding to the pattern graph to obtain a matching result. For example, the processing unit maps the update edge to the starting edge of all matching sequences respectively, and continues to match the remaining unmatched nodes to obtain a matching result, that is, a subgraph corresponding to the update edge that is isomorphic to the pattern graph, without the need for isomorphism testing and avoiding invalid exploration, thereby increasing the matching efficiency of pattern matching.

[0008] In a possible implementation, the pattern graph includes multiple nodes and connecting edges connecting different nodes; the matching sequence corresponding to the pattern graph includes multiple matching sequences generated with each connecting edge (which may be referred to as a pattern edge) in the pattern graph as a starting edge. In other words, each pattern edge of the pattern graph corresponds to a set of matching sequences, namely, matching sequences generated with each pattern edge as a starting edge.

[0009] By taking each pattern edge in the pattern graph as the starting edge to generate multiple matching sequences corresponding to the pattern graph, during matching, the update edge is mapped to the starting edge for matching, ensuring that each pattern edge in the pattern graph will be matched with the update edge as the starting edge, thereby ensuring the completeness of the matching result.

[0010] Since different orders of the two nodes of the pattern edge will produce different matching results, each pattern edge will exchange its node order to generate two matching sequences. In other words, a set of matching sequences generated by each pattern edge of the pattern graph includes two matching sequences generated after exchanging the node order, further ensuring the completeness of the matching results.

[0011] In another possible implementation, the matching sequence corresponding to the pattern graph is obtained by pruning multiple matching sequences based on the symmetry order, wherein two matching sequences that are mutually symmetric sequences have the same isomorphic subgraphs matched. Exemplarily, after generating multiple complete matching sequences with each pattern edge of the pattern graph as the starting edge, the symmetric sequence in the matching sequence is detected, and one of the two matching sequences that are mutually symmetric sequences is pruned; or, first identify the symmetric sequence in the pattern graph, for example, identify the nodes with symmetry in the pattern graph, and use the pattern edge composed of two nodes with symmetry as the starting edge to generate a group of matching sequences, two of which are symmetric sequences, and use the symmetric sequence to prune multiple matching sequences, that is, delete one of the two matching sequences that are mutually symmetric sequences in the multiple matching sequences corresponding to the pattern graph, eliminate duplicate matches, and further improve matching efficiency.

[0012] The processing unit needs to process several set operation tasks in the process of performing matching tasks. The operation objects of the set operation tasks include the neighbor node sets of two nodes in the data graph; the set operation includes intersection or difference, for example. There are usually a large number of set operation tasks for long and short sets among the several set operation tasks. Therefore, in another possible implementation, a binary search unit (BSU) for the set operation tasks for long and short sets is set in each processing unit.

[0013] In order to increase the processing speed of the set operation tasks for long and short sets, the binary search unit is pipelined so that the binary search unit can process multiple data in parallel during the process of processing the set operation tasks.

[0014] In another possible implementation, the binary search unit is used to perform the following processing on the pending set operation task: convert the long set into a binary search tree for representation, the node value in the binary search tree is determined based on the elements in the long set, each node value in the binary search tree is greater than all node values ​​of the left subtree corresponding to each node, and each node value in the binary search tree is less than all node values ​​of the right subtree corresponding to each node; divide the short set into at least one data block, each data block in the at least one data block includes several elements in the short set; for each data block, compare and calculate each data block in parallel with the node values ​​of the first N layers of the binary search tree to obtain a first comparison calculation result, where N is a positive integer greater than 1.

[0015] In other words, the first N layers of the long set organized in a binary search tree are set as N hardware processing stages. In each stage, the data blocks obtained from the short set are compared in parallel and an index array is output. The index arrays of the first N-1 stages are used to index the elements to be compared in the long set of this stage (that is, the nodes of the binary search tree) to generate a parallel comparison array for comparing this hardware node with the data blocks to be compared; the index array output by the Nth stage is used to determine the binary search range of the corresponding elements in the subsequent data blocks to be compared.

[0016] In another possible implementation, the comparison calculation result of each data block with the node value of the i-th layer in the first N layers of the binary search tree is determined based on the elements in each data block and the comparison array of the i-th layer, the comparison array of the i-th layer is determined by the index array of the previous layer and the node value of the i-th layer, and the index array of the previous layer is determined based on the first comparison calculation results of all layers before the i-th layer.

[0017] In another possible implementation, the binary search unit further includes, based on the index array of the Nth layer, matching the elements in each data block to the subspace of the corresponding long set for comparison calculation to obtain a second comparison calculation result, and the subspace of the first set is obtained by dividing the elements corresponding to each node of the binary search tree; based on the first comparison calculation result and the second comparison calculation result, determining the processing result of the set operation task to be processed.

[0018] In another possible implementation, each processing unit further includes a scratchpad memory (SPM) for storing data read by the binary search unit for a number of times greater than or equal to a second preset threshold. That is, the scratchpad memory caches data that is frequently read by the binary search unit, and when the binary search unit needs to read the data again, the data is directly read from the scratchpad memory without having to read the data from the next level of storage, thereby speeding up the efficiency of reading data and further increasing the efficiency of set operations.

[0019] In another possible implementation, each processing unit also includes a merge computing unit (MU) and a sets dispatcher (sets dispatcher), wherein the sets dispatcher is used to evaluate the time overhead of the merge computing unit processing the pending set operation tasks and the time overhead of the binary search unit processing the pending set operation tasks based on the set operation overhead evaluation model; based on the time overhead, the pending set operation tasks are assigned to the merge computing unit for processing or to the binary search unit for processing.

[0020] A merge calculation unit, a binary search unit and a set scheduler are set in the processing unit of the present application. The merge calculation unit and the binary search unit can be called a hybrid set calculation unit. The set scheduler uses a set operation overhead evaluation model to evaluate whether the set operation task to be processed is suitable for processing by the merge calculation unit or the binary search unit. The set scheduler assigns the set operation task to be processed to the merge calculation unit or the binary search unit for processing based on the evaluation result, thereby speeding up the processing speed of the set operation task.

[0021] In another possible implementation, the construction of the collection computing overhead evaluation model is related to time complexity and hardware performance, the time complexity indicates the time complexity of the collection operation task to be processed, and the hardware performance includes first hardware performance and second hardware performance, the first hardware performance includes one or more of the number of parallel processing sub-units and the hardware frequency of the merge computing unit, and the second hardware performance includes one or more of the number of parallel processing sub-units of the binary search unit, hardware access delay and pipeline depth.

[0022] Exemplarily, the collection scheduler establishes a collection calculation cost evaluation model based on time complexity and hardware performance to estimate the time cost of using a merge calculation unit to perform collection calculations and the time cost of using a binary search unit to perform collection calculations, and selects the unit with the smaller time cost after evaluation to execute. The mode evaluation formula is as follows:

[0023] MU: (|A|+|B|) / (MP*F)

[0024] BSU:(LM*(|B|*(log(|A|)-PD)) / BSP

[0025] Where |A| and |B| are the lengths of two sets respectively, and the length of set A is smaller than the length of set B; MP represents the number of parallel processing units in the merge computing unit, BSP represents the number of parallel processing units in the binary search unit, F represents the hardware frequency of the merge computing unit, LM represents the hardware memory access delay of the binary search unit, and PD represents the pipeline depth in the binary search unit.

[0026] In another possible implementation, a redundancy detector (Redundancy Detector) is also set in each processing unit. The redundancy detector is used to detect the number of times each set operation task is repeatedly processed during the execution of the matching task, and cache the processing results of the target set operation task based on the number of repeated processing. The number of times the target set operation task is repeatedly processed meets the preset conditions.

[0027] A set operation task may be, for example, set calculation. The redundancy detector of the present application detects set calculations that need to be calculated frequently, and caches the results of the frequently calculated set calculations. When the set calculation is needed next time, there is no need to calculate the set calculation again, and the result can be directly read from the cache, thereby reducing redundant set calculations, speeding up the processing speed of set calculations, and increasing graph matching efficiency.

[0028] Optionally, the preset condition may be a number of repeated processing times greater than a preset percentage of the number of repeated processing times of each set operation task; for example, the redundancy detector detects the number of repeated calculations of each set calculation, and caches the set calculation results whose repeated calculation times rank in the top 30%. The redundancy detector continuously detects and records the number of repeated calculations of each set calculation, continuously updates the cached set calculation results, implements dynamic caching, deletes the set calculation results whose repeated calculation times are out of the top 30%, and adds the set calculation results whose repeated calculation times are newly in the top 30%.

[0029] Alternatively, the preset condition may be greater than or equal to a first preset threshold, for example, the redundancy detector caches the collective calculation results whose number of repeated calculations is greater than or equal to 10.

[0030] In another possible implementation, the redundancy detector is specifically used to detect that the processing result of the pending collective operation task is cached, and send the processing result of the pending collective operation task to the core of the processing unit where the redundancy detector is located. That is, if the processing result of the pending collective operation task is hit from the cache, the processing result is sent to the core of the processing unit, and there is no need to calculate the collective operation, thereby reducing redundant calculations.

[0031] In another possible implementation, the redundancy detector is also used to detect that the processing result of the pending collection operation task is not cached, and to send a request message to the collection scheduler, wherein the request message carries the identifier of the pending collection operation task, and the request message is used to request the collection scheduler to schedule the pending collection operation task.

[0032] In another possible implementation, each processing unit further includes a private cache; the redundancy detector is further used to maintain a first hash table in the private cache, the first hash table recording the cache address of the target set operation task and the processing result of the target set operation task; and / or, maintaining a second hash table in the private cache, the second hash table recording the cache address of each set operation task and the number of times each set operation task is repeatedly processed. The redundancy detector records the cache address of the processing result of the cached set operation task and the number of times the set operation task is repeatedly processed through the hash table, which is convenient for query.

[0033] In another possible implementation, the acceleration device for graph data processing provided by the present application further includes a scheduler, which is used to schedule the update edges of neighboring edges in the data graph to the same processing unit in at least one processing unit for processing. Adjacent update edges will use part of the same data, and assigning adjacent update edges to a processing unit for processing is conducive to speeding up the graph matching speed.

[0034] In another possible implementation, the acceleration device for graph data processing provided by the present application further includes a shared cache, which is used to cache the updated edges in the data graph and the edge data adjacent to the updated edges. Exemplarily, when processing graph data, the data graph is read into the memory, and the shared memory reads the node / edge data required by the processing unit from the memory, such as the updated edges and the edge data adjacent to the updated edges.

[0035] In the second aspect, the present application provides an acceleration method for graph data processing, which is applied to an acceleration device for graph data processing. The acceleration device for graph data processing includes at least one processing unit. The acceleration method for graph data processing provided by the present application includes processing the matching task of the matching sequence of the update edge in the data graph and the matching sequence corresponding to the pattern graph by each processing unit in at least one processing unit to obtain a graph matching result.

[0036] In a possible implementation, the pattern graph includes multiple nodes and connecting edges connecting different nodes; the matching sequence corresponding to the pattern graph includes multiple matching sequences generated with each connecting edge in the pattern graph as the starting edge.

[0037] In another possible implementation, the matching sequence corresponding to the pattern graph is obtained by pruning multiple matching sequences based on a symmetric sequence, wherein two matching sequences that are symmetric sequences to each other have the same isomorphic subgraphs obtained by matching.

[0038] In another possible implementation, the matching task execution process includes executing several set operation tasks, and the operation objects of the set operation tasks include the set of neighbor nodes of two nodes in the data graph; each processing unit includes a binary search unit, and the acceleration method for graph data processing provided in the present application also includes processing a first set operation task to be processed by a binary search unit, and the operation objects of the first set operation task to be processed include a first set and a second set, and the length of the first set is greater than the length of the second set; wherein the binary search unit is hardware pipelined so that the binary search unit processes multiple data in parallel during the process of processing the first set operation task to be processed.

[0039] In another possible implementation, the first to-be-processed set operation task is processed as follows by a binary search unit: the first set is converted into a binary search tree for representation, the node values ​​in the binary search tree are determined based on the elements in the first set, each node value in the binary search tree is greater than all node values ​​of the left subtree corresponding to each node, and each node value in the binary search tree is less than all node values ​​of the right subtree corresponding to each node; the second set is divided to obtain at least one data block, each data block in at least one data block includes several elements in the second set; for each data block, each data block is compared and calculated in parallel with the node values ​​of the first N layers of the binary search tree to obtain a first comparison calculation result, where N is a positive integer greater than 1.

[0040] In another possible implementation, the comparison calculation result of each data block with the node value of the i-th layer in the first N layers of the binary search tree is determined based on the elements in each data block and the comparison array of the i-th layer, the comparison array of the i-th layer is determined by the index array of the previous layer and the node value of the i-th layer, and the index array of the previous layer is determined based on the first comparison calculation results of all layers before the i-th layer.

[0041] In another possible implementation, the processing of the first pending set operation task by the binary search unit also includes: based on the index array of the Nth layer, matching the elements in each data block to the corresponding subspace of the first set for comparison calculation to obtain a second comparison calculation result, and the subspace of the first set is obtained based on the element division corresponding to each node of the binary search tree; based on the first comparison calculation result and the second comparison calculation result, determining the processing result of the first pending set operation task.

[0042] Optionally, each processing unit also includes a temporary register memory, and the acceleration method for graph data processing provided in the present application also includes caching data read by the binary search unit a number of times greater than or equal to a second preset threshold in the temporary register memory.

[0043] In another possible implementation, each processing unit also includes a merge computing unit and a collection scheduler, and the acceleration method for graph data processing provided in the present application also includes: sending the pending collection operation task to the collection scheduler, so that the collection scheduler evaluates the time overhead of the merge computing unit processing the pending collection operation task and the time overhead of the binary search unit processing the pending collection operation task based on the collection operation overhead evaluation model; based on the time overhead, the pending collection operation task is assigned to the merge computing unit for processing or to the binary search unit for processing.

[0044] In another possible implementation, the construction of the collection computing overhead evaluation model is related to time complexity and hardware performance, where the time complexity indicates the time complexity of the collection operation task to be processed, and the hardware performance includes first hardware performance and second hardware performance. The first hardware performance includes one or more of the number of parallel processing sub-units and the hardware frequency of the merge computing unit, and the second hardware performance includes one or more of the number of parallel processing sub-units of the binary search unit, the hardware access delay, and the pipeline depth.

[0045] In another possible implementation, each processing unit also includes a redundancy detector, and the acceleration method for graph data processing provided by the present application also includes: detecting the number of times each set operation task is repeatedly processed during the execution of the matching task through the redundancy detector, and caching the processing results of the target set operation task based on the number of repeated processing, and the number of times the target set operation task is repeatedly processed meets the preset conditions.

[0046] In another possible implementation, the preset condition includes a number of repeated processing times greater than a preset percentage of the number of repeated processing times of each collective operation task; or, the preset condition includes being greater than or equal to a first preset threshold.

[0047] In another possible implementation, the acceleration method for graph data processing provided by the present application also includes: when the redundancy detector detects that the processing result of the pending set operation task is cached, the processing result of the pending set operation task is sent to the core of the processing unit where the redundancy detector is located.

[0048] In another possible implementation, the acceleration method for graph data processing provided by the present application also includes: when the redundancy detector detects that the processing result of the pending collection operation task is not cached, sending a request message to the collection scheduler, the request message carries the identifier of the pending collection operation task, and the request message is used to request the collection scheduler to schedule the pending collection operation task.

[0049] In another possible implementation, each processing unit also includes a private cache, and the acceleration method for graph data processing provided in the present application also includes: maintaining a first hash table in the private cache, the first hash table recording the cache address of the target set operation task and the processing result of the target set operation task; and / or, maintaining a second hash table in the private cache, the second hash table recording the cache address of each set operation task and the number of times each set operation task is repeatedly processed.

[0050] In another possible implementation, the acceleration device for graph data processing also includes a scheduler, and the acceleration method for graph data processing provided in the present application also includes: scheduling the update edges of neighboring edges in the data graph to the same processing unit in at least one processing unit for processing through the scheduler.

[0051] In another possible implementation, the acceleration device for graph data processing also includes a shared cache. The acceleration method for graph data processing provided in the present application caches the updated edges in the data graph and the edge data adjacent to the updated edges through the shared cache.

[0052] In a third aspect, an embodiment of the present application provides an acceleration chip for graph data processing, comprising a memory and at least one processing unit, each of the at least one processing unit being used to process the matching task of a matching sequence between an update edge in a data graph and a matching sequence corresponding to a pattern graph to obtain a graph matching result.

[0053] In a fourth aspect, an embodiment of the present application provides a computing device, comprising a memory and a processor, wherein the memory stores instructions, and when the instructions are executed by the processor, the method described in the second aspect is implemented.

[0054] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in the second aspect is implemented.

[0055] In a sixth aspect, an embodiment of the present application further provides a computer program or a computer program product, wherein the computer program or the computer program product comprises instructions, which, when executed, cause a computer to execute the method described in the second aspect.

[0056] In a seventh aspect, an embodiment of the present application further provides a chip, comprising at least one processor and a communication interface, wherein the processor is used to execute the method described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A schematic diagram of graph matching is shown;

[0058] Figure 2 A schematic diagram of a generation process of a matching sequence of a pattern graph P is shown;

[0059] Figure 3 The following is a flowchart showing an acceleration method for graph data processing provided by an embodiment of the present application;

[0060] Figure 4 A schematic diagram showing the proportion of collection calculation time during the execution of the pattern graph matching task is shown;

[0061] Figure 5 It shows that during the execution of the pattern graph matching task, more than 30% of the set calculations are repeatedly calculated more than 10 times;

[0062] Figure 6A schematic diagram showing the ratio of long sets and short sets for set operations during the execution of the pattern graph matching task is shown;

[0063] Figure 7 A schematic diagram of the architecture of a hardware acceleration device for dynamic graph pattern matching tasks provided by an embodiment of the present application is shown;

[0064] Figure 8 A schematic diagram of the execution flow of the hardware accelerator provided in an embodiment of the present application for any set of calculations is shown;

[0065] Fig. 9 An example schematic diagram showing a method of representing a set in a binary search unit provided in an embodiment of the present application is shown;

[0066] Fig.10 A schematic diagram showing the execution calculation of a set calculation by a binary search unit provided in an embodiment of the present application;

[0067] Fig.11 A performance comparison chart of the acceleration solution for graph data processing provided by an embodiment of the present application and the existing solution is shown;

[0068] Fig.12 A performance comparison diagram of several PSMiner architectures of the hardware acceleration device provided in the embodiment of the present application is shown;

[0069] Fig.13 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The term "and / or" mentioned in this article is a kind of relationship that describes the association of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0071] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of objects. For example, a first hash table and a second hash table are used to distinguish different hash tables rather than to describe a specific order of hash tables.

[0072] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0073] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0074] To facilitate understanding of the solutions of the embodiments of the present application, the technical terms involved in this document are first explained below.

[0075] Dynamic graph: A graph whose structure evolves over time is called a dynamic graph. The nodes and edges of a dynamic graph are added, modified, and deleted over time.

[0076] Dynamic graph pattern matching: After a dynamic graph is updated, enumerate all subgraphs that are added / deleted due to the graph update and are isomorphic to the given pattern.

[0077] A graph pattern matching algorithm is usually used to extract a subgraph matching a specified pattern graph from graph data, and tasks are performed based on the extracted subgraph. The pattern graph here is used to express the association rules between specific entities in actual scenarios. For example, in the field of medicine, there is a specific molecular structure that can be used for medical treatment. The connection relationship between molecules in this characteristic molecular structure can be designed as a pattern graph, and the subgraph matching this pattern graph is queried from the graph data corresponding to other macromolecular substances to determine whether the other macromolecular substances contain this specific molecular structure.

[0078] Graph pattern matching means matching all subgraphs in a given graph that are isomorphic to a given pattern. Dynamic graphs evolve over time, and graph updates are constantly arriving and cached in batches. These cached updates are applied to the previous graph snapshot and generate the latest graph snapshot. Dynamic graph pattern matching enumerates all subgraphs in the latest graph snapshot that are isomorphic to the given pattern and that were added / deleted due to graph updates. Figure 1 A schematic diagram of graph matching is shown. Figure 1 The dashed lines in the input graph G (InputGraph G) represent updated (i.e., newly added) connections. Figure 1 The first row shows two subgraphs obtained by matching the pattern graph P with the data graph G before update, which are respectively composed of nodes {1,2,4,5} and nodes {3,2,4,5}. Figure 1 The bottom row in the figure shows the matching of the pattern graph P with the updated data graph G, that is, four new matching subgraphs obtained by matching the pattern graph P with the data graph G after adding a new connecting edge between nodes 3 and 4, including the matching subgraph {1,2,3,4}, the matching subgraph {5,2,3,4}, the matching subgraph {5,4,2,3}, and the matching subgraph {3,4,5,2}.

[0079] Graph pattern matching in related technologies usually uses a pattern-agnostic method for graph pattern matching. The pattern-agnostic method is centered on the subgraph, starting from a vertex, and continuously expands the subgraph in a breadth-first search (BFS) or depth-first search (DFS) manner, and performs an isomorphism test on the subgraph to ensure the uniqueness of the result. For example, related technology 1 is a distributed dynamic graph pattern matching method based on incremental calculation (which can be called the Tesseract solution). Tesseract assigns the update edges to different nodes for processing, uses an exploration-based pattern-agnostic method, performs pattern matching in a depth-first search manner, and performs an isomorphism test on the matched subgraph to ensure that it is isomorphic to the given pattern graph. Tesseract uses the timestamps of the edges in the graph to establish an expansion order for all edges, assigns them different priorities, and ensures that high-priority edges can be extended to low-priority edges, and vice versa, to eliminate duplicate matches.

[0080] However, this solution is based on a pattern-agnostic approach, which means that the information in the pattern graph is not fully utilized, which increases the search space and results in a large amount of useless exploration and isomorphism testing overhead during matching.

[0081] In order to avoid a large amount of useless exploration and isomorphic testing overhead, an embodiment of the present application provides an acceleration method for graph data processing (also referred to as a dynamic graph pattern incremental matching algorithm based on pattern perception, which can be abbreviated as GraphPi-S), which generates a complete matching sequence corresponding to the pattern graph by analyzing the structure of a given pattern graph, and updates the edges to perform pattern matching on each matching sequence corresponding to the pattern graph to obtain graph matching results, such as isomorphic subgraphs that are added / reduced due to the updated edges of the data graph.

[0082] For example, the structure of a given pattern graph is analyzed, and a set of matching sequences is generated with each pattern edge as the starting edge. That is, there are as many matching sequences as there are pattern edges in the pattern graph.

[0083] Since different orders of the two nodes of a pattern edge will produce different matching results, in order to ensure the completeness of the matching, the order of the nodes of each pattern edge will be exchanged to generate two matching sequences. In other words, a set of matching sequences corresponding to each pattern edge will include two matching sequences.

[0084] Matching sequences that are symmetrical to each other in the pattern graph will obtain the same matching results. That is to say, there may be matching sequences that are symmetrical to each other in the matching sequence corresponding to the pattern graph, which will produce repeated matches. Therefore, in order to eliminate redundant repeated matches, the pattern-aware dynamic graph pattern incremental matching algorithm provided in the embodiment of the present application also includes identifying symmetrical sequences in the matching sequence corresponding to the pattern graph, using the symmetrical sequences to prune the matching sequences, eliminate repeated matches, and increase matching efficiency.

[0085] Figure 2 FIG. 1 shows a schematic diagram of a generation process of a matching sequence of a pattern graph P. Figure 2 Take as an example to illustrate the generation of matching sequence of pattern graph. Figure 2 As shown, for a given pattern graph P, four groups of matching sequences are generated with each of its pattern edges as the starting edge, for a total of 8 matching sequences, including a group of matching sequences {u0,u1,u2,u3},{u1,u0,u2,u3} generated with the pattern edge u0-u1 of the pattern graph P as the starting edge; a group of matching sequences {u1,u2,u3,u0},{u2,u1,u3,u0} generated with the pattern edge u1-u2 of the pattern graph P as the starting edge; a group of matching sequences {u1,u3,u2,u0},{u3,u1,u2,u0} generated with the pattern edge u1-u3 of the pattern graph P as the starting edge; a group of matching sequences {u2,u3,u1,u0},{u3,u2,u1,u0} generated with the pattern edge u2-u3 of the pattern graph P as the starting edge. Then, nodes with symmetry in the pattern graph are identified. When the nodes with symmetry are used as the starting edge and as the matching sequence, the matching sequence is pruned to eliminate duplicate matches. For example, Figure 8 The two nodes of the pattern edge u2-u3 in the pattern graph P in are symmetrical, and the matching sequences generated with u2-u3 as the starting edge are mutually symmetrical sequences. One of the matching sequences needs to be deleted to avoid repeated matching. For example, the symmetric sequence is determined to be {u2>u3}, and the matching sequence {u2,u3,u1,u0} is deleted due to the symmetric sequence. Therefore, the matching sequence corresponding to the pattern graph P generated by the dynamic graph pattern incremental matching algorithm based on pattern perception provided in the embodiment of the present application is finally seven matching sequences, including: {u0,u1,u2,u3},{u1,u0,u2,u3}; u1,u2,u3,u0},{u2,u1,u3,u0}; {u1,u3,u2,u0},{u3,u1,u2,u0}; {u3,u2,u1,u0}. On the basis of eliminating repeated matches, redundant repeated matches are eliminated.

[0086] After the matching sequence corresponding to the pattern graph P is generated, the update edge is mapped to the starting edge of the matching sequence for matching, ensuring that each pattern edge in the pattern graph will be matched with the update edge as the starting edge to ensure the completeness of the matching result.

[0087] It can be understood that the matching sequence corresponding to the pattern graph is a set of nodes in which the nodes of the pattern graph are arranged in a certain order. When performing dynamic graph matching, the update edges are matched in the order indicated by the matching sequence. Figure 1 For example, the updated edge is 3-4, and the matching sequence of the pattern graph is {u0,u1,u2,u3}. The matching order is node u0 matches node 3, node u1 matches node 4, and u2 is the neighbor node of u1. Therefore, node u2 should be matched with the neighbor node of node u4. The neighbor nodes of node 4 are {2,5}. Therefore, the candidate matching nodes of node u2 are {2,5}, and node 2 is selected to match node u2; then match node u3. Node u3 is the intersection of the neighbor nodes of node u1 and the neighbor nodes of node u2. Therefore, the node that matches node u3 in the data graph G should be the intersection of the neighbor nodes of node 4 and the neighbor nodes of node 2. The intersection of the neighbor nodes of node 4 and the neighbor nodes of node 2 is node 5, so node u3 is matched with node 5. Finally, according to the matching sequence {u0,u1,u2,u3}, the subgraph obtained by matching the updated edge 3-4 is {3,4,2,5}.

[0088] In order to further increase the execution efficiency of dynamic graph pattern matching tasks (i.e., graph data processing tasks), the embodiment of the present application also specially designs a hardware acceleration device (also referred to as a hardware accelerator) for dynamic graph pattern matching tasks. The hardware acceleration device includes at least one processing unit, each processing unit being used to process the matching task of updating edges in the data graph and the matching sequence corresponding to the pattern graph to obtain a graph matching result.

[0089] The specific implementation of the acceleration method and device for graph data processing provided by the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0090] Figure 3 FIG. 1 shows an execution flow chart of an acceleration method for graph data processing provided by an embodiment of the present application. Figure 3 As shown, the acceleration method for graph data processing includes a preprocessing stage and a matching result generation stage. In the preprocessing stage, the structure of the pattern graph is analyzed to generate a matching sequence corresponding to the pattern graph. In the matching result generation stage, the updated edge is matched with the matching sequence of the pattern graph, and the graph matching result is output to obtain the matching subgraph added / reduced due to the updated edge.

[0091] The preprocessing stage can be executed in the processor (central processing unit, CPU) of the computing device, and the matching result generation stage can be executed in the hardware accelerator. In this way, on the one hand, the more computationally intensive matching result generation stage (which involves a large number of set calculations, so there will be a large computing overhead) is put into the hardware accelerator for execution, without occupying the computing power overhead of the computing device CPU. On the other hand, the dedicated hardware accelerator will also increase the efficiency of graph matching.

[0092] Exemplarily, the processor of the computing device performs preprocessing on the pattern graph to obtain a matching sequence corresponding to the pattern graph, for example, the structure of the input pattern graph is analyzed, and a set of matching sequences (including two matching sequences generated by exchanging the order of the starting edge nodes) is generated with each pattern edge as the starting edge to obtain a complete matching sequence. Then, the two nodes of the starting edge are marked as symmetric nodes as symmetric sequences, and the matching sequence is pruned based on the symmetric sequence. The pruned matching sequence and the corresponding symmetric sequence constitute the execution plan of the dynamic graph pattern matching, that is, the pattern graph is matched with the update edge in the data graph according to the node order indicated by the matching sequence, and the symmetric sequence is used to eliminate repeated exploration in the matching process, and further reduce redundant matching. The matching result generation stage is performed in the hardware accelerator, for example, the update edge is dynamically assigned to the processing unit in the hardware accelerator for pattern graph matching, and the update edge is mapped to the starting edge of all matching sequences respectively, and the remaining unmatched nodes are continued to be matched to generate a matching result.

[0093] The matching task of updating the matching sequence corresponding to the edge and the pattern graph can be expressed as a series of set operations (such as set calculations, including intersection or difference) between adjacent nodes. According to the benchmark test, Figure 4 As shown in Figure 2, set operations account for more than 89% of the execution time. Since the update of dynamic graphs is usually associated with a few high-degree nodes, a large number of repeated set calculations and set calculations with huge differences in length will be generated. Figure 5 It shows that more than 30% of the set calculations are repeated more than 10 times. Figure 6 It shows that the ratio of long sets to short sets for set operations is huge, some of which exceed 1000.

[0094] In order to eliminate a large number of repeated repeated set calculations, the number of repetitions of the same set calculation is calculated during the execution of the pattern graph matching task. When a threshold is reached, the result of the set calculation will be cached. When the same set calculation is called again in the future, the result is directly obtained from the cache to reduce redundant set calculations. However, when running on a general core (such as a CPU core in a multi-core computer), calculating the number of repetitions of set calculations may result in higher lock overhead. This is because multiple threads need to access the same memory location that stores the number of repetitions of set calculations. Experimental results show that lock overhead accounts for 76.6% of the execution time, which greatly reduces the performance improvement brought by caching frequently used set calculation results. In addition to the lock overhead, the repetition count itself and the index preservation result will also bring overhead. Therefore, the hardware acceleration device for dynamic graph pattern matching tasks provided in the embodiment of the present application is specially designed for the hardware unit to effectively detect redundant set calculations and reduce redundant calculations.

[0095] Figure 7 FIG. 1 is a schematic diagram showing the architecture of a hardware acceleration device for dynamic graph pattern matching tasks provided by an embodiment of the present application. The architecture can be referred to as the PSMiner architecture. Figure 7 As shown, the PSMiner architecture provided by the embodiment of the present application mainly includes a scheduler, a shared cache and multiple processing units, wherein the shared cache is used to pre-fetch the graph data (for example, including node data / edge data) required by the processing unit from the memory (for example, an off-chip memory); the scheduler is used to dynamically assign the associated update edges in the batch graph update to the same processing unit for processing. Exemplarily, the scheduler assigns the update edges arriving in batches to the processor for processing, maintains a queue for each processing unit, and each queue initially queues a first update edge connected to a frequently updated node, and then detects the second update edge adjacent to the first update edge in the update edges arriving in batches, and adds the second update edge to the queue until all the update edges are assigned; the processing unit is used to process the update edges, execute the pattern matching algorithm, and output the matching results.

[0096] Continue to see Figure 7 A redundancy detector is set in each processing unit, and the redundancy detector is used to detect the number of times each set calculation is repeatedly calculated during the execution of the matching task, and cache the results of the frequently calculated set calculations based on the number of repeated calculations.

[0097] In the embodiment of the present application, a set calculation whose number of repeated calculations exceeds a certain threshold can be defined as a frequently calculated set calculation, for example, a set calculation whose number of repeated calculations exceeds 10 can be defined as a frequently calculated set calculation, and the result of the set calculation can be cached. The set calculations that rank in the top 30% of the number of repeated calculations can also be defined as frequently calculated set calculations, and the results of the set calculations can be cached, so that the calculation results can be reused when the set calculation needs to be executed again, reducing redundant set calculations, speeding up the processing speed of set calculations, and thus increasing the efficiency of graph matching.

[0098] In another example, the redundancy detector is also used to detect whether the collective calculation result of the collective calculation task to be calculated is cached. If it is cached, the result of the collective calculation is read from the cache and sent to the core of the processing unit where the redundancy detector is located. That is, if the collective calculation result of the collective calculation task to be calculated is hit from the cache, the calculation result is sent to the core of the processing unit, and there is no need to calculate the collective operation, thereby reducing redundant calculations. If it is detected that the collective calculation result of the collective calculation task to be calculated is not cached, a request message is sent to the collective scheduler, and the request message carries the identifier of the collective operation task to be processed. The request message is used to request the collective scheduler to schedule the collective calculation task to be calculated.

[0099] A private cache is also set up in the processing unit. The redundant detector can cache the detected repeated calculation times of the set calculation and the results of the frequently calculated set calculation that need to be cached into the private cache. The private cache has a faster reading and writing speed than the shared cache, further increasing the matching efficiency.

[0100] The redundancy detector can record and save the number of repeated calculations and the results of set calculations in the form of a hash table. For example, the redundancy detector maintains a first hash table in a private cache, and the first hash table records the cache address of the target set operation tasks and the processing results of the target set operation tasks; and / or, maintains a second hash table in the private cache, and the second hash table records the cache address of each set operation task and the number of times each set operation task is repeatedly processed.

[0101] A plurality of computing units are also provided in the processing unit for executing the collective computing tasks assigned by the collective scheduler.

[0102] The graph pattern matching scheme in the related art uses a merge algorithm when performing set calculations, but the performance of the merge algorithm is not as good as the binary search algorithm when the lengths of the sets differ greatly. However, the data dependency and random memory access in the binary search algorithm lead to low execution efficiency on general-purpose hardware, and the existing binary search scheme does not have data parallelism, resulting in low search efficiency.

[0103] In order to further improve the efficiency of graph pattern matching, the processing unit in the hardware accelerator provided in the embodiment of the present application is designed as a hybrid set computing unit, that is, the hybrid set computing unit includes a merge computing unit and a binary search unit, the merge computing unit is used to execute the merge algorithm to process the set computing, and the binary search unit is used to execute the binary search algorithm to process the set computing. At the same time, in order to solve the problems of the binary search algorithm on general hardware (such as the problem of low execution efficiency caused by lack of parallelism, data dependence, etc.), the embodiment of the present application also performs hardware pipeline processing on the binary search unit, so that the binary search unit can process multiple data in parallel during the process of processing the set computing task, thereby improving the set computing efficiency of the binary search unit.

[0104] It should be noted that Figure 7 The schematic diagram of the architecture of the hardware acceleration device for dynamic graph pattern matching tasks is only an example and does not constitute a limitation on the embodiments of the present application. For example, the hardware acceleration device may include more or fewer components, such as the hardware acceleration device may also include a communication interface for receiving instructions from the CPU of the computing device or sending matching results to the CPU.

[0105] Figure 8 A schematic diagram of the execution flow of the hardware accelerator provided in an embodiment of the present application for any set of calculations is shown.

[0106] When the processing unit needs to perform set calculation during the matching algorithm provided in the embodiment of the present application, the redundancy detector uses a hash table to establish a cache table of set calculation results, wherein the hash table<key,value> <(id(set0), id(set1), set op), storage address of set calculation result>. The redundancy detector detects whether the set calculation result is saved. The detection method is to check whether the key <(id(set0), id(set1), set op) set calculation result has a valid value. If it has been saved, the address of the result will be returned. Otherwise, the set calculation will be sent to the set scheduler, and the hash table will be used to record the number of set calculation reuses and save the set calculation results whose reuse times exceed the first 30% of the batch updates. The result address is saved in the hash table. The hash table used for multiplexing counts and saving the addresses of set calculation results resides in the private memory of the processing unit. If the set calculation result is not saved, the set scheduler assigns the set calculation to the merge calculation unit or the binary search unit for set calculation.

[0107] In one example, the collection scheduler may adopt a collection computing cost evaluation model to evaluate the time cost of the merge computing unit executing the collection computing task and the time cost of the binary search unit executing the collection computing task respectively; and assign the collection computing to be calculated to the one with smaller time cost for processing.

[0108] Specifically, the collection scheduler establishes a collection computing overhead evaluation model based on time complexity and hardware performance to estimate the time overhead of using a merge computing unit to perform collection computing and the time overhead of using a binary search unit to perform collection computing, and selects the unit with the smallest time overhead after evaluation to execute. The model evaluation formula is as follows:

[0109] MU: (|A|+|B|) / (MP*F)

[0110] BSU:(LM*(|B|*(log(|A|)-PD)) / BSP

[0111] Where |A| and |B| are the lengths of two sets respectively, and the length of set A is smaller than the length of set B; MP represents the number of parallel processing units in the merge computing unit, BSP represents the number of parallel processing units in the binary search unit, F represents the hardware frequency of the merge computing unit, LM represents the hardware memory access delay of the binary search unit, and PD represents the pipeline depth in the binary search unit.

[0112] The binary search unit uses a data parallel pipeline to accelerate the efficiency of binary search, increase the computational efficiency of set calculations, and thus increase the efficiency of graph matching. The following example introduces the accelerated processing process of the binary search unit for the assigned set calculation.

[0113] Fig. 9 FIG. 2 shows an example of a method for representing a set in a binary search unit provided in an embodiment of the present application. Fig. 9 As shown in the figure, the long set of inputs is represented recursively in the form of a tree with the middle position as the vertex. The accelerator only accelerates the comparison calculation of the first N layers (taking 3 layers as an example). The corresponding hardware accelerator is also designed into N stages (e.g. Fig. 9 The hardware acceleration of stage 1 to stage 3 in the short set is used to accelerate the data in the short set. A data block of the short set is compared and searched from stage 1 to stage 3. Multiple data blocks of the short set are pipelined and compared and searched from stage 1 to stage 3 in turn; after the hardware acceleration of stage 1 to stage 3. If no match is found in the data of each short set block, further comparison and search can be performed in the reduced search space.

[0114] It is understandable that the "tree" mentioned in the embodiments of the present application is a set of multiple nodes with a hierarchical relationship. It is called a "tree" because the structure looks like an upside-down tree with its roots facing up and leaves facing down. Some characteristics of the "tree" include: each node is connected to a limited number of child nodes or no child nodes; a node without a parent node is called a root node; a node without a child node is called a leaf node; each non-root node has one and only one parent node; except for the root node, each child node can be divided into multiple non-intersecting subtrees. The "tree" mentioned in this article can also be called a "binary search tree". Each node value in the binary search tree is greater than all node values ​​of the left subtree corresponding to each node, and less than all node values ​​of the right subtree corresponding to each node.

[0115] Fig.10 FIG. 1 is a schematic diagram showing the execution calculation of the binary search unit for set calculation provided by the embodiment of the present application. Fig.10 As shown, the acceleration rules for each stage are as follows:

[0116] The first step is to obtain the set data: the corresponding elements in the long set are taken into the comparison units cmp_data 1-3 of stage 1 to stage 3 respectively; a block of data is taken from the short set according to the arrangement order, referred to as data block 1.

[0117] The second step is stage 1 acceleration: data block 1 is compared with the elements in cmp_data1 to obtain index data index1; in this example, cmp_data1 =

[10] , data block 1 = [2 9 16 18], and index1 = [0 0 1 1].

[0118] The third step is to accelerate stage 2: obtain the parallel comparison data group b2 with data block 1 in stage 2 according to index1 and cmp_data2, compare data b2 and data block 1 element by element to obtain index2', and then combine the index data index1 to obtain the index array index2; in this example, cmp_data2 = [5 15], b2[i] = cmp_data2[index1[i]], b2 = [5 515 15], index2 = 2*index1+index2'([0 1 1 1]) = [0 1 3 3].

[0119] Step 4, stage 3 acceleration: obtain the parallel comparison data group b3 of Stage 3 and block 1 according to the index array index2 and cmp_data3, compare b3 with block 1 element by element to obtain index3' and combine it with the index array index2 to obtain the index array index3; in this example, cmp_data3 = [3 7 12 17], b3[i] = cmp_data3[index2[i]], b3 = [3 7 1717], index3 = 4*index1+2*index2+index3'([0 1 0 1]) = [0 3 6 7].

[0120] When comparing each stage, the data block and the corresponding position of cmp_data are compared element by element. If it is less than 0, it is 1, and if it is equal to 1, it is a special value, such as -1, indicating that a match is found. The result can be recorded in the output cache (such as a private cache), and the corresponding elements are compared in the subsequent stages of the data block.

[0121] Step 5, further calculation: obtain the index array index3, match each element in data block 1 to the subspace of the corresponding long set; the index of the subspace corresponding to the element of data block 1[i] is index3[i]; use the elements at the vertices of the tree structure as the boundary to split, and the 7 elements are divided into 8 subspaces in turn; further search and matching methods can adopt any feasible method, and this application does not limit this.

[0122] The hardware accelerator provided in the embodiment of the present application designs a binary search unit of a parallel pipeline, designs the first N layers of the long set organized in a binary search tree as N hardware processing stages, realizes the parallel comparison calculation of the data blocks in the short set and the elements at the corresponding positions in the long set, and accelerates the calculation efficiency of the binary search unit. Exemplarily, the continuous data blocks to be compared obtained from the short set and the parallel comparison data group corresponding to this stage are input in each stage for parallel processing and comparison of corresponding elements, and an index array for generating parallel comparison data in the next stage is generated according to the size relationship; the index values ​​of the corresponding elements of the index array passed from the previous stages determine the sequential index of the binary tree nodes to be compared in this stage, and generate the parallel comparison data group of this stage; the corresponding elements of the index array generated by the combination of N stages are used to determine the range of binary search of each element in the data block in the subsequent comparison process of this data block, so as to narrow the search range and further accelerate the efficiency of binary search.

[0123] In another example, in order to further increase the computational efficiency of the binary search unit, a temporary register memory is further provided in the processing unit for storing data frequently read by the binary search unit with a frequency greater than or equal to a certain threshold. In other words, the temporary register memory caches data frequently read by the binary search unit, and when the binary search unit needs to read the data again, the data is directly read from the temporary register memory without having to read the data from the next level of storage (such as a private cache), thereby speeding up the efficiency of reading data and further increasing the efficiency of set computation.

[0124] The acceleration solution for graph data processing provided by the embodiment of the present application executes a dynamic graph matching incremental algorithm based on pattern perception through PSMiner, avoiding a large amount of invalid exploration and expensive isomorphism testing overhead. In addition, the hardware accelerator avoids redundant calculations by caching frequently used set results. At the same time, the hardware accelerator designs a hybrid set calculation unit (including a merge calculation unit and a binary search unit), and assigns the set to a calculation unit with a smaller time overhead for set calculation through a set calculation overhead evaluation model. A data-parallel pipeline binary search accelerator is designed for the binary search unit, which accelerates the speed of set calculation and achieves higher processing efficiency.

[0125] Fig.11 The performance comparison diagram of the acceleration solution for graph data processing provided by the embodiment of the present application and the existing solution is shown. Fig.11 As shown, compared with the existing graph data processing solutions, the acceleration GraphPi-S and hardware accelerator PSMiner for graph data processing provided by the embodiments of the present application are 9.8 times and 770.9 times higher than GraphPi (experiments have shown that GraphPi's performance exceeds Tesseract) on average. Compared with the most advanced hardware accelerator, the hardware accelerator PSMiner is 60.4 times higher than FINGERS on average.

[0126] Fig.12 A performance comparison chart of the PSMiner architecture of the hardware acceleration device provided in an embodiment of the present application compared with the accelerator architecture in the related art is shown. Fig.12 The PSMiner-N architecture is a hardware accelerator architecture in which the processing unit in the hardware accelerator does not include the redundant detector and binary search unit provided in the embodiments of the present application, the PSMiner-R architecture is a hardware accelerator architecture in which the processing unit in the hardware accelerator includes the redundant detector provided in the embodiments of the present application, and the PSMiner architecture is a hardware accelerator architecture in which the processing unit in the hardware accelerator includes the redundant detector and binary search unit provided in the embodiments of the present application.

[0127] like Fig.12As shown, PSMiner-R has an average performance improvement of 3.0 times compared to PSMiner-N, and the performance improvement mainly comes from the detection and reduction of redundant set calculations by the redundant detector. PSMiner has an average performance improvement of 5.0 times compared to PSMiner-R, and the performance improvement mainly comes from using the pipeline-based binary search unit provided in the embodiment of the application to accelerate the binary search algorithm.

[0128] An embodiment of the present application also provides a computing device, including at least one processor, a memory, a hardware accelerator, and a communication interface.

[0129] Fig.13 A schematic diagram of the structure of a computing device provided in an embodiment of the present application.

[0130] like Fig.13 As shown, the computing device 1300 includes at least one processor 1301, a memory 1302, a hardware accelerator 1303 and a communication interface 1304. Among them, the processor 1301, the memory 1302, the hardware accelerator 1303 and the communication interface 1304 are connected in communication, and the communication connection can be realized by wired means (such as a bus) or by wireless means. The communication interface 1304 is used to send and / or receive data sent by other devices; the hardware accelerator 1303 is the PSMiner architecture mentioned above, which can realize the function of the acceleration device for graph data processing mentioned above; the memory 1302 stores computer instructions, and the processor 1301 executes the computer instructions to execute the acceleration method for graph data processing in the aforementioned method embodiment, which is combined with the hardware accelerator to eliminate redundant matching in the dynamic graph pattern matching process, and reduce the redundant set calculation in the graph matching process, and increase the efficiency of graph matching, so as to meet some application scenarios that require high-performance dynamic graph pattern matching, such as anomaly detection, financial fraud detection and social network analysis, etc.

[0131] It should be understood that in the embodiment of the present application, the processor 1301 may be a central processing unit CPU, and the processor 1301 may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0132] The memory 1302 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1301. The memory 1302 may also include a nonvolatile random access memory.

[0133] The memory 1302 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DRRAM).

[0134] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer instructions are executed by a processor, the above-mentioned method is implemented.

[0135] An embodiment of the present application provides a chip, which includes at least one processor and an interface, wherein the at least one processor determines program instructions or data through the interface; the at least one processor is used to execute the program instructions to implement the method mentioned above.

[0136] An embodiment of the present application provides a computer program or a computer program product, wherein the computer program or the computer program product comprises instructions, and when the instructions are executed, the computer is caused to execute the above-mentioned method.

[0137] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0138] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented as a software module executed by hardware, a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0139] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation method of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An acceleration device for graph data processing, characterized in that: include: At least one processing unit, wherein each processing unit is used to process the matching task of the update edge in the data graph and the matching sequence corresponding to the pattern graph to obtain a graph matching result.

2. The device according to claim 1, characterized in that The pattern graph includes a plurality of nodes and connection edges connecting different nodes; The matching sequence corresponding to the pattern graph includes multiple matching sequences generated with each connecting edge in the pattern graph as a starting edge.

3. The device according to claim 2, characterized in that The matching sequence corresponding to the pattern graph is obtained by pruning the multiple matching sequences based on a symmetric sequence, wherein two matching sequences that are mutually symmetric sequences have the same isomorphic subgraphs obtained by matching.

4. The device according to any one of claims 1 to 3, characterized in that: The matching task execution process includes executing a number of set operation tasks, and the operation objects of the set operation tasks include the neighbor node sets of two nodes in the data graph; Each of the processing units comprises: A binary search unit, configured to process a first pending set operation task, wherein an operation object of the first pending set operation task includes a first set and a second set, and a length of the first set is greater than a length of the second set; The binary search unit is subjected to hardware pipeline processing, so that the binary search unit processes multiple data in parallel during the process of processing the first to-be-processed set operation task.

5. The device according to claim 4, characterized in that The binary search unit is used to process the first pending set operation task as follows: Convert the first set into a binary search tree for representation, wherein the node values ​​in the binary search tree are determined based on the elements in the first set, each node value in the binary search tree is greater than all node values ​​of a left subtree corresponding to each node, and each node value in the binary search tree is less than all node values ​​of a right subtree corresponding to each node; Dividing the second set to obtain at least one data block, each data block in the at least one data block includes a number of elements in the second set; For each data block, each data block is compared and calculated in parallel with the node values ​​of the first N layers of the binary search tree to obtain a first comparison calculation result, where N is a positive integer greater than 1.

6. The device according to claim 5, characterized in that The comparison calculation results of each data block and the node value of the i-th layer in the first N layers of the binary search tree are determined based on the elements in each data block and the comparison array of the i-th layer, and the comparison array of the i-th layer is determined by the index array of the previous layer and the node value of the i-th layer, and the index array of the previous layer is determined based on the first comparison calculation results of all layers before the i-th layer.

7. The device according to claim 5 or 6, characterized in that The processing of the first pending set operation task by the binary search unit further includes: Based on the index array of the Nth layer, matching the elements in each data block to the corresponding subspace of the first set for comparison and calculation, to obtain a second comparison and calculation result, where the subspace of the first set is obtained by segmenting the elements corresponding to each node of the binary search tree; Based on the first comparison calculation result and the second comparison calculation result, a processing result of the first to-be-processed set operation task is determined.

8. The device according to any one of claims 4 to 7, characterized in that: Each of the processing units further comprises: The temporary register memory is used to store data that has been read by the binary search unit a number of times greater than or equal to a second preset threshold.

9. The device according to any one of claims 4 to 8, characterized in that: Each of the processing units further comprises: Merge calculation unit; A collection scheduler, used for respectively evaluating the time cost of the merge calculation unit processing the pending collection operation task and the time cost of the binary search unit processing the pending collection operation task based on the collection operation cost evaluation model; Based on the time cost, the to-be-processed set operation task is allocated to the merge calculation unit for processing or to the binary search unit for processing.

10. The device according to claim 9, characterized in that The construction of the collection computing overhead evaluation model is related to time complexity and hardware performance. The time complexity indicates the time complexity of the collection operation task to be processed. The hardware performance includes first hardware performance and second hardware performance. The first hardware performance includes one or more of the number of parallel processing sub-units and hardware frequency of the merge computing unit. The second hardware performance includes one or more of the number of parallel processing sub-units, hardware access delay and pipeline depth of the binary search unit.

11. The device according to any one of claims 1 to 10, characterized in that: Each of the processing units further comprises: A redundancy detector is used to detect the number of times each set operation task is repeatedly processed during the execution of the matching task, and cache the processing result of the target set operation task based on the number of repeated processing, and the number of times the target set operation task is repeatedly processed meets a preset condition.

12. The device according to claim 11, characterized in that The preset condition includes a number of repeated processing times greater than a preset percentage of the number of repeated processing times of each of the collective operation tasks; Alternatively, the preset condition includes being greater than or equal to a first preset threshold.

13. The device according to claim 11 or 12, characterized in that The redundant detector is specifically used for: It is detected that the processing result of the pending collective operation task is cached, and the processing result of the pending collective operation task is sent to the core of the processing unit where the redundancy detector is located.

14. The device according to any one of claims 11 to 13, characterized in that: The redundant detector is also used for: It is detected that the processing result of the pending collection operation task is not cached, and a request message is sent to the collection scheduler, wherein the request message carries the identifier of the pending collection operation task, and the request message is used to request the collection scheduler to schedule the pending collection operation task.

15. The device according to any one of claims 11 to 14, characterized in that: Each of the processing units further comprises: Private cache; The redundant detector is also used for: Maintaining a first hash table in the private cache, wherein the first hash table records the target set operation task and the cache address of the processing result of the target set operation task; And / or, a second hash table is maintained in the private cache, wherein the second hash table records cache addresses of the respective set operation tasks and the number of times the respective set operation tasks are repeatedly processed.

16. The device according to any one of claims 1 to 15, characterized in that Also includes: A scheduler is used to schedule update edges that are neighboring edges in the data graph to the same processing unit in the at least one processing unit for processing.

17. A method for accelerating graph data processing, characterized in that: The acceleration device for graph data processing is applied to the acceleration device for graph data processing, the acceleration device for graph data processing includes at least one processing unit, and the method includes: Each of the at least one processing unit processes the matching task of the update edge in the data graph and the matching sequence corresponding to the pattern graph to obtain a graph matching result.

18. The method according to claim 17, characterized in that The pattern graph includes a plurality of nodes and connection edges connecting different nodes; The matching sequence corresponding to the pattern graph includes multiple matching sequences generated with each connecting edge in the pattern graph as a starting edge.

19. The method according to claim 18, characterized in that The matching sequence corresponding to the pattern graph is obtained by pruning the multiple matching sequences based on a symmetric sequence, wherein two matching sequences that are mutually symmetric sequences have the same isomorphic subgraphs obtained by matching.

20. The method according to any one of claims 17 to 19, characterized in that: The matching task execution process includes executing a number of set operation tasks, and the operation objects of the set operation tasks include the neighbor node sets of two nodes in the data graph; Each of the processing units includes a binary search unit, and the method further includes: Processing a first pending set operation task by a binary search unit, wherein an operation object of the first pending set operation task includes a first set and a second set, and a length of the first set is greater than a length of the second set; The binary search unit is subjected to hardware pipeline processing, so that the binary search unit processes multiple data in parallel during the process of processing the first to-be-processed set operation task.

21. The method according to claim 20, characterized in that The first pending set operation task is processed by the binary search unit as follows: Convert the first set into a binary search tree for representation, wherein the node values ​​in the binary search tree are determined based on the elements in the first set, each node value in the binary search tree is greater than all node values ​​of a left subtree corresponding to each node, and each node value in the binary search tree is less than all node values ​​of a right subtree corresponding to each node; Dividing the second set to obtain at least one data block, each data block in the at least one data block includes a number of elements in the second set; For each data block, each data block is compared and calculated in parallel with the node values ​​of the first N layers of the binary search tree to obtain a first comparison calculation result, where N is a positive integer greater than 1.

22. The method according to claim 21, characterized in that The comparison calculation results of each data block and the node value of the i-th layer in the first N layers of the binary search tree are determined based on the elements in each data block and the comparison array of the i-th layer, and the comparison array of the i-th layer is determined by the index array of the previous layer and the node value of the i-th layer, and the index array of the previous layer is determined based on the first comparison calculation results of all layers before the i-th layer.

23. The method according to claim 20 or 21, characterized in that The processing of the first pending set operation task by the binary search unit further includes: Based on the index array of the Nth layer, matching the elements in each data block to the corresponding subspace of the first set for comparison and calculation, to obtain a second comparison and calculation result, where the subspace of the first set is obtained by segmenting the elements corresponding to each node of the binary search tree; Based on the first comparison calculation result and the second comparison calculation result, a processing result of the first to-be-processed set operation task is determined.

24. The method according to any one of claims 20 to 23, characterized in that: Each of the processing units also includes a temporary register memory, and the method further includes: The data read by the binary search unit for a number of times greater than or equal to a second preset threshold is cached in the temporary register memory.

25. The method according to any one of claims 20 to 24, characterized in that: Each processing unit further includes a merge calculation unit and a collection scheduler, and the method further includes: Sending the pending set operation task to the set scheduler, so that the set scheduler can evaluate the time cost of the merge calculation unit processing the pending set operation task and the time cost of the binary search unit processing the pending set operation task based on the set operation cost evaluation model; Based on the time cost, the to-be-processed set operation task is allocated to the merge calculation unit for processing or to the binary search unit for processing.

26. The method according to claim 25, characterized in that The construction of the collection computing overhead evaluation model is related to time complexity and hardware performance. The time complexity indicates the time complexity of the collection operation task to be processed. The hardware performance includes first hardware performance and second hardware performance. The first hardware performance includes one or more of the number of parallel processing sub-units and hardware frequency of the merge computing unit. The second hardware performance includes one or more of the number of parallel processing sub-units, hardware access delay and pipeline depth of the binary search unit.

27. The method according to any one of claims 17 to 26, characterized in that: Each of the processing units further includes a redundancy detector, and the method further includes: The redundancy detector detects the number of times each set operation task is repeatedly processed during the execution of the matching task, and caches the processing result of the target set operation task based on the number of repeated processing. The number of times the target set operation task is repeatedly processed meets the preset conditions.

28. The method according to claim 27, characterized in that The preset condition includes a number of repeated processing times greater than a preset percentage of the number of repeated processing times of each of the collective operation tasks; Alternatively, the preset condition includes being greater than or equal to a first preset threshold.

29. The method according to claim 27 or 28, characterized in that Also includes: When the redundancy detector detects that the processing result of the to-be-processed collective operation task is cached, the processing result of the to-be-processed collective operation task is sent to the core of the processing unit where the redundancy detector is located.

30. The method according to any one of claims 27 to 29, characterized in that: Also includes: When the redundancy detector detects that the processing result of the pending collection operation task is not cached, it sends a request message to the collection scheduler, wherein the request message carries the identifier of the pending collection operation task, and the request message is used to request the collection scheduler to schedule the pending collection operation task.

31. The method according to any one of claims 27 to 29, characterized in that: Each processing unit further includes a private cache, and the method further includes: Maintaining a first hash table in the private cache, wherein the first hash table records the target set operation task and the cache address of the processing result of the target set operation task; And / or, a second hash table is maintained in the private cache, wherein the second hash table records cache addresses of the respective set operation tasks and the number of times the respective set operation tasks are repeatedly processed.

32. The method according to any one of claims 17 to 31, characterized in that: The acceleration device for graph data processing further includes a scheduler, and the method further includes: The scheduler schedules the update edges of neighboring edges in the data graph to the same processing unit in the at least one processing unit for processing.

33. An acceleration chip for graph data processing, comprising a memory and at least one processing unit, characterized in that: Each of the at least one processing unit is used to process a matching task of updating edges in the data graph and a matching sequence corresponding to the pattern graph to obtain a graph matching result.

34. A computing device comprising a memory and a processor, characterized in that: Instructions are stored in the memory, and when the instructions are executed by the processor, the method according to any one of claims 17 to 32 is implemented.

35. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 17 to 32 is implemented.

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